JPS6152725A - Timer counter - Google Patents

Abstract

PURPOSE:To obtain a free running timer counter for which the overhead of a CPU is small, by using two comparator registers for switching between up- counting and down-counting of an up/down counter (U/DCNT). CONSTITUTION:An upper limit value alpha and a lower limit value beta are written on comparator registers 22 and 23 respectively by a CPU1. When an U/DCNT21 starts counting at a time t0 in the up-counting mode, the value alpha of the comparator register 22 and the value of the U/DCNT21 coincide with each other at a time t1, and an AND24 outputs the output to set a flip flop 26, and the U/ DCNT21 is st to the down-counting mode. When the counted value is reduced to reach the value beta of the comparator register 23, the flip flop 26 is reset to set the U/DCNT21 to the up-counting mode. During this period, the U/DCNT21 passes counted value ''0'', and the output signal is inverted at each time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a free-running timer counter used in a single-chip microcomputer.

Problems to be Solved by the Prior Art and the Invention In single-chip microcomputers, in order to generate time intervals at arbitrary duties, generate pulses at arbitrary frequencies, monitor external events, monitor pulse width (frequency), etc. A timer counter is essential. As such timer counters, there are a counter type and a free running counter type.

The counter-type timer counter includes a down counter (or up counter), a reload register, and the like. For example, in this case, when the down counter underflows after counting a predetermined clock, the carried coefficient is generated as an interrupt signal to the CPU, and the contents of the reload register are set to the down counter again and the same operation continues. I will do it. Therefore, by resetting (or setting) the flip 70 sof using the above-mentioned carry-out signal, a signal of any duty can be generated. In this case, setting (or resetting) of flip-flops i, j: is performed by the CPU or other means. However, such counter-type time counters are used for one purpose, so if two different arbitrary duty signals are required, two timer counters are required, which means that the number of purposes increases. In this case, the time counter must be increased, which is disadvantageous in terms of manufacturing costs.

On the other hand, a free running time counter,
It is composed of a free-running counter, a comparator register, a matching circuit, etc., and even if the purpose of use increases, the free-running counter can be used in common, so it is cheaper than a counter-type time counter in terms of manufacturing cost. It's advantageous. However, in this free-running time counter, when generating a signal of any duty or company with any frequency, for example, a signal with /4 pulse width Δt, the current value t of the 7-leaving running counter is set to pulse width Δt in the comparator register. The value t + Δt must be set by adding Δt, and the above addition must be performed every time an interrupt signal of the time counter is generated, and then the value must be set in the comparator register. As a result, there was a problem that the CPU overhead increased.Means for resolving the problem In view of the above-mentioned problems, the present invention provides a free-running time counter with less CPU overhead. The means includes an up/down counter that counts up or down by counting a predetermined clock, a first comparator register in which an upper limit value of the count value of the up/down counter is set, and a counter of the up/down counter. The second, where the lower limit of the numerical value is set.
When the count value of the first comparator register and the up/down counter match the set value of the first comparator register, the up/down counter is put into the down counting mode, and the 5th value of the up/down counter is set. means for setting the up/down counter to an up counting mode when the set value of the second comparator register matches the set value of the second comparator register;
This is achieved by a timer counter that outputs a signal according to the bit indicating the sign of the down counter.

Effect.

In the above arrangement, once desired values are set in w, the first and second comparator registers by, for example, the CPU, the time counter changes the duty or frequency according to the desired values without the intervention of the CPU. It will generate a signal.

Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block circuit diagram showing a single-chip microcomputer including a timer counter according to the present invention. In the first part, 1 is a CPU, 2 is a timer counter, 3 is a ROM that stores programs, fixed data, etc.
Reference numeral 4 indicates an input/output (ILO) interface for connecting to an external device such as a memory M for storing temporary data, and an input/output (ILO) interface for connecting with an external device such as a computer 6. A path 7 connects each of these elements. The internal clock generation circuit 8 supplies various internal clocks to necessary internal devices such as the CPU 1 and the timer counter 2.

FIG. 2 is a detailed block circuit diagram of the timer counter 2 of FIG. 1. In FIG. 2, 21 is an up/down counter which counts the clock signal CLK of the internal clock generating circuit 8 and counts up or down. 22 and 23 are comparator registers in which the CPU 1 sets an upper limit value α and a lower limit value β of the up/down counter 21, respectively. The coincidence circuit 24 inputs the contents of the up/down counter 21 (
all bits) and the contents of the comparator register 22 (all bits 2)
When these contents completely match, a set signal is generated to the 7 lip-flop 26 to set it. In addition, the matching circuit 25
monitors whether the contents of the up/down counter 21 (all bits) and the contents of the comparator register 23 (all bits) match, and when these contents match the prepayment, the flip-flop 26 is reset. Generate a signal to reset it. Timer counter 2 output OUT
is a pitch i indicating the positive/negative sign of the up/down counter 21
− is done.

FIG. 3 is a timing diagram for explaining the operation of the timer counter 2 of FIG. 2. Up/down counter 21
In the up counting mode, the contents of are increased from time t0, and at time t, the contents of the up/down counter 21 reach the upper limit value α (positive value) of the comparator register 22.
matches.

As a result, the coincidence circuit 24 sets the 7-lig flop 2G, so that the up/down counter 21 is switched from the up counting mode to the down counting mode. Therefore, after time t8, the content of the up/down counter 21 decreases.

At time t2, when the content of the up/down counter 21 crosses zero, the output signal OUT changes from "1" to On. Furthermore, at time t3, the content of the up/down counter 21 reaches the lower limit value β of the comparator register 23. (
pattern value).

As a result, the coincidence circuit 25 resets the F-flop 26, so that the up/down counter 21 is switched from the down counting mode to the up counting mode. Therefore, after time t, the contents of the up/down counter 21 increase.

Then, at time t4, the up/down counter 2
When the content of 1 crosses zero, the output signal OUT changes from '0' to 1s.

The same behavior continues thereafter. In other words, rneeti ratio α/(α
+β) signal OUT is generated.

In the above embodiment, the output signal OUT of the timer counter 2 is sent to the outside via the I10 interface 5, but this signal OUT'1 can act as an interrupt to execute the interrupt route. is also possible.

As described in detail, according to the present invention, once set in the comparator register, it is possible to automatically generate a signal with a desired density or frequency. When applied to a chip microcomputer, the CPU overhead can be reduced by Z.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a single-chip microcomputer including a timer counter according to the present invention, and FIG.
This figure is a basic block circuit diagram of the timer counter 2 of FIG. 1, and FIG. 3 is a timing diagram for explaining the operation of the timer counter 2 of FIG. 2. 1: CPtJ, 2: timer counter, 3: R
OM14: RAM, 5: I10 interface, 8: Internal clock generation circuit, 21: Up/down counter, 22, 23: Controller register, 24
゜25 matching circuit, 26: flip-flop, α: upper limit, β: lower limit.

Claims (1)

[Claims] 1. An up/down counter that counts up or down by counting a predetermined clock, a first comparator register in which an upper limit value of the count value of the up/down counter is set, and an upper limit value of the count value of the up/down counter. When the count value of the second comparator register in which the lower limit value is set and the up/down counter match the set value of the first comparator register, the up/down counter is put into the down counting mode, and the up/down counter and means for setting the up/down counter to an up counting mode when the counted value of the down counter matches the set value of the second comparator register, and according to a bit indicating a positive or negative sign of the up/down counter. A timer counter that outputs a signal.