JP3903607B2 - Pulse count method in pulse input circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse count method in a pulse input circuit of a microcomputer apparatus equipped with a pulse input circuit used for measurement control.
[0002]
[Prior art]
In a pulse input circuit mounted on a microcomputer (CPU) used for measurement control, the number of pulses (number of falling edges of a pulse) generated within a certain time and a pulse interval (following from the falling edge of a pulse) (Time until the falling edge) is calculated.
[0003]
FIG. 5 shows a conventional pulse input circuit, and FIG. 6 shows a timing chart thereof. In FIG. 5, reference numeral 50 denotes a pulse input circuit mounted on the CPU 1, which includes a pulse detection circuit 51, a clock counter 52, a reference timer circuit 53, a read register 54, and the like.
[0004]
The pulse detection circuit 51 samples a pulse input signal with a basic clock signal, and receives an input pulse detection signal for interrupting the CPU 1 and a data latch signal for latching the output data of the clock counter 52 in the read register 54. Generate.
[0005]
The clock counter 52 is a counter that counts for each basic clock signal with a predetermined bit width. The reference timer circuit 53 is an interval timer that counts the basic clock signal and interrupts the CPU 1 at regular intervals. The read register 54 latches the data input from the clock counter 52 by the data latch signal from the pulse detection circuit 51 and realizes an external interface with the CPU 1.
[0006]
When the pulse detection circuit 51 detects the falling edge of the pulse input signal, the data of the clock counter 52 is latched in the read register 54 by the data latch signal. Further, an interval timer interrupt is given to the CPU 1 by a timer interrupt signal from the reference timer 53.
[0007]
When the CPU 1 accepts the input pulse detection signal interrupt, the CPU 1 reads the data in the read register 54 and obtains the pulse interval by obtaining the difference between the previous value and the current value of the read data. Further, the number of pulses generated in a certain time is obtained by counting interrupts by pulse signals generated during the timer interrupt from the reference timer 53. Also, the accumulated data is obtained by adding the pulse intervals between them.
[0008]
[Problems to be solved by the invention]
In a measurement control system using a pulse input circuit, improvement in the accuracy of the pulse input circuit is required in order to increase the accuracy of the entire system. In order to increase the accuracy of the pulse input circuit, the frequency of the reference clock signal must be increased to reduce the sampling period.
[0009]
However, in the conventional pulse input circuit, if the sampling frequency is shortened by increasing the clock frequency, new data is latched within the time from when the read register 54 latches data until the data is read. For example, in FIG. 6, when data (f2 + g + h + i) is read, new data j may be latched as in (f2 + g + h + i + j), and accurate data cannot be read.
[0010]
The present invention has been made in view of the above problems, and the object of the present invention is to provide a pulse count in a pulse input circuit that can accurately read data of a pulse counter and a pulse interval counter even when the clock frequency is high. To provide a method.
[0011]
[Means for Solving the Problems]
The pulse count method in the pulse input circuit of the present invention is a pulse detection circuit that samples an input pulse signal with a fundamental clock signal to obtain an input pulse detection signal, and counts the input pulse detection signal controlled by a control signal of a fixed period. In a pulse input circuit having a pulse counter and a pulse interval counter that is controlled by a control signal having a constant period and counts a reference clock signal, two pulse counters and two pulse interval counters are provided, and each of the two counters is constant. The pulse counter and the pulse interval counter can be accurately counted even when the frequency of the basic clock signal is high.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
FIG. 1 shows a pulse input circuit according to the first exemplary embodiment. 11 is a pulse detection circuit, 12 is a reference timer circuit, 13A and 13B are alternately selected pulse counters A and B, 14A and 14B are alternately selected pulse interval counters A and B, and are integrated counters A and B, respectively. It has the function of. Reference numerals 15 and 16 denote control signal inversion inverters.
[0013]
Hereinafter, the configuration of the pulse input circuit will be described together with the operation using the timing chart of FIG.
[0014]
The pulse detection circuit 11 samples the input pulse signal A by the basic clock signal A, detects the falling edge of the input pulse signal A after the switching of the reference timer signal H as a pulse break, and inputs it for each pulse. A pulse detection signal c is generated.
[0015]
The reference timer circuit 12 has a reference timer circuit for generating a fixed period signal H from the basic clock signal A. From the reference timer signal H, the input pulse signal A, and the basic clock “A”, the pulse counters 13A and 13B and the pulse interval counter are provided. 14A and 14B control signals A and B switching signal D, A and B counter output enable signal E, A group counter (13A and 14A) clear signal, B group counter (13B and 14B) clear signal key Generate. Further, after outputting each data signal, an interrupt signal is generated. The AB switching signal D is inverted by the inverters 15 and 16 to become a signal D 'and is input to the counters 13B and 14B.
[0016]
The pulse counters 13A and 13B are regularly and alternately selected by the AB switching signals D and D 'and perform a counting operation. The pulse counter 13A or 13B selected by the AB switching signal D or D 'counts up the input pulse detection signal C. In response to the AB counter output enable signal O, pulse counter data “K” is output. When the A group clear signal or the B group clear signal is asserted, the counter value is cleared to O.
[0017]
The pulse interval counters 14A and 14B are regularly and alternately selected by the AB switching signals D and D ', and the selected pulse interval counter 14A or 14B counts up the basic clock signal A. In response to the AB counter output enable signal O, the pulse interval counter data “Q” is output. When the A group clear signal or the B group clear signal is asserted, the counter value is cleared to O.
[0018]
When the pulse counter 13A and the pulse interval counter 14A output each data, the pulse counter 13B and the pulse interval counter 14B are disabled by the AB switching signal D 'and the AB counter output enable signal O.
[0019]
Similarly, when the pulse counter 13B and the pulse interval counter 14B output each data, the pulse counter 13A and the pulse interval counter 14A are disabled by the AB switching signal D and the AB counter output enable signal O. Yes.
[0020]
Therefore, when the CPU 1 reads the pulse count data “K” and the pulse interval count data “K” after outputting the interrupt signal, the data of the A group counters 13A and 14A and the B group counters 13B and 14B collide. Normal data can be read without doing this.
[0021]
By switching the A and B group counters at regular intervals, the pulse counter and the pulse interval counter are always operated during the time when the CPU 1 reads the pulse count data “K” and the pulse interval count data “K”. Therefore, each data can be counted accurately even when the number of basic clock periods becomes high.
[0022]
With the above operation, the pulse counter and the pulse interval counter can accurately count even when the frequency of the basic clock “a” is increased.
[0023]
Embodiment 2
FIG. 3 shows a pulse input circuit according to the second embodiment. 31 is a pulse detection circuit, 32 is a reference timer circuit, 33A and 33B are alternately selected pulse interval counters, 34A and 34B are alternately selected, and pulse counters 35A and 35B are alternately selected adders. It has a counter function. 36 is a pulse counter read register, 37 is an integration counter read register, and 41, 42 and 43 are inverters for inverting the control signal.
[0024]
Hereinafter, the configuration of this pulse input circuit will be described together with the operation using the timing chart of FIG.
[0025]
The pulse detection circuit 31 samples the input pulse signal A using the basic clock signal A, detects the falling edge of the input pulse signal A as a pulse break, and generates an internal pulse signal (pulse detection signal) for each pulse. Generate. A plurality of control signals are generated in combination with the timer control signal.
[0026]
The plurality of generated control signals are a pulse interval counter switching signal to the pulse interval counters 33A and 33B, a counter A / B output control signal, a counter A clear signal S, and a counter B clear signal. The signal is inverted by the inverter 41 to become a signal 'and input to the counter 33B.
[0027]
The reference timer circuit 32 has a reference timer for generating a fixed period signal from the basic clock signal A, and outputs A / B system switching signal D and AB system outputs which are control signals of the pulse counters 34A and 34B and the adders 35A and 35B. A control signal O, an A system clear signal F, and a B system clear signal K are generated. The signal D is inverted by the inverters 42 to 43 to become a signal A ′, which is input to the counter 34B and the adder 35B. Further, the register update signal Z of the read registers 36 and 37 and the interrupt signal for the external CPU are generated.
[0028]
In addition, the pulse detection circuit 31 recognizes that the counters 35A and 35B are being updated based on the timer control signal output from the reference timer 32 and the counter A / B output switching control signal set, and detects the internal pulse signal signal. Delay.
[0029]
The pulse interval counters 33A and 33B are counters that measure the pulse interval by counting the basic clock signal A. Each of the counters 33A and 33B counts alternately for each pulse by a pulse interval counter switching signal output from the pulse detection circuit 31. Further, after the counting of one pulse is completed, data is sent to the adders 35A and 35B, and then cleared by the respective counter clear signals or.
[0030]
The adders 35A and 35B have a function of integrating the data “te” output from the pulse interval counters 33A and 33B. The adders 35A and 35B are switched at a constant cycle by an A / B system switching signal D output from the reference timer circuit 32 and its inverted signal D ′. Further, after the accumulated counter read register 37 data “NA” is latched, it is cleared to 0 by the respective clear signals K and K.
[0031]
The pulse counters 34A and 34B are counters that measure the number of input pulse signals A by counting the internal pulse signals from the pulse detection circuit 31. The counters 34A and 34B are switched at a constant cycle by an A / B system switching signal D output from the reference timer detection circuit 32. Further, after the data “g” is latched in the pulse counter read register 36, it is cleared to 0 by the respective clear signals K and K.
[0032]
The pulse counter reading register 36 and the integration counter reading register 37 are updated at a constant cycle by a register update signal output from the reference timer circuit 32, and realize an interface with an external CPU.
[0033]
As described above, since there are two pulse interval counters and two pulse counters to switch between them, it takes enough time to transfer data to the adder after the count is completed. Can be measured.
[0034]
【The invention's effect】
Since the present invention has two pulse counters and two pulse interval counters, and each is used by switching alternately, even if the basic clock frequency is high, the pulse count and pulse interval count data can be accurately obtained. Can be read. Therefore, when the control is performed using the pulse count data and the pulse interval count data, a higher basic clock frequency can be used, so that more precise control is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram of a pulse input circuit according to a first embodiment.
FIG. 2 is a timing chart of the pulse input circuit.
FIG. 3 is a block diagram of a pulse input circuit according to the second embodiment.
FIG. 4 is a timing chart of the pulse input circuit.
FIG. 5 is a block diagram of a pulse input circuit according to a conventional example.
FIG. 6 is a timing chart of the pulse input circuit.
[Explanation of symbols]
1 ... CPU
11 ... Pulse detection circuit 12 ... Reference timer circuits 13A, 13B ... Pulse counters A, B
14A, 14B ... Pulse interval counter A, B
31 ... Pulse detection circuit 32 ... Reference timer circuits 33A, 33B ... Pulse interval counters A, B
34A, 34B ... Pulse counter A, B
35A, 35B ... Adders A, B (integration counters A, B)
36 ... Pulse counter read register 37 ... Integration counter read register 51 ... Pulse detection circuit 52 ... Clock counter 53 ... Reference timer circuit 54 ... Read register

Claims (1)

A pulse detection circuit that samples an input pulse signal with a fundamental clock signal to obtain an input pulse detection signal; and
A pulse counter controlled by a control signal of a constant period and counting an input pulse detection signal;
In a pulse input circuit having a pulse interval counter that is controlled by a control signal of a fixed period and counts a reference clock signal,
Two pulse counters and two pulse interval counters are provided,
The pulse count in the pulse input circuit is characterized in that each of the two counters is alternately operated at a constant cycle so that the pulse counter data and the pulse interval counter data can be accurately read even if the frequency of the basic clock signal is high. method.

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