SU1210099A1 - Speed meter with quasi-constant measuring error - Google Patents

Abstract

The device relates to information conversion technology, and more specifically to digital means of measuring speed. The purpose of the invention is to improve measurement accuracy over a wide range of measured speeds. The meter circuit contains a pulse speed sensor 1, a reference frequency generator 2, triggers 4 and 5, a delay element 6, a period number counter 7, a memory arithmetic unit 8 including registers 9 and 10 intermediate memory, a magnitude device 11 and a division device 12, in the code reading device 13, frequency divider 14, reset pulse generator 15, bus 16. Register selection flip-flop 5 switches when counter 3 overflows, therefore in register 9 (10) there remains the last code value of the current time that was written before erepolneniyu. When switching registers, recording is similarly performed in the second register. By the time of the next overflow of the counter 3 i (L

Description

The ipasHOCTb codes in registers 9 (10) represent the code for the value of the sum of the sensor periods between the two replica devices. The device relates to information conversion technology, and more specifically to digital speed measurement tools.

The purpose of the invention is to improve the measurement accuracy in a wide range of measured speeds.

The drawing shows a diagram of the meter.

The circuit contains a pulse-speed sensor, a generator 2 of the reference frequency, a counter-driver 3 period codes (counter), triggers 4 and 5, a delay JMeHT 6, a counter 7 the number of periods, an arithmetic unit 8 with memory, including registers 9 and 1 an intermediate memory, a magnitude device 11 and a dividing device 12, an output reading device 13, a frequency divider 14, a reset pulse generator 15 connected to a reset bus 16.

The meter works as follows.

Counter 3 is continuously filled with pulses of the reference frequency generator 2, so that at its pulse output an overflow pulse periodically appears with a periodicity of the cycle Tc Tp-2, where T is the period of the frequency of the reference generator 2, and n is the number of binary bits of the counter 3. Thus, with discreteness in TD, the current time code appears at the information outputs of counter 3. The overflow pulse each time through the counting input triggers the trigger 5. The latter causes the input signal to write to the V inputs of the intermediate memory registers in turn, but the absence of signals on the clocked C-loop does not write ™ dits.

Sensor 1 pulses enter the meter circuit via a synchronous node

12f0099

nor mi. The outgoing code is proportional to the frequency of the sensor, and therefore to the speed of rotation or movement. 1 il.

on the trigger 4. In order to avoid the coincidence of the moment of arrival of the sensor pulse front with the oscillating pulse fronts of the generator 2, the sensor signals from the D-input switch trigger 4 into a single state. Trigger zeroing is performed at the leading edge of the generator 2 pulses, taking into account the delay introduced by element 6. The leading edge of the signal, which appears on the inverse output of trigger 5, is used as a clock, records the number of periods in the counter 7, and writes the code value the current time in that of the registers, on the V-input of which there is a permission signal from trigger 5 (trigger, register selection). The width of the counter 3 and the frequency of the generator 2 are chosen such that T T, where T. is the maximum value of the period of the measured frequency. Each subsequent sensor pulse causes the transfer of the values of the current time code to the specified register, updating the previously recorded information.

Since the register selection trigger 5 switches at the moment of the overflow of the counter 3, then in the register 9 (10) there remains the recorded last code value of the current time, the recording of which preceded the overflow. After switching registers, the recording of the current time code is similarly made to the second of the registers, in which by the time of overflow of the counter 3 the last record also remains.

It is obvious that by the time of the next counter overflow, the difference between the current time codes recorded in registers 9 and 10 is, at a certain scale, the code of the value of the sensor pulse periods, cyMMbJ, elapsed between the two overflows:

rn

-N, kZ: T

lo

Ul

15

where i 1, 2, 3, ..., ha;

Td. Is the i -th period of the sensor pulses; K - coefficient of proportionality, determined by the level of the reference frequency. With a uniform following of the sensor pulses and the equality of the values of the periods

N, - N, KmT. The overflow pulse of the counter 3 is fed to the clock input of the subtracting device 11 and causes the rewriting of the values of the codes Nq and N, n about the inputs to be reduced and subtracted into the device 11, where the operation of subtracting N, - N, o is performed, so that the input of the divider code of the device 12 dividing the value of K m. The value of t is supplied to the input of the dividend code from the outputs of the period counter. As a result of the Dividing operation, the output code of the device 12 arriving at the code reading device 13 is expressed as:

in

one

to m t,

K T „

 K, -f

where fа is the pulse frequency of the sensor; K - coefficient of proportionality.

Thus, the output code is proportional to the frequency of the sensor, and therefore, on a certain scale, to the speed of its rotation or movement.

Claims (1)

Invention Formula A speed viewer with a quasi-constant measurement error, which contains a pulse speed sensor, a reference frequency generator, a period code generator, an output reading device, is different. with the aim of increasing the accuracy of measurement in a wide range of measured orosti, the shaper of the period code is made in the form of a counter with counting and setting inputs with information and pulse traces of subsequent bits, and VNIISH Order 513/53 Circulation 778 Subscription Branch PPP Patent, Uzhgorod, ul, Proektna, 4 s , 10099 The circuit additionally introduces the first and second triggers with controlling, clocking and setting inputs each, a delay element, a generator, 5 reset pulses connected to the reset bus-, a frequency divider, a counter for the number of periods with counting and installation inputs, an arithmetic unit with a memory, including to the first and second intermediate memory registers with information inputs of recording, resolution and setting MJi inputs each, a subtractor with information inputs of a code 15 and a decrementable code of the readable, clocking and installation inputs, a device of division with the information inputs of a dividend code and a divisor code , with the reference generator Frequency 20 is connected to the counting input of the period code generator and, through a delay element, to the counting input of the first trigger, a pulse sensor, to the control D input of the same trigger repaj whose inverse output is connected to the counting input of the count of the number of periods and the inputs of the intermediate registers memory, pulse output for1 Shrovatel period code 20 is connected to the clock inputs of the frequency divider, the subtractor and the second trigger, the direct and inverse outputs, which are connected to the resolution of the first and second registers, respectively, the information outputs of the period code generator are connected in parallel to the information inputs of both memory registers , the outputs of the first of them are connected to the information inputs of the code being reduced, and the outputs of the second are connected to the inputs of the code of the subtracted subtraction device, the outputs of the latter are connected to the information inputs of the divider code, and the outputs of ticker of the number of periods - to the inputs of the divisible divider device code, the information outputs of the latter are connected to the information inputs of the output reading device, the clocking input of which is connected to the output of the division 1-: frequency bodies, the installation inputs of triggers, registers, counter, driver, subtractors and dividers connected to tire reset. 35 40 45 50