JPS6314264A - Dma processing system - Google Patents

Abstract

PURPOSE:To shorten the CPU queuing time due to DMA processing by limiting the bus use request of a DMA device by an incorporated programmable timer. CONSTITUTION:A DMA device 4k is provided with a programmable timer T and counts a clock signal BCLK of a system bus 1 to obtain an output COUNT which has prescribed turn-on time and turn-off time. The time of the timer T is given as a program value from a CPU through a data/control bus 11 and address data is given to an address decoder DEC through an address bus 12 to designate the time of the timer T. The operation of the timer T is set in accordance with the address from the CPU and setting of turn-on/off time, and a turn-on/off output is periodically obtained with respect to the clock BCLK. The output of the timer T limits a bus use request signal BLR of the DMA device 4k by a gate G.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a DMA processing method in a computer system.

B8 Summary of the Invention The present invention provides a computer system in which a plurality of DMA devices are coupled to a system bus, by limiting the bus use request signal of each DMA device using a programmable timer, thereby reducing the number of bus accesses of each DMA device to one. This makes it possible to optimize the bus load without the bus being occupied by the bus.

C9 technology A computer system equipped with a number of DMA devices has a CPU 9 connected to the system bus 1 as shown in FIG.
2. Memory 3. n DMA devices 41 to 4n are coupled, and further coupled is a bus arbiter 5 that performs priority processing on bus use requests from each device.

In such a configuration, each DMA device 41 to 4r
, are given the right to use the bus according to the time chart shown in FIG. When the DMA processing request signal BRL from the D ki A device is sent onto bus 1, this signal BR
The bus arbiter 5 that receives the bus arbiter 5 puts a use permission signal BGL on the bus 1 if the bus is usable. When the DMA device that issued the bus use request receives this signal BGL, the device issues a signal BUSYL that prohibits other devices from using the bus.
Direct data exchange with the memory 3 is performed by issuing signals R8 and control C0NTR0L.

Here, as shown in FIG. 7, the priority processing for bus use requests from each DMA device 41 to 4n is performed by arranging a signal BGL line in a daisy chain configuration as shown in FIG. , priority is given to devices in order of physical proximity to the bus arbiter 5. In the figure, the DMA device 4 outputs the signal BRL to the bus, and the signal BRL passes through the delay circuit DEL to close the gate G, and the signal BGL from the bus arbiter 5 side is suppressed by the gate G. The signal BGL output to the device 42 side of the stage is not output. Therefore, multiple DMAs
Although the signal BRL is output from the device, the device closest to the bus arbiter 5 among the devices outputting the signal BGL receives the signal BGL, and does not provide the signal BGL to subsequent devices.

D0 Problems to be Solved by the Invention In the conventional DMA processing method, priority processing is performed using a daisy chain, so a DMA device with a low priority may not be granted the right to use the bus forever.
Makes system optimization difficult.

When a large number of DMA requests are received, the main CPU of the system is also unable to use the bus due to the BUSYL signal, causing the CPU to stop processing.

Means and operation for solving the E1 problem The present invention has been made in view of the above problem, and it connects a plurality of DMA devices to the system bus of a computer system, and connects each DMA device to the system bus of a computer system.
In a system that allows all DMA processing by giving priority to device A, each DMA device is provided with a programmable timer, and the output of each DMA request to the bus is limited by the time set in the programmable timer. By limiting the DMA requests within the device by the timer setting time, it is possible to restrict some upper-level DMA devices from occupying the bus, and also secure the bus usage time on the CPU side.

F. Embodiment FIG. 1 is a main circuit diagram showing an embodiment of the present invention. The system configuration is shown in Figure 5, of which D
The MA devices 41 to 4n each include circuit means shown in FIG. 1 as a DMA processing circuit.

In FIG. 1, the DMA device 4 is equipped with a programmable timer T, and the clock signal BCL of the system bus 1 is
K is counted to obtain an output C0UT that has a predetermined on-time and off-time. The time setting of this timer T is given as a program value from the CPU through the data/control bus 11, and is given to the corresponding DM through the address bus 12.
The address data of the A device is sent to the address decoder DEC.
The timer T is specified by being given to the timer T.

The operation of this programmable timer T is as shown in Fig. 2. It sets the address and on/off time of the DMA device from the CPU, and sets the clock BC.
Periodic on/off outputs such as outputs C0UTI and C0UT2 are obtained according to the on/off time setting contents for the LK human power.

Next, the output of the programmable timer T limits the bus use request signal BRL to the DMA device 4 at the gate G1. The output of the gate G1 is converted into an on-time timing signal by the differentiating circuit DIF and sent to the flip-flop FF.
The set is made by human power. The set state of flip-flop FF generates a bus use request signal BR from its output through buffer gate G2 to the bus arbiter. In response to this, the logical product of the permission signal BGI from the bus arbiter and the signal obtained by delaying the set output of the flip-flop FF by the delay circuit DEL is obtained at the gate G5, and the output of this gate G5 secures priority to the lower DMA device. .

Further, from the signal BGI and the mutual output of the flip-flop FF, the gate G11 obtains a bus use permission signal IBGL for the device 4 and resets the flip-flop FF.

The operating waveforms of these parts are shown in the time chart shown in Figure 3. In response to signal BRL, the BR signal output to the bus is waited until the signal that becomes the output of programmable timer T becomes valid, and the signal from the bus arbiter is When the bus use request signal BR is issued to BGI, gate 05
does not send the signal BGO to the lower device by
When not making a request, it sends out a signal BGO to enable a request to be made to a lower level.

Therefore, bus access requests from a plurality of DMA devices are limited by the settings of the respective built-in programmable counters T, and as shown in FIG.
By setting the valid on-time by the CPU at the time of system startup as shown in 2+45, there will be no competing DMA requests for the system bus, and the DMA device closest to the bus arbiter will not occupy the bus for a long time. There will be nothing to do. Furthermore, it is possible to set a time period in which the CPU 2 uses the bus.

According to the present invention, bus usage requests of DMA devices are limited by a built-in programmable timer, thereby eliminating bus occupancy by higher-level DMA devices and reducing bus usage for lower-level devices as well. There is no time limit and the CPU is less likely to be wasted due to DMA processing. Moreover, by setting the time of the programmable timer using the CPUflj, it becomes easy to make changes to optimize the bus accessability of each DMA device depending on the target of the system.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a main part showing an embodiment of the present invention, Fig. 2 is an output waveform diagram of the programmable timer in Fig. 1, Fig. 3 is a time chart of each part in Fig. 1, and Fig. 4 is a diagram of the output waveform of the programmable timer in Fig. 1. 5 is a system configuration diagram, FIG. 6 is a time chart of DMA processing, and FIG. 7 is a daisy chain configuration diagram of the DMA devices. 1... System bus, 41 + 42 + 4, 4
n-DMA device, 5... bus arbiter, T.
...Programmable timer, DEC...Address recorder, DIF...Differential circuit, FF...Flip-flop, DEL...Delay circuit. Figure 2 Blog Fuma Sword and Bessuma 〇Shichiryoku〉Omi 1 Tears Σ Figure 3 Tsuyuugaya t1 Evening 1 Mu Chart

Claims (1)

[Claims] In a system in which a plurality of DMA devices are coupled to a system bus of a computer system and each DMA device is given priority to enable DMA processing,
A programmable timer is installed in the A device, and each D
A DMA characterized in that output of an MA request to a path is limited by a set time of the programmable timer.
Processing method.