JP2574345B2 - Bus arbitration equipment - Google Patents

Description

The present invention relates to a computer, a workstation, and the like.
The present invention relates to a bus adjustment device that arbitrates a bus between a plurality of bus masters arranged on the same data transfer bus.

2. Description of the Related Art In recent years, with the development of microprocessor application technology, personal computers (hereinafter referred to as personal computers) and workstations that support communication using RS232C and the like have been increasing. These devices use a direct memory access controller (DMAC) in addition to a microprocessor to speed up processing. Therefore, since two bus masters exist on the same data transfer bus, a bus arbitration circuit is required.

Hereinafter, an example of the above-described personal computer will be described with reference to the drawings. FIG. 2 is a block diagram mainly showing a communication unit inside a conventional personal computer.

In FIG. 2, 20 is a microprocessor, 21 is a data transfer bus, 22 is a DMAC, 23 is a sequencer, 24 is a buffer RAM for temporarily storing data sent via the external interface circuit 25, and 25 is a buffer RAM. An external interface circuit for receiving data sent from outside, 26 is a RAM arranged on the data transfer bus 21, 27 is data sent from an external device, 28 is an external interface circuit
Reference numeral 25 denotes a first interrupt signal issued to the sequencer 23, and reference numeral 29 denotes a second interrupt signal issued by the sequencer 23 to the microprocessor 20.

The operation of the personal computer configured as described above will be described below, focusing on arbitration of the data transfer bus.

First, when the external interface circuit 25 receives data 27 from an external device into an internal reception buffer, it issues a first interrupt signal 28 to the sequencer 23. The sequencer 23 reads out the data received by the external interface circuit 25 and writes the data into the buffer RAM 24, and at the same time, a second interrupt signal 29 to the microprocessor 20.
Emits. The external interface circuit 25 negates the first interrupt signal 28 when the internal receiving buffer becomes empty. When receiving the second interrupt signal 29, the microprocessor 20 reads out the data stored in the buffer RAM 2 via the sequencer 23 if it is a bus master and there is no work that has priority over the data reception work. , Stored in the RAM 26. When there is no more received data in the buffer RAM 24, the sequencer 23 negates the second interrupt signal 29. If microprocessor 20
If the sequencer 23 and the buffer RAM 24 do not exist between the external interface circuit 25 and the external interface circuit 25 receive the data 27, and the DMAC 22 is the bus master, and the data 27 is sent one after another, overflow occurs. Will cause. When a plurality of bus memories exist on the same data transfer bus and an overflow can occur, a sequencer 23 and a buffer are provided between the external interface circuit 25 and the microprocessor 20.
A RAM 24 is provided to perform buffering by hardware.

Problems to be Solved by the Invention However, the above configuration has a problem that the amount of hardware increases because a sequencer and a buffer RAM are required. Especially the sequencer is buffered
In order to realize complicated functions such as RAM address generation, data read / write, and interrupt signal processing, the hardware becomes very complicated. It is also possible to use hardware that surrenders the data transfer bus to the DMAC using a data reception interrupt signal. However, when a microprocessor having a built-in external interface circuit is used, an interrupt signal is not output to the outside of the microprocessor, so that overflow occurs when an external DMAC occupies the bus. In this case, the aforementioned sequencer and buffer RAM
It is also not possible to use

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a bus arbitration device that does not generate overflow when receiving data and requires a small amount of hardware.

Means for Solving the Problems In order to solve the above problems, the bus arbitration apparatus of the present invention employs an oscillator that generates a rectangular wave having a period T and a period K (0 ≦ 0) during which the microprocessor occupies the data transfer bus.
K ≦ T) and a period L (L
= T−K).

Operation The present invention requires a small amount of hardware due to the above-described configuration, and does not cause overflow in any case when receiving data.

Embodiment A bus arbitration device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a bus arbitration device according to an embodiment of the present invention, wherein 1 is a microprocessor, 2 is a data transfer bus, 3 is a DMAC, 4 is an external interface circuit, and 5 is a divider 6 The input clock signal, 6 is a frequency divider that divides the input clock signal 5 by the frequency division ratio M (M = 1, 2, 3,...) Indicated by the microprocessor 1, and 7 is the frequency divider 6 Output clock signal, 8 is a decimal counter that counts output clock signal 7, 9
Is a count output value of the counter 8, 10 is a comparator for comparing the count output value 9 with the occupancy setting value 12, and 11 is set by the microprocessor 1 so that the DMAC 3 can set the maximum occupancy that can be the bus master. A bit occupancy setting register, 12 is an occupancy setting value output from the occupancy setting register 11, 13 is a DMA enable signal output from the comparator 10, 14 is a RAM arranged on the data transfer bus 2, and 15 is Data 16 sent from an external device is an interrupt signal issued from the external interface circuit 4 to the microprocessor 1.

The bus arbitration device configured as above
The operation will be described with reference to the drawings.

First, the microprocessor 1 stores the frequency division ratio M of the input clock signal 5 in the frequency divider 6 via the data transfer bus 2 and the maximum occupancy J (J = 0, 1,...) Of the DMAC in the occupancy setting register 11.
・ ・, 10) is set. The output clock signal 7 that has been frequency-divided by the frequency divider 6 is counted by the counter 8 and the counting result (0, 1,..., 9) is output. The comparator 10 compares the count output value 9 with the occupancy setting value 12. If the count output value 9 is smaller than the occupancy setting value 12, the DMA enable signal 13 is asserted, and the count output value 9 becomes the occupancy setting value. When it is greater than or equal to 12, the DMA enable signal 13 is negated. When the DMA permission signal 13 is asserted, the DMAC 3 becomes the bus master and can occupy the data transfer bus 2, but when the DMA permission signal 13 is negated, the DMAC 3 becomes the bus master of the data transfer bus 2. It is not possible. If the DMA permission signal 13 is negated when the DMAC 3 is the bus master, the DMAC 3 immediately gives up the bus and the microprocessor 1 becomes the bus master. For example, if the occupancy setting register 11 is set to 4, the DMA enable signal 13 is asserted when the count output value 9 is 0, 1, 2, and 3, and as a result, the DMAC 3 is up to 40% of the bus master of the data transfer bus 2. Can be Of course, when the DMA permission signal 13 is asserted and the DMAC 3 does not require the exclusive right of the data transfer bus 2, the microprocessor 1 becomes the bus master. Since the frequency division ratio M and the occupancy setting register 11 of the frequency divider 6 can be set by the microprocessor 1, arbitrary values can be selected for the cycle and the duty of the DMA permission signal 13.

Hereinafter, a description will be given of a case where data is received from the outside at a transfer rate of 9600 bps (bit / sec) using an RS232C interface in a microprocessor system using the above bus arbitration device. RS232C is a serial transfer, and adding a start bit, stop bit, etc.
One byte is transferred in 1 msec. Therefore, DMAC3 is continuously 1m
If the data transfer bus 2 is occupied for more than sec, overflow may occur. Therefore, the period of the DMA enable signal 13 is set to 1
It must be less than msec. Now input the clock of microprocessor 1 as input clock signal 5 (10MHz)
When a clock obtained by dividing the frequency by 3 is used, the following equation is established.

1 × 10 ⁻³ > M × 10 × 3 / (10 × 10 ⁶ ) From this equation, if M <100/3 where M = 32 (= ²⁵ ), the period T is about 1 msec (999
μsec). If the interrupt processing time of the microprocessor 1 by the interrupt signal 16 (the time required to read one byte of data from the external interface circuit 4 using the interrupt processing routine and buffer it in the 1RAM 14) is 300 μsec at the maximum, a period of 1 msec. The period K during which the microprocessor 1 occupies the data transfer bus 2 requires at least 300 μsec. Therefore, 7 may be set in the occupancy setting register 11 as the maximum occupancy of the DMAC3. DMA when DMAC3 is the bus master
As a method of releasing the data transfer bus 2 by negating the enable signal 13, for example, a halt (stop) signal is input to the DMAC 3, or if the transfer performed by the DMAC 3 is based on an external transfer request signal, The DMA
This can be easily realized by, for example, forcibly negating using the permission signal 13.

As described above, according to the present embodiment, the period K (0 ≦ K ≦ T) in which the microprocessor occupies the data transfer bus using the oscillator that generates the square wave of the cycle T and one or more DMs
By dividing and using the period L (L = TK) in which the AC can be occupied, the microprocessor can secure the right to occupy the data transfer bus at a constant period and at a constant rate.

In the above embodiment, the frequency divider 6 is used as an oscillator.
Although the counter 8, the comparator 10, and the occupancy setting register 11 are used, the oscillator is not limited to this. The period during which the microprocessor 1 occupies the data transfer bus 2 at a constant cycle using the output signal and the DMAC 3 Anything can be used as long as it can be divided into periods that can be occupied. For example for a timer
It is also possible to use an IC or to use an oscillator having a constant cycle and duty.

As described above, according to the present invention, the period during which the microprocessor occupies the data transfer bus using the output signal of the oscillator and the DM
By dividing and using the period in which the AC can be occupied, complicated hardware using a sequencer and a buffer RAM is unnecessary in a system involving an external data receiving operation. Further, even when a microprocessor having a built-in external interface circuit is used, the microprocessor can periodically secure a data transfer bus at a constant rate, so that a reception error due to overflow can be prevented.

In addition, since the cycle and duty of the oscillator can be set programmably, the occupancy of the data bus of the microprocessor can be set arbitrarily. In this case, a certain microprocessor processing time can be ensured without fail, which is very effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bus arbitration device according to an embodiment of the present invention, and FIG. 2 is a block diagram mainly showing a communication unit inside a conventional personal computer. 1,20 microprocessor, 2,21 data transfer bus, 3,22 DMAC, 4,25 external interface circuit, 5 input clock signal, 7 output clock signal, 9 Count output value, 12 ... Occupancy setting value, 13 ...
... DMA enable signal, 15, 27 ... data, 16 ... interrupt signal, 28 ... first interrupt signal, 29 ... second interrupt signal.

Claims (2)

(57) [Claims] When a microprocessor and one or more direct memory access controllers use the same data transfer bus, the microprocessor occupies the transfer bus using an oscillator that generates a rectangular wave having a period T. A bus arbitration device, wherein the bus arbitration device is divided into a period K (0 ≦ K ≦ T) and a period L (L = TK) that can be occupied by the one or more direct memory access controllers. 2. A frequency divider for dividing an input clock signal by an arbitrary frequency division ratio according to an instruction from a microprocessor and outputting the same, a counter for counting an output clock signal of the frequency divider, An oscillator configured by an occupancy setting register that sets the occupancy by the microprocessor, and a comparator that compares a value set in the occupancy setting register with an output value of the counter and outputs a comparison result is used. The bus arbitration device according to claim 1, wherein: