WO1993012486A1

WO1993012486A1 - Direct memory access interface for buses of different width

Info

Publication number: WO1993012486A1
Application number: PCT/US1992/004165
Authority: WO
Inventors: Jerry L. Ballard; Johannes H. Suwandhaputra
Original assignee: Tandy Corporation
Priority date: 1991-12-09
Filing date: 1992-05-19
Publication date: 1993-06-24
Also published as: AU2142492A

Abstract

An interface (10) is provided for regulating the transfer of data between a first device (14) having a data bus (26) of first width and a second device (12) having a bus (20) of second width. The interface (10) intercepts a first transfer request sent from the first device (14) and in response thereto the interface (10) generates emulating control signals of the second device (12) such that a first data of first width from the first device (14) is sent and intercepted in the interface (10). The interface (10) waits for the second data to arrive and the first data is passed together with the second data as a single data of the second width to the second device (12).

Description

DIRECT MEMORY ACCESS INTERFACE FOR BUSES OF DIFFERENT WIDTH

Field of the Invention

This invention relates to interface circuits between computers and peripheral devices and particularly to programmable direct memory access (DMA) interface circuitry utilized between dissimilar-sized data buses of a computer and a peripheral device.

Background of the Invention

In many host computer systems involving bulk data storage applications the data transfer rate to and from an associated peripheral data storage device is sufficiently high that it is difficult for a processor of the host computer to service the data storage device and also service other peripheral devices, such as, for example, a key board, instruction pointer and monitor. A special data processing technique known as direct memory access (DMA) is known to solve these high data-rate interface and adapter problems. This technique allows a peripheral device to read or write data to or from the main memory storage of a host computer system's processor without requiring the use of the processor. In personal computer design the DMA function is provided by a DMA controller.

SUBSTfTUTESHEET During normal program execution of the host computer system, the processor is the source or destination of data and controls a system bus to accomplish the data transfer, providing bus address and control information. When an interface associated with a peripheral device connected to the host computer system is utilized to transfer data using the DMA technique, it sends a request signal to the DMA controller. The controller prioritizes this request and sends a "hold" request signal to the processor. At the end of the current bus cycle, the processor removes itself from the system bus and sends a "hold" acknowledge signal to the DMA controller, indicating that the bus is available for the data transfer. The DMA controller then attaches itself to the system bus and drives the address and control lines of the bus, executing a data transfer cycle between the requesting interface and the main memory storage. The interface is notified of this action by the DMA controller sending a DMA acknowledge signal to the interface. The DMA controller can be thought of as a third party, which, when requested, will take over as the system-bus master and will cause the transfer of data directly between the peripheral device interface and the memory storage of the host computer system.

Without the DMA technique, a processor would be required to perform an input/output loop which takes a minimum of 29 clock periods to perform, for example. Through the use of the DMA technique only 5 clock periods are required per byte of data transferred. Unfortunately, the processor cannot be active during the DMA- cycle and must wait until the DMA cycle has completed to in order continue with its data processing functions. Further, while the bus architecture of the processors of many host computer systems are capable of 16-bit or 32-bit data transfers, the bus architecture of many peripheral devices is only capable of performing 8-bit data transfers. Thus, a 16-bit processor will require two DMA cycles or 10 clock periods to transfer both bytes when performing DMA transfers with an 8-bit peripheral device. This can result in a significant reduction in processor efficiency and data throughput.

Input-output channel controllers (IOCCs) have been designed to include data buffers to provide temporary storage of data in the event the processor is not ready for a DMA transfer. Moreover, multiple data buffers have been used in an IOCC when there is a mismatch in data width between the processor' s internal bus and that of the peripheral bus. For example, an IOCC may contain two separate temporary storage buffers, capable of storing one byte of data, enabling the accumulation of two bytes of data in temporary storage from a peripheral bus capable of transferring one byte at a time, until such time as the processor is ready for the data. At such time, the data contained in both buffers is transferred in a single two-byte wide transfer on the system bus to the processor's main memory storage. Similarly, IOCCs have been designed to utilize data buffers in the temporary storage and decomposition of two-byte words into two, one-byte words. The use of data buffers in IOCCs to accomplish this purpose is described in U.S. Patent No. 4,479,179.

However, the . above-described DMA transfer techniques for use in a mismatched bus environment are inefficient in that they involve multiple DMA clock cycle operations to load the buffers where the data is then stored until the processor of the host computer is ready for a transfer. A more desirable arrangement would involve accomplishing the conversion of data to the appropriate bus width in a manner which is transparent to the host computer and its associated DMA controller, so that a minimum of clock cycle operations are utilized and data is transferred to or from the host computer according to the bus width of the host computer.

In a multimedia computing system in which a host computer is interconnected with a monitor and a peripheral device such as a compact disk read-only-memory (CD-ROM) drive, for example, it is especially desirable to maximize the efficiency of data transfer from the drive to the host computer system, as the processor of the host computer system is needed for the continuous display of images on the monitor and for processing audio information, in addition to its other processing functions.

Summary of the Invention

The foregoing problems are solved and a technical advance is achieved by method and apparatus for effecting direct memory access data transfers between mismatched data buses of a computer and a peripheral device, in which the conversion of data to or from the data width appropriate for^* the bus size of the computer is accomplished in a manner transparent to the computer, thus minimizing the required DMA cycle operations of the computer. In a departure from the art, a direct memory access interface is provided for facilitating the transfer of data between the mismatched- data buses of the computer and the peripheral device, the interface having its own arrangement for intercepting DMA request signals from the peripheral device and for performing DMA control

SUJBSTΓΓUTE SHEET operations to either compose or decompose data to the appropriate bus data width without involving the computer.

In an illustrative embodiment, the interface is interconnected between a computer having a 16-bit bus and a peripheral device such as a CD-ROM drive having an 8-bit bus. In response to an intercepted DMA read request from the peripheral device, the interface issues false acknowledge and false I/O read signals, emulating the DMA control operations of the computer in its own false DMA cycle to initiate a transfer of a first byte of data to the interface. The first byte of data is received in the interface where it is latched for temporary storage. The next DMA read request of the peripheral device is permitted by the interface to pass to the computer, which then initiates its normal DMA cycle by issuing system data acknowledge and system I/O read signals and thus causing a second byte of data to be transferred from the peripheral device. The interface receives the second byte of data from the peripheral device in a buffer and passes it directly to the computer, together with t a first data byte previously stored, so that the computer receives a 16-bit data word corresponding to the data width of its host bus. The interface accomplishes the DMA control operations to collect the first byte of data independently of and transparent to the computer, thereby minimizing the DMA cycle operations required by the computer and increasing data throughput from the peripheral device. By composing a single two-byte word from two single bytes of data, the interface reduces by half the amount of time required to perform DMA transfers. In an alternative embodiment, the interface operates in a similar manner to perform DMA write operations in which data is written from the computer to the peripheral device. In a write operation, a 16-bit data word is transferred from the computer to the interface and is decomposed, such that one byte of data is passed directly through the buffer to the peripheral device and the other byte of data is temporarily stored. During the false DMA cycle performed by the interface independent of the computer, the stored data byte is transferred to the peripheral device.

In a preferred embodiment, an interface circuit of the present invention is provided for regulating the transfer of data between a first device having a data bus of a first data width, and a second device having a data bus of a second data width, in which the second data width is an integer multiple of the first data width. The interface circuit includes an arrangement for intercepting at least one data request signal sent from the first device and for emulating control signals of the second device in response to the data request signal, in order to initiate transfer of data independent of the second device. The arrangement also provides for passing to the second device a subsequent data request signal sent from the first device in order to allow the second device to initiate transfer of data. The circuit further includes an arrangement for receiving data being transferred between the devices and for storing at least one data block of the first data width, such that when the data is being transferred from the- first device to the second device, at least one data block is stored responsive to the data request signal, and responsive to the subsequent data request signal, a data block of the first data width and the at least one stored data block are passed together to the second device as a single data block of the second data width.

In another aspect, the interface circuit includes an arbitration arrangement for prioritizing access to the data bus of the second device upon simultaneous issuance of a data request signal sent from the first device and an input/output command signal sent from the second device. A determination is made which of the data request signal and the command signal will be given access to the bus first based on the state of an internal clock of the second device.

An important technical advantage acheived with the invention is that the DMA interface emulates the DMA control functions of a host computer to accomplish a false DMA cycle transparent to the host computer, thereby reducing the work load of the host computer and also increasing data transfer throughput between the computer and an associated peripheral device.

The interface further accomplishes data transfers for both read and write operations.

Brief Description of the Drawings

FIG. 1 depicts a block diagram of a data processing system utilizing a DMA interface of the present invention;

FIG. 2 depicts block diagram of showing the details of the DMA interface of FIG. 1;

FIG. 3 depicts a schematic showing the circuitry of the DMA interface of FIG. l;

FIG. 4 depicts a flow chart illustrating the logical sequences implemented by the DMA interface of the present invention during DMA read cycles;

SUBSTITUTESHEET FIG. 5 depicts a flow chart illustrating the logical sequences implemented by the DMA interface of the present invention to eliminate possible contention for the host bus during read operations;

FIG. 6 depicts a signal timing diagram illustrating the control signals of the system utilized during DMA read cycles;

FIGS. 7a and 7b depict signal timing diagrams illustrating control signals of the system utilized during host bus arbitration in DMA read cycles;

FIG. 8 depicts a flow chart illustrating the logical sequences implemented by the DMA interface during DMA write cycles;

FIG. 9 depicts a flow chart illustrating the logical sequences implemented by the DMA interface to eliminate possible contention for the host bus during write operations;

FIG. 10 depicts a signal timing diagram illustrating control signals of the system utilized during DMA write cycles; and

FIGS. 11a and lib depict signal timing diagrams illustrating control signals utilized by the system during host bus arbitration in DMA write cycles.

Detailed Description of the Preferred Embodiment In FIG. 1 of the drawings, there is shown a block diagram of a data processing system 2, which includes a direct memory access (DMA) interface 10 incorporating features of the present invention. The interface 10 interconnects a host computer system 12 to a peripheral device ^• 14. More specifically, the interface 10 interconnects an industry standard architecture (ISA) internal host bus 16 of the system 12 to an internal

SUBSTITUTESHEET peripheral bus 18 of the peripheral device 14. Address, data, and control buses 20, 22, and 24, respectively, interconnect the interface 10 to the host bus 16. Address, data, and control buses 26, 28, and 30, respectively, interconnect the interface 10 to the peripheral bus 18. It is understood that the architecture of the buses 16, 18 is mismatched, such that one of the buses is capable of accommodating data in a data width or bit quantity M, which is greater than and some multiple of a data width or bit quantity N of the other bus. In the present embodiment, for example, the host bus is a 16-bit bus capable of accommodating data in 16-bit wide quantities, while the bus 18 is an 8-bit bus only capable of accommodating data in 8-bit wide quantities. It is understood that other values for M and N are contemplated. A host processor 32 of the system 12 is connected to the bus 16. The processor 32 is an Intel 386 or 286 series microprocessor, although another processor can be used.

In the illustrative embodiment, the data processing system is a multimedia computing system in which the host system 12 is a multimedia computer and the peripheral device 14 is a compact disk read-only-memory (CD-ROM) drive, these components being operationally interconnected by the interface 10 of the present invention. While not shown, it is understood that other peripheral devices are also connected to the system 12, including, for example, a keyboard, an instruction pointer, a monitor, audio devices, additional memory, etc.

According to the. invention, the DMA interface 10 operates to receive 8-bit wide quantities of data from the peripheral device 14 and transfers the data in a 16-bit wide quantity to the host system 12 in a single DMA cycle of the system 12. When a direct memory access data request (DRQ) signal normally intended for the host system 12 is sent from the peripheral device 14 to request a transfer of a data block from the peripheral device to the host system, the DMA interface 10 intercepts the DRQ signal and prevents the signal from passing to the host system. The DMA interface 10 then emulates the control functions of the host system 12 for accomplishing a transfer of the data block from the peripheral device. In response to the DRQ signal, the DMA interface 10 sends out a "false" data acknowledge (DACK) signal and a "false" input/output read (IOR) signal to the peripheral device 14. These signals are referred to as "false" because they are sent by the interface 10 instead of from the host processor 32 of the system 12. The peripheral device 14, in response to the false DACK and false IOR signals, sends the first block comprising 8-bits of data to the DMA interface 10 where it is latched for temporary storage. Thus, the transfer of the first 8-bit block of data occurs in a manner transparent to the system 12. The peripheral device 14 then sends a second DRQ signal intended for the system 12 for initiating a transfer of the next 8-bit block of data from the peripheral device. The second DRQ signal is not intercepted by the interface 10, but instead is passed through the DMA interface 10 to the host system 12 and the system performs a normal DMA cycle in which the system 12 initiates DACK and IOR signals and completes the DMA transfer. During the normal DMA cycle involving the host processor 32, the second 8-bit block of data from the peripheral device is sent to the interface 10. Instead of remaining latched for temporary storage, the second block along with the first, previously latched block are together sent as a single, 16-bit wide block to the host system 12. In this manner, the interface 10 is able to accomplish a 16-bit block transfer of data in a single DMA cycle of the host system 12 from an 8-bit peripheral device. The DMA control functions for the first data block transfer are performed by the interface 10 by use of the false signals which emulate the DMA control functions normally performed by the system 12.

In a similar fashion, this interface 10 is able to decompose 16-bit data words into 8-bit data words during data write cycles from the system 10 to the peripheral device 14. Such a function would be advantageous in applications in which the peripheral device 14 is a floppy drive, hard disk drive, or similar device. The interface 10 thus reduces the work load on the host system 12 by simulating a DMA transfer to the peripheral device 14. Instead of having the host system 12 performing two 8-bit transfers, the DMA interface is used to make a full 16-bit data transfer to the peripheral device 14, resulting in a simultaneous transfer to the peripheral device 14 of the first 8-bit block, followed by a DMA transfer performed by the interface alone to transfer the second 8-bit block to the peripheral device. This reduces by half the number of DMA cycles required to perform DMA data transfers and thereby increases the data transfer throughput of the system 2.

In FIG. 2, details of the interface 10 are illustrated in which the interface comprises a preblock interrupt control logic circuit 50, a host control interface circuit 52, data storage blocks 54 and 56, and a state machine 58. The DMA interface 10 is connected to

SUBSTITUTESHEET the bus 16 of the host system 12 by the address bus 20, the data bus 22, and also control lines 60, 62, 64, 66, 70, 72 and 74. Similarly, the DMA interface 10 is connected to the peripheral device 14 by the peripheral data bus 28, the address bus 26 comprising at least line 76 and by the control bus 30 comprising control lines 82, 84, 86, 88 and 90. The control lines 60-74 and 82-90 are discussed further below.

The preblock interrupt logic circuit 50 is used to generate interrupt signals to the host processor 32 on the system interrupt (SYS-INT) control line 60. The interrupt signals are sent to the host computer system 12 at the beginning and at the end of the data transfer. A first interrupt signal is called the preblock interrupt (PREINT) signal and is used to generate a system interrupt signal on the SYS-INT control line 60. The PREINT signal is generated in the event that an interrupt signal is not already generated by the peripheral device 14, and functions to prepare the host system 12 to receive data by placing the processor 32 in a halt state. The PREINT signal thus causes the processor 32 to give the peripheral device 14 immediate access to the host bus 16. This reduces the time required to perform a data block transfer from eight to four milliseconds. A second interrupt signal is generated by the peripheral device 50 and is used to indicate the end of the block and to take the processor 32 out of the halt state. It is understood that an additional interrupt can be generated from the peripheral device 14 if an error occurs in order to take the processor 32 out of the halt state. The overall effect of the preblock interrupt logic circuit 50 is to reduce the time required to perform a DMA transfer. In operation, the preblock interrupt circuit 50 receives the first DRQ from the peripheral device 14 on the compact disk direct memory access request (BCDDRQ) control line 90. The preblock interrupt logic circuit 50 responds by issuing the first PREINT signal to the host processor 32 on the SYS-INTR control line 60. The first PREINT signals tells the processor 32 that the peripheral device 14 is preparing to transfer a data block. The processor 12 then executes a halt instruction. While in the halt mode, the processor 12 will only acknowledge DMA cycles. This allows the DMA interface 10 to transfer data as fast as it can. At the end of the block transfer the peripheral device 14 will generate the second interrupt signal on the block compact disk interrupt (BCDINT) control line 82. The second interrupt is used to take the processor 12 out of its halt state. Once the interrupt has ended, the processor 12 will check to make sure that the data transfer did take place and it will then resume operation.

The host control interface circuit 52 functions at the beginning of the data transfer to program the peripheral device 14 with the type of transfer, the byte count, and the starting memory location. In addition, the host control interface circuit 52 also serves to buffer data in non-DMA operations. Typical non-DMA operations include I/O commands and peripheral status words. A PORTWR line 53 is connected between the circuit 52 and the circuit 50 and is used to enable a preblock interrupt signal that was initiated by a first DMA request (DRQ) .signal. A PORTRD line 55 is also connected between the circuit 50 and the circuit 52 and is used to read the preblock interrupt status, e.g. whether it is a preblock interrupt that is occuring or whether it is the end of the block.

The interface 10 also includes a data storage block

54 connected to the data bus line 22 and the peripheral bus line 28 of the interface. Referring to FIG. 3, the block 54 includes a latch 54a and a buffer 54b. The latch

54a accommodates data in the lower bit (7..0) address range and is capable of holding 8-bits (one byte) of data. The buffer 54b accommodates data in the upper bit

(15..8) address range and is also capable of holding

8-bits (one byte) of data. When the peripheral device 14 initiates a DMA read cycle, the first byte of data from the device is received by the interface 10 in the block 54 and is latched in the latch 54a for temporary storage.

When the peripheral device 14 sends the second byte of data to the interface 10, the block 54b receives the second byte of data in the buffer 54b and passes it directly through to the system 12, along with the first byte from the latch 54a, so that 16-bits are passed together to the system 12. Accordingly, when the second byte of data is received by the interface 10 from the peripheral device 14, it is received in the block 54 and buffered, but it is not latched.

In DMA write operations from the processor 32 to the peripheral device 14, a data storage block 56 (FIG. 2) is used to buffer the lower [7..0] bits and to latch the upper [15..8] bits of data, in similar, reverse operations to those just described, these operations being discussed later in detail. • While not shown, the block 56 also includes an 8-bit latch and an 8-bit buffer. The state machine 58 emulates the control signals from the host system 12. The first DRQ signal sent by the peripheral device 14 by means of the CDDRQ control line 90 is captured by the state machine 58. The state machine 58 then issues to the peripheral device 14 a false data acknowledge (FDACK) signal and a false I/O read (FIOR) signal by means of the block compact disk acknowledge (BCDDACK) control line 88 and the block compact disk I/O read (BCDIOR) control line 84, respectively. The peripheral device 14 then sends out the first byte of data to the interface 10 via the data bus 28. The first byte is then latched for temporary storage in the latch 54a of the block 54. The peripheral device 14 issues a second DRQ signal, which is passed by the state machine 58 to the host system 12 by means of the send direct memory access request (SDRQ) control line 72. The host system 12 issues a system data acknowledge (SDACK) signal and a system I/O read (SIOR) signal back to the peripheral device 14 by means of the SDACK and the SIOR control lines 70 and 64, respectively. The SDACK signal is used by the DMA interface 10 to enable both the upper and lower bytes of data to pass onto the host bus 16 simultaneously. The second byte of data is received in the buffer 54b of the block 54 and is passed to the system 12 along with the first byte of data from the latch 54a. In this manner, two 8-bit bytes are placed on the bus 16 as a single 16-bit data word. The third DRQ signal from the peripheral device 14 is treated just like the first DRQ signal in that it is not passed to the system 12. Thus, the process is repeated until the end of the data block transfer. At the end of the data block transfer, the peripheral device 14 generates an interrupt signal. This end-of-block interrupt signal is transmitted from the peripheral device 14 by means of the BCDINT control line 82. The end-of-block interrupt signal is used by the interface 10 to generate the second system interrupt signal. This second interrupt signal is used to take the processor 32 out of the halt state and return it to its normal processing functions.

The state machine 58 also contains bus arbitration logic in the event of contention for the host bus 16. During a false DMA cycle, the host system 12 may send an input/output command to the peripheral device 14. In this event, there is contention for control of the host bus 16 and the arbitration logic is activated. The arbitration logic determines which request takes precedence, as discussed further below.

FIG. 3 illustrates in detail the circuitry for a presently preferred implementation of the DMA interface 10 in accordance with the present invention. In FIG. 3, part numbers and values of components are set forth, which components and part numbers are available at the present time f om commercial vendors.

As shown in FIG. 3, the interface 10 includes circuitry corresponding to components previously described in FIG. 2, however the embodiment of FIG. 3 is configured for performing DMA read operations only. Therefore, there is no circuitry corresponding to the data storage block 56, which is utilized for DMA write operations.

The host control interface 52 and the state machine 58 each, include programmable logic devices designated in FIG. 3 with the part number PL5173, and labeled 302 and 304, respectively. Tables I and II set forth pin identification information, declarations and intermediate

SUBSTfTUTESHEET variable definitions and logic equations associated with the respective programmable logic devices 302 and 304.

/** Declarations and intermediate Variable Definitions **/ /** Logic Equations **/ cdadd = !sal5 & !sal4 St !sal3 St !sal2 & Isall IsalO & sa9 & sa8 & !sa7 & !sa6 St !sa5 & !sa4 !sa3 & !sa2 & !sal & aen; portwr = !sal5 Si !sal4 St !sal3 St !sal2 & Isall St IsalO St sa9 Si !sa8 St !sa7 St !sa6 Si sa5 St Isa4 & sa3

portrd = !sal5 St Isal4 S> !sal3 St !sal2 St isall St IsalO & sa9 St Isaδ St Isa 7 St !sa6 St sa5 St Isa4 St sa3

TABLE II

Programmable Logic Device 304 IN Name Description

/* Ext. dec address */ /* system io write */ /* system io read */

/* dma channel 7 */

SUB^STITUTESHEET

/** Declarations and intermediate Variable Definitions **/ /** Logic Equations **/ portrd = cdadd St ior; cdior = fior & drqen

# ior Si !drqen

# ior30x cddack = fdack St drqen

# mdack St !drqen

# mdack St 8biten; enable = cdadd St ior30x

# cdadd & iow; lbufen = cdadd & ior30x

# cdadd St iow

# dack3;

FIG. 4 depicts a flow chart which further describes the read cycle implemented by the interface 10. In step 102, the preblock interrupt PREINT signal is enabled by the first DRQ signal coming from the peripheral device 14. After the preblock interrupt signal is enabled, the system 10 proceeds to step 104 where the host system 12 programs the interface 10 with the location of the data starting address, the byte count to be transferred, and the type of data transfer. The interface 10, in turn, programs the peripheral device 14 with this information. In step 106, a determination is made whether the DRQ signal received by the interface 10 is even. The purpose of this determination is to determine which half of the 16-bit data word is to be transferred. If the DRQ signal is the first (designated herein as "even") DRQ signal representing the first 8 bits of data to be transferred, execution proceeds to step 108. In step 108, a determination is made whether an I/O instruction has occurred at the same time as the DRQ signal being received by the interface 10. Since the processor 32 still has control of the host bus 16 an I/O instruction is able to occur. If an I/O instruction occurs at the same time as the DRQ signal is sent from the peripheral device 14, there is rivalry for the bus 16. In this event, the arbitration scheme of the state machine 58 is activated in step 110. The arbitration scheme implemented by the state machine 58 is subsequently discussed with reference to FIG. 5.

If in step 108 it is determined that an I/O instruction is not occurring at this time, then execution proceeds to step 114. In step 114, the state machine 58 generates a false data acknowledge (FDACK) signal and a false I/O read (FDIOR) signal, both of which are propagated to the peripheral device 14. The FDACK signal is used to enable the data latch 54a for receiving the first 8-bit data transfer. The FIOR signal is used for initiating the transfer of the first 8-bit data byte from the peripheral device 14 to the interface 10. In step 116, the first or even 8-bit data byte is stored in the latch 54a. After this first, lower byte is stored, execution proceeds to step 118. In step 118, the interface 10 waits for the next DRQ signal from the peripheral device 14. Upon receipt of the next DRQ signal, execution returns to step 106. If in step 106 the next DRQ signal is not even, control proceeds to step 119. In step 119, the DRQ signal is passed from the peripheral device 14 directly to the host system 12, without being intercepted by the interface 10. In response, the processor 32 in step 120 issues a system data acknowledge (SDACK) signal and a system I/O read (SIOR) signal. The system data acknowledge (SDACK) signal is used to enable the system 12 to receive data on the bus 16. The SIOR signal initiates the second 8-bit (upper) data byte to be read from the peripheral device 14. In step 122, it is understood that the second data byte is received in the buffer 54b of the block 54 and then is immediately transferred with the first data byte in the latch 54a to the host system 12, as a single 16-bit word.

Execution proceeds to step 124 where a determination is made whether the last data block has been transferred, as determined by the status of a counter. If in step 124 the counter does not equal zero, additional data remains to be transferred and control returns to step 118. If in step 124 the counter equals zero, execution proceeds to step 126. In step 126, an interrupt signal is generated to pull the system 12 out of the halt state. In step 128, the DMA cycle is completed and ends.

Referring to FIG. 5 of the drawings, there is depicted a flowchart of the arbitration scheme for handling contention for the host bus 16. In the event the false DMA cycle occurs at the same time as the host system I/O cycle, then the arbitration scheme is activated from step 110 in FIG. 4. In step 140 of FIG. 5, a decision is made whether the positive edge of the clock cycle of the processor 32 is next. If the processor 32 clock cycle is approaching the positive edge, execution proceeds to step 142. In step 142, the false DMA cycle being served first. Next, in step 144 a wait state is issued to the host processor 32 causing a delay in the system I/O cycle. The wait state is issued by deactivating the I/O ready (READY) control line 62. In step 146, the false DMA cycle is initiated by generating the FDACK and FIOR control signals. The FDACK and FIOR signals are used to enable the latch 54a and initiate the data transfer from the peripheral device 14. In step 148, the 8-bit (lower) even byte of data is stored in the latch 54a. In step 150, after serving the false DMA cycle, the system 10 will enable the host processor 32 to execute a system I/O cycle. In step 150, the I/O cycle is enabled by reactivating the I/O ready control line 62. After the I/O cycle is completed in block 150, the bus arbitration ends and execution returns to step 114, in FIG. 3, to complete the DMA read cycle.

If in step 140, the clock cycle of the processor 32 is approaching a negative clock edge, then execution proceeds to step 160 in FIG. 5. In step 160, the I/O cycle of the host system 12 is served instead of the false DMA cycle of the interface 10. In step 162, the false DMA cycle is delayed so that the I/O cycle can take place. In step 164, the system I/O cycle is initiated and completed. . In step 166, the interface 10 generates the FDACK and FIOR control signals to the peripheral 14. The FDACK signal will enable the latch 54 and the FIOR signal will initiate the data transfer from the peripheral device 14. In step 168, the 8-bit even (lower) data byte is latched in the latch 54. Execution then returns to step 114 in FIG. 4. FIG. 6 illustrates a timing diagram for the DMA read operation involving the CDDRQ control line 90, the BCCDACK control line 88, the BCDIOR control line 84 and the peripheral data bus line 28, all of which are also shown in FIG. 2. In FIG. 6 at time 602, the peripheral device 14 sends to the interface 10 the first DRQ signal on the CDDRQ control line 90. The first DRQ signal is captured by the state machine 58 and is therefore not passed to the host system 12. At time 604 a false data acknowledge (FDACK) signal is sent on the BCDDACK control line 88 by the state machine 58 to the peripheral device 14. At time 606 a false I/O read (FIOR) signal is sent by the state machine 58 on the BCDIOR control line 84 to the peripheral device 14. The peripheral device 14 will then output the first byte of data on the peripheral data bus 28 to the latch 54a. The trailing edge of the FIOR signal on line 84 is used to latch the first byte coming out from the peripheral at time 608. This byte is stored in the latch 54a. At time 610 the second DRQ is issued by the peripheral device 14 on the line 90 to the interface 10. When the second DRQ signal is sent, it is passed through the state machine 58 to the host processor 32. In response to the second DRQ signal, the host processor 32 issues a system data acknowledge (SDACK) signal at time 612, which is passed through the interface 10 to the peripheral device 14 on the BCDACK control line 88. At time 614 a system I/O read (SIOR) signal is sent by the processor 32 to the peripheral device 14 on the line 84, requesting the second data byte from the peripheral device 14. At time 616 both- the first data byte from the latch 54a and the second data byte then received in the buffer 54b are passed as a single 16-bit (two-byte) word to the system 12. At time 618 the next DRQ is received fro; the peripheral device 14, which is treated in the same mauler as the first DRQ at time 602.

FIGS. 7a and 7b illustrate timing diagrams for the arbitration scheme of the interface 10 implemented when there is contention for the host bus 16 due to both a peripheral device DMA data transfer and a system I/O request involving the system 10. FIG. 7a illustrates the case where the DMA data transfer obtains priority over the bus 16 and FIG. 7b illustrates the case where the system I/O cycle obtains priority.

In FIG. 7a, the status of the system clock for the processor 32 is designated by the timing line 700. The timing line 702 represents the status on an I/O cycle signal within the state machine 58 designated as P30X I/O read/write (P30XIOR/W) (not shown) , which represents a decoded address qualified with an I/O command to the state machine. The timing line 704 shows the status of the first DRQ signal from the peripheral device 14. At time 706, both the P30XIOR/W signal and the DRQ signal are occurring, at the same time. In this case, there is contention for the host bus 16. Time 706 occurs prior to the system clock approaching a positive edge which then occurs at time 708. Consequently, the false DMA cycle is served first by delaying the system I/O cycle. Also at time 706, the SIOR signal is moved low. It is held low by the READY signal on line 710. At time 712, the READY signal is moved low in order to issue a wait state to the host processor 32, thereby delaying the system I/O cycle. The state machine 58 initiates the false DMA cycle by issuing an FDACK signal as shown by the timing line 714 at time 716. At time 718 the FIOR signal is issued as shown

SUBSTITUTESHEET on the timing line 720. After the false DMA cycle is completed, the READY signal on the line 710 goes high at time 719 signifying that the peripheral device 14 is now ready to execute an I/O command. The host processor 32 completes the I/O command by deactivating the SIOR signal at time 722 as shown on timing line 724.

In FIG. 7b, the P30XIOR/W and DRQ signals occur concurrently at time 726, indicating contention for the bus 16. Time 728 occurs prior to the system clock approaching a falling edge or negative portion of the clock cycle on the line 700. Consequently, the false DMA cycle is delayed and the system I/O cycle is served first. This is accomplished by delaying the false DMA acknowledge (FDACK) and the false I/O read (FIOR) signals until the system I/O cycle is finished. The system I/O cycle is initiated by issuing a system I/O ready (SIOR) signal at time 728 as shown on the line 724. Upon completion of the system I/O cycle at time 730 the SIOR signal goes high as shown on the line 724. At time 732 the state machine 58 issues an FDACK signal as shown on the line 714 and at time 734 issues a FIOR signal as shown on the line 720, thereby initiating the false DMA cycle. The DMA interface 10 will then continue in its execution of a DMA transfer.

FIGS. 8-11 illustrate write cycle operations in which the interface 10 of the present invention is utilized to accomplish the transfer of data from the system 12 to the peripheral device 14. The interface 10 functions to decompose 16-bit data words into 8-bit data words during the write cycle. . Such a function would be advantageous in applications utilizing floppy drives, hard disk drives, and like devices. The interface 10 reduces the work load

SUBSTΓΓUTE SHEET on the host system by simulating a DMA transfer to the peripheral device. Instead of having the host system performing 8-bit transfers, the DMA interface 10 receives a full 16-bit data transfer, reducing by half the number of DMA cycles required to perform DMA data transfers and thereby increasing the throughput of the system 12.

FIG. 8 depicts a flow chart which further describes the write cycle implementε by the interface 10. In step 802, the preblock interrupt PREINT signal is enabled by the first DRQ signal coming from the peripheral device 14. After the preblock interrupt signal is enabled, the execution proceeds to step 804 where the host system 12 programs the interface 10 with the location of the data starting address, the byte count to be transferred, and the type of data transfer. The interface 10, in turn, programs the peripheral device 14 with this information. In step 806, a determination is made whether the DRQ signal received by the interface 10 is even. This is done to determine which half of the 16-bit data word is to be transferred to the peripheral device 14. If the DRQ signal is the first DRQ signal representing the first 8 bits of data to be transferred, execution proceeds to step 808. In step 808, the state machine 58 passes the DRQ signal to the system 12. In step 810, the host system 12 generates a system data acknowledge (SDACK) signal followed by a system I/O write (SIOR) signal. These signals are passed to the peripheral device 14 through the interface 10. The system 10 then outputs a 16-bit word of data to the interface 10. In step 812, the interface 10 receiving the 16-bit word decomposes it into upper and lower 8-bit bytes, whereby the lower (0..7) byte is immediately passed through the buffer (not shown) of the block 56 to the peripheral device 14, and the upper (8..15) byte is stored in the the latch (also not shown) of the block 56. After this upper byte is latched, execution proceeds to step 814. In step 814, the interface 10 waits for the next DRQ signal from the peripheral device 14. Upon receipt of the next DRQ signal, execution returns to step 806.

If in step 806 the next DRQ signal is not even, control proceeds to step 816. Since the first DRQ was even, then this next DRQ is odd and execution proceeds to step 816 with the lower byte of data still in the latch of the block 56. In step 816 a determination is made whether an I/O instruction has occurred at the same time as the next DRQ signal being received by the interface 10. If an I/O instruction occurs at the same time as the DRQ signal is sent from the peripheral device 14, there is rivalry for the bus 16. In this event, the arbitration scheme of the state machine 58 is implemented. The arbitration scheme implemented by the state machine 58 is subsequently discussed with reference to FIG. 9.

If in step 816 it is determined that an I/O instruction is not occurring at this time, then execution proceeds to step 818. In step 818, the state machine 58 generates a false data acknowledge (DACK) signal and a false I/O read (DIOR) signal which are propagated to the peripheral device 14. The false DACK signal is used to enable the data latch of the block 56 for sending the upper data byte to the peripheral device 14. The false I/O write (FIOW) signal is used for initiating the writing or transfer of the upper data byte from the interface 10 to the peripheral device 14. In step 820, the upper data byte is output from the latch of th block 56 and written directly to the peripheral device 14. Execution proceeds to step 822 where a determination is made whether the last data block has been transferred, as determined by the status of a counter. If in step 822 the counter does not equal zero, additional data remains to be written to the peripheral device 14 and control returns to step 814. If in step 822 the counter equals zero, execution proceeds to step 824. In step 824, an interrupt signal is generated to pull the system 12 out of the halt state. In step 826, the DMA write cycle is completed and ends.

In FIG. 9, there is depicted a flowchart of the arbitration scheme for handling contention for the host bus 16 involving a DMA write operation. In the event of the false DMA cycle is occurring at the same time as the host system I/O cycle, then the arbitration scheme is activated from step 816 in FIG. 8. In step 900 of FIG. 9, a decision is made whether the positive edge of the clock cycle of the processor 32 is next. If the clock cycle of the processor 32 is approaching the positive edge, execution proceeds to step 902. In step 902, the false DMA cycle of the interface 10 is served first, instead of the system 12 I/O cycle, also contending for the bus 16. In step 904 a wait state is issued to the host processor 32 causing a delay in the system I/O cycle. The wait state is issued by deactivating the I/O ready control line 62. In step 906, the false DMA cycle is initiated by generating the FDACK and FIOR control signals. The FDACK and FIOR signals are used to enable the latch 56 and initiate the data transfer to the peripheral device 14. In step 908,- the upper data byte stored in the. latch 56 is output from the latch to the peripheral device 14 in a write operation initiated by the interface 10. In step

SUBSTITUTE SHEET 910, after serving the false DMA cycle, the interface 10 will enable the host processor 32 to execute a system I/O cycle. In step 910, the I/O cycle is enabled by reactivating the I/O ready control line 62. After the I/O cycle is completed, execution returns to step 814, in FIG. 8, to complete the DMA write cycle.

If in step 900, the clock cycle of the processor 32 is approaching a negative clock edge, then execution proceeds to step 912 in FIG. 9. In step 912, the I/O cycle of the host system 12 is served instead of the false DMA cycle of the interface 10. In step 914, the false DMA cycle is delayed so that the I/O cycle can take place. In step 916, the system I/O cycle is initiated and completed. In step 918, the interface 10 generates the FDACK and FIOR control signals to the peripheral 14. The FDACK signal will enable the latch 55 and the FIOR signal will initiate the data write to the peripheral device 14. In step 920, the upper data byte is written from the latch 56 to the peripheral device 14. Execution then returns to step 814 in FIG. 8.

FIG. 10 illustrates a timing diagram for the DMA write operation involving the CDDRQ control line 90, the SDACK control line 70, the BCDIOW control line 86 and the data bus 22, all of which lines are also shown in FIG. 2. In FIG. 10 at time 602, the peripheral device 14 sends to the interface 10 the first DRQ signal on the CDDRQ control line 90. The first DRQ signal is passed by the state machine 58 to the host system 12. The host system 12 responds at time 1004 by issuing a system data acknowledge (SDACK) signal on the line 70. At time 1006, the system 12 issues a system I/O write (SIOR) signal on the line 86. Both of these signals are passed by the interface 10

SUBSTITUTESHEET to the peripheral device 14. At time 1008 the system 12 outputs a 16-bit word of data to the interface 10 on the line 22. At this same time 1008, the 16-bit word is decomposed so that the lower byte is directly passed on co the peripheral device 14 on the line 28. The remaining upper byte is latched in the latch 56.

At time 1010, a second DRQ request is received by the state machine 58 from the peripheral device 14 on the line 90, which ir ~*ot passed to the system 12. In response, at time 1012 t lse data acknowledge (FDACK) signal is sent on the BCDI, ^* control lir. 88 by the state machine 58 to the periph_* __. device 14. ; time 1014 a false I/O write (FIOW) signal is aent b;

state machine 58 on the BCDIOW control lire 86 tc 3 peripheral device 14. The peripheral device 4 will ^" n output the upper data byte latched in the latch 56 « the peripheral device 14. At time 1016 the next DRQ signal is received from the peripheral device 14, which is treated in the same manner as the first DRQ at time 1002.

FIGS. 11a and lib illustrate timing diagrams for the arbitration scheme of the interface 10 implemented when there is contention for the host bus 16 due to both a peripheral device DMA write data transfer and a system I/O request involving the system 10. FIG. lla illustrates the case where the DMA data transfer obtains priority over the bus 16 and FIG. lib illustrates the case where the system I/O cycle obtains priority.

In FIG. lla, the status of the system clock for the processor 32 is designated by the timing line 1100. The timing line 1102 represents the status on an I/O cycle signal in the state machine 58 designated as P30X I/O read/write (P30XIOR/W) (not shown), which represents a

SUBSTITUTESHEET decoded address qualified with an I/O command to the state machine. The timing line 1104 shows the status of the first DRQ signal from the peripheral device 14. At time 1106, both the P30XIOR/W signal and the DRQ signal are occurring at the same time. In this case, there is contention for the host bus 16. Time 1106 occurs prior to the system clock approaching a positive edge which then occurs at time 1108. Consequently, the false DMA cycle is served first by delaying the system I/O cycle. Also at time 1106, the SIOR signal is moved low. It is held low by the READY signal on the line 1110. At time 1112, the READY signal is moved low in order to issue a wait state to the host processor 32, thereby delaying the system I/O cycle. The state machine 58 initiates the false DMA cycle by issuing an FDACK signal as shown by the timing line 1116, at time 1114. At time 1118 the FIOW signal is issued as shown on the timing line 1120. After the false DMA cycle is completed in which the upper data byte is written to the peripheral device 14, the READY signal on the line 1110 goes high at time 1119 signifying that the peripheral device 14 is now ready to execute an I/O command. The host processor 32 completes the I/O command by deactivating the SIOW signal at time 1122 as shown on timing line 1124.

In FIG. lib, the P30XIOR/W and DRQ signals occur concurrently at time 1126, indicating contention for the bus 16. Time 1126 occurs prior to the system clock approaching a falling edge or negative portion of the clock cycle on the line 1100 at time 1128. Consequently, the false DMA cycle is delayed and the system I/O cycle is served first. This is accomplished by delaying the false DMA acknowledge (FDACK) and the false I/O read (FIOR) signals until the system I/O cycle ^• is finished. The system I/O cycle is initiated by issuing a system I/O write (SIOW) signal at time 1130 as shown on the line 1124. Upon completion of the system I/O cycle at time 1132 the SIOW signal goes high as shown on the line 1124. At time 1134 the state machine 58 issues an FDACK signal as shown on the line 1116 and at time 1136 issues a FIOW signal as shown on the line 1120, thereby initiating the false DMA cycle. The DMA interface 10 will then continue in its execution of a DMA transfer.

It is understood that variations may be made in the present invention without departing from the spirit and scope of the invention. For example, the interface 10 may be alternatively configured so that it is integrated in either the system 12 or the device 14. Further, it will be appreciated that the entire interface may be embodied as a single integrated circuit chip, or any varying combination of discrete digital or analog components interconnected in a standard manner. The peripheral device may be other types of data storage devices or devices intended for supplying some form of information to the system 12. The system 12 may be a multimedia computer or other appliance. The data width of the buses interconnected by the interface may be different than shown in the present embodiment. For example, the computer could have a 32-bit bus and the peripheral device either an 8-bit or 16-bit bus, or vice-versa. Other combinations are contemplated involving a bus .having a data bus width (M) which is an integer multiple of a bus having ^' a ^' data ^" bus width (N) , the buses being interconnected by the interface and employing the appropriate data storage block configurations for DMA read and/or DMA write operations.

SUBSTITUTE SHEET Although illustrative embodiments of the invention have been shown and described, a latitude of modification, change and substitution is intended in the foregoing disclosure and in some instances some features of the invention will be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

SUBSTITUTESHEET

Claims

WHAT IS CLAIMED IS:

1. An interface apparatus for regulating direct memory access data transfer operations between a first device having a data bus of a first data width and a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the apparatus comprising: means for intercepting at least one data request signal sent from said first device and for emulating control signals of said second device in response to said at least one data request signal in order to initiate transfer of data independent of said second device, and for passing to said second device another data request signal sent from said first device in order to allow said second device to initiate transfer of data; and means for receiving data being transferred between said devices and storing at least one data block of said first data width, such that responsive to said another data request signal, data is transferred with respect to said second device as a single data block of said second data width.

2. The apparatus of claim 1 such that when said data is being transferred from said first device to said second device, said at least one data block is stored responsive to said at least one data request signal, and responsive to said another data request signal, a data block of said first data width is received and composed with said at least one stored data block and passed to said second device as said single data block of said second data width.

3. The apparatus of claim 1 such that when said data is being transferred from said second device to said first device, responsive to said another data request signal said single block of data of said second width is transferred to said receiving means and said single block is decomposed into a data block of said first data width which is passed to said first device, and at least one data block of said first data width which is stored, and responsive to said at least one data request signal said at least one stored data block is then transferred to said first device.

4. The apparatus of claim 1 further comprising: means for prioritizing access to said data bus of said second device upon simultaneous issuance of a data request signal sent from said first device and an input/output command signal sent from said second device.

5. The apparatus of claim 4 wherein said prioritizing means determine which of said data request signal and said command signal will be given access to said bus first based on the state of an internal clock of said second device.

6. The apparatus of claim 5 wherein one of said data request and command signals is processed first when said internal clock is in a high state and the other of said data request and command signals is processed first when said internal clock is in a low state.

7. The apparatus of claim 1 wherein said intercepting means comprises a state machine.

8. The apparatus of claim 1 wherein said receiving means comprises buffer means for receiving and passing said data.

9. The apparatus of claim 1 wherein said receiving means comprises latch means for temporarily storing said data.

SUBSTITUTE SHEET

10. An interface apparatus for regulating direct memory access operations for reading data from a first device having a data bus of a first data width to a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the apparatus comprising: means for intercepting at least one successive data request signal sent from said first device and for emulating control signals of said second device in response to said at least one data request signal in order to initiate transfer of at least one data block of said first data width from said first device independent of said second device, and for passing a subsequent data request signal from said first device to said second device in order to allow said second device to initiate transfer of a subsequent data block of said first data width from said first device; and means for receiving data being transferred from said first device and for temporarily storing said at least one data block, such that in response to said at least one successive data request signal, said at least one data block is temporarily stored, and in response to said subsequent data request signal, said subsequent data block and said at least one stored data block are passed together to said second device as a single data block of said second data width.

SUBSTITUTE SHEET

11. The apparatus of claim 10 further comprising: means for prioritizing access to said data bus of said second device upon simultaneous issuance of a data request signal sent from said first device and an input/output command signal sent from said second device.

12. The apparatus of claim 11 wherein said prioritizing means determine which of said data request signal and said command signal will be given access to said bus first based on the state of an internal clock of said second device.

13. The apparatus of claim 12 wherein one of said data request and command signals is processed first when said internal clock is in a high state and the other of said data request and command signals is processed first when said internal clock is in a low state.

14. The apparatus of claim 10 wherein said intercepting means comprises a state machine.

15. The apparatus of claim 10 wherein said receiving means comprises buffer means for receiving and passing said data.

16. The appparatus of claim 10 wherein said receiving means comprises latch means for temporarily storing said data.

17. The apparatus of claim 10 wherein said emulated control signals comprise data acknowledge signals.

18. The apparatus of claim 10 wherein said emulated control signals comprise data input/output read signals.

19. The apparatus of claim 10 wherein said first device comprises a peripheral^' device and said second device comprises a host computer.

20. The apparatus of claim 10 wherein said second data width is twice said first data width.

21. Interface apparatus for regulating direct memory access operations for reading data from a first device having a data bus of a first data width to a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the apparatus comprising: at least one data buffer for receiving data being transferred from said first device; at least one data latch for temporarily storing data being transferred from said first device; and a state machine for intercepting at least one successive data request signal sent from said first device and for emulating control signals of said second device in response to said at least one data request signal in order to initiate transfer of at least one data block of said first data width from said first device independent of said second device, and for passing a subsequent data request signal from said first device to said second device in order to allow said second device to initiate transfer of a subsequent data block of said first data width from said first device; such that in response to said at least one successive data request signal, said at least one data block is temporarily stored in said at least one data latch, and in response to said subsequent data request signal, said subsequent data block is received in said at least one data buffer and passed together with said at least one stored data block to said second device as a single data block of said second data width.

SUBSTITUTE SHEET

22. An interface apparatus for regulating direct memory access operations for writing data to a first device having a data bus of a first data width from a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the apparatus comprising: means for receiving a data block of said second data width from said second device fcr transfer to said first device, said data block of said second data width being decomposed so that a data block of said first data width is passed to said first device and at least one data block of said first data width is temporarily stored; and means for passing an initial data request signal from said first device to said second device in order to allow said second device to initiate transfer of said data block of said second data width, and for intercepting at least one subsequent ^data request signal sent from said first device and for emulating control signals of said second device in order to initiate transfer of said at least one stored data block from said receiving means to said first device independent of said second device.

23. The apparatus of claim 22 wherein said emulated control signals comprise data input output write signals,

SUBSTITUTE SHEET

24. A method for regulating direct memory access data transfer operations between a first device having a data bus of a first data width and a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the method comprising: intercepting at least one data request signal sent from said first device; emulating control signals of said second device in response to said at least one data request signal in order to initiate transfer of data independent of said second device; passing to said second device another data request signal sent from said first device in order to allow said second device to initiate transfer of data; and receiving data being transferred between said devices and storing at least one data block of said first data width, such that responsive to said another data request signal, data is transferred with respect to said second device as a single data block of said second data width.

25. A method for regulating direct memory access data transfer operations between a first device having a data bus of a first data width and a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the method comprising: intercepting at least one data request signal sent from said first device; emulating control signals of said second device in response to said at least one data request signal in order to initiate transfer of data independent of said second device; responsive to said at least one data request signal, temporarily storing at least one data block of said first data width; passing to said second device another data request signal sent from said first device in order to allow said second device to initiate transfer of data; and responsive to said another data request signal, passing a data block of said first data width and said at least one stored data block together to said second device as a single data block of said second data width.

26. The method of claim 24 further comprising: prioritizing access to said data bus of said second device upon simultaneous issuance of a data request signal sent from said first device and an input/output command signal sent from said second device.

27. The method of claim 25 wherein said prioritization is determined based on the state of an internal clock of said second device.

28. The method of claim 26 wherein one of said data request and command signals is processed first when said internal clock is in a high state and the other of said data request and command signals is processed first when said internal clock is in a low state.

SUBSTITUTESHEET

29. A method for regulating direct memory access operations for writing data to a first device having a data bus of a first data width from a second device having a data bus of a second data width, said second data width being an integer multiple of said first data width, the method comprising: passing to said second device an initial data transfer request signal sent from said first device in order to allow said second device to initiate transfer of data; responsive to said initial data request signal, transferring a single block of data of said second data width from said second device; decomposing said single block of data into at least two data blocks of said first data width; passing one of said data blocks of said first data width to said first device; storing the other at least one of said data block; intercepting at least one subsequent data request signal sent from said first device; emulating control signals of said second device in response to said at least one subsequent data request signal in order to initiate transfer of said at least one stored data block to said first device; and responsive to said emulated control signals, transferring said at least one stored data block to said first device.

IBSTITUTE SHEET