JPH01150958A - Device for arbitrating bus - Google Patents

Abstract

PURPOSE:To eliminate a hardware, which uses a sequencer and a buffer RAM, by dividing a data transferring bus into a period, which is occupied by a microprocessor, and a period, which can be occupied by a DMAC (Direct Memary Access Controller), with using the output signal of an oscillator. CONSTITUTION:The oscillator to generate the rectangular wave of a cycle T is used. Then, a data transferring bus 2 is divided into a period K (0<=K<=T), which is occupied by a microprocessor 1, and a period L (L=T-K), which can be occupied by >=1 DMACs 3, and used. Then, the microprocessor 1 can secure the occupying right of the data transferring bus 2 with a constant cycle and rate. Thus, hardware quantity is caused to be reduced and even in any case in data reception, an overflow is not executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bus arbitration device for computers, workstations, etc., which arbitrates between a plurality of bus masters arranged on the same data transfer bus.

2. Description of the Related Art In recent years, with the development of microprocessor sensor application technology, the number of personal computers (hereinafter referred to as personal computers) and workstations that support communication using R3232C and the like has increased.

In order to speed up processing, these devices use a direct memory access controller (hereinafter referred to as DMAC) in addition to a microprocessor. Therefore, since there are two bus masters on the same data transfer bus, a bus arbitration circuit is required.

An example of the above-mentioned personal computer will be described below with reference to the drawings. FIG. 2 is a block diagram showing the inside of a conventional personal computer, centering on the communication section.

In FIG. 2, 20 is a microprocessor, 121 is a data transfer bus, 22 is a DMAC 123 is a sequencer,
24 is a buffer RAM 2 for temporarily storing data sent through the external interface circuit 25;
5 is an external interface circuit that receives data sent from the outside; 26 is a RAM arranged on the data transfer bus 21;

27 is data sent from an external device, 28 is a first included signal that the external interface circuit 25 issues to the sequencer 23, and 29 is a second included signal that the sequencer 23 issues to the microprocessor 20.

The operation of the personal computer configured as described above will be explained below, focusing on arbitration of the data transfer bus.

First, when the external interface circuit 25 receives data 27 from an external device into an internal reception buffer, it issues a first included signal 28 to the sequencer 23 .

The sequencer 23 reads the data received by the external interface circuit 25 and writes it into the buffer RAM 24, and simultaneously issues a second included signal 29 to the microprocessor 20. The external interface circuit 25 negates the first included signal 28 when the internal receive buffer becomes empty. microprocessor
When 20 receives the second included signal 29, if it is the bus master and there is no task that has priority over the data receiving task, it sends the buffer R via the sequencer 23.
Read the data stored in AM24 and transfer it to RAM26.
Store inside. When there is no more received data in the buffer RAM 24, the sequencer 23 negates the second included signal 29. If microprocessor-20
and the external interface circuit 25, the sequencer 23
, if the buffer RAM 24 does not exist, when the external interface circuit 25 receives the data 27, the DMAC
If 22 is the bus mask -, overflow will occur if data 27 is sent one after another. In this way, if a plurality of bus masters exist on the same data transfer bus and an overflow may occur, a sequencer 23 and a buffer RAM 24 are provided between the external interface circuit 25 and the microprocessor 20 to provide a hardware buffer. Do the ring.

Problems to be Solved by the Invention However, the above configuration has the problem of increasing the amount of hardware because it requires a sequencer and a buffer RAM. In particular, the hardware of a sequencer is extremely complex because it implements complex functions such as generating addresses in a buffer RAM, reading and writing data, and processing included signals. It is also possible to use hardware that passes the data transfer bus to the DMAC using the data reception included signal.

However, when using a microprocessor with a built-in external interface circuit, the interlaced signal is not output to the outside of the microprocessor, so if an external DMAC occupies the bus, an overflow will occur. In this case, it is also impossible to use the sequencer and buffer RAM described above.

In view of the above problems, the present invention provides a bus arbitration device that does not cause overflow during data reception and requires less hardware.

Means for Solving the Problems In order to solve the above problems, the bus arbitration device of the present invention has the following features:
A period K (0≦K≦
T) and the period L (
It has a configuration in which it is divided into two parts (L-T-K) and used.

Effects of the present invention Due to the above-described configuration, the amount of hardware can be reduced, and overflow will not occur in any case during data reception.

Embodiment Hereinafter, a bus arbitration device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of a bus arbitration device in an embodiment of the present invention, in which 1 is a microprocessor, 12 is a data transfer bus, 3 is a DMAC, 4 is an external interface circuit, and 5 is a frequency divider 6. An input clock signal, 6 is a frequency divider that divides the input clock signal 5 by a frequency division ratio M (M=1.2.3...) indicated by the microprocessor-1, 7 is a frequency divider 6 8 is a decimal counter that counts the output clock signal 7, 9 is the count output value of counter 8, 10
is a comparator that compares the count output value 9 and the occupancy setting value 12; 11 is set by the microprocessor-1;
A 4-bit occupancy setting register that can set the maximum occupancy at which the DMAC 5 can become a bus master; 12 is an occupancy setting value output from the occupancy setting register 11; 13 is a DMA permission signal output from the comparator 10; 14 is a RAM arranged on the data transfer bus 2, 15 is data sent from an external device, and 16 is an external ink-face circuit 4.
is an included signal issued to microprocessor-1.

The operation of the bus arbitration device configured as described above will be explained below with reference to FIG.

First, the microprocessor 1 sends the frequency division ratio M of the human clock signal 5 to the frequency divider 6 via the data transfer bus 2, and sends the maximum occupancy J of the DMAC to the occupancy setting register 11 (J=
0.1. ..., 10) with the 6 frequency divider 6
The frequency-divided output clock signal 7 is counted by a counter 8, and the count result (0, 1, . . . , 9) is output. The comparator 10 compares the count output value 9 with the occupancy setting value 12, and the count output value 9 becomes the occupancy setting value 1.
If it is smaller than 2, the DMA permission signal 13 is asserted, and it is determined whether the count output value 9 is equal to the occupancy setting value 12 or not.
When it is larger, the DMA grant signal 13 is negated.

When the DMA permission signal 13 is asserted, the DM
AC5 can become a bus master and occupy data transfer bus 2, but DMAC5 cannot become a bus master of data transfer bus 2 when DMA permission signal 13 is negated. If DMA enable signal 13 is negated when DMAC5 is the bus master, D
MAC 5 immediately hands over the bus, and microprocessor 1 becomes the bus master.

For example, if 4 is set in the occupancy setting register 11, the DMA permission signal 1 will be activated when the count output value 9 is 0.1.2.3.
3 is asserted, resulting in DMAC5 up to 40
% can become the bus master of data transfer bus 2. Of course, when the DMA permission signal 13 is asserted and the DMAC 5 does not require exclusive ownership of the data transfer bus 2, the microprocessor-1 becomes the bus master. Frequency division ratio M of frequency divider 6 and occupancy setting register 1
1 can be set by the microprocessor, so D
The period and duty of the MA permission signal 13 can be selected as arbitrary values.

A case will be described below in which a microprocessor system using the above bus arbitration device receives data from the outside at a transfer rate of 9600 bps (bit/5ec) using an R3232C interface. R32
32C is a serial transfer, and when a start bit, stop bit, etc. are added, one byte is transferred in about 1 m5ec. Therefore, if the DMAC 5 continuously occupies the data transfer bus 2 for more than 1 m5ec, an overflow may occur. Therefore, the period of the DMA permission signal 13 is set to 1m5e.
It must be less than c.

Now human power clock signal 5 as microprocessor 1
Using a clock obtained by dividing the clock input (lOMllz) by three, the following equation holds true.

lX10-8>MX10X3/(10X106) From this formula, M< 100/3 Here, if M=32 (=25), the period T is approximately 1 m
5ec (999/Jsec). The included processing time of the microprocessor-1 by the included signal 16 (reading 1 byte of data from the external interface circuit 4 using the interwoven processing routine and RA
If the time required for buffering to M14 is 300 μsec at maximum, then at least 300 psec is required for the period during which the microprocessor-1 occupies the data transfer bus 2 during a period of 1 m5 ec. Therefore, it is sufficient to set 7 in the occupancy setting register 11 as the maximum occupancy of the DMAC 5. DM if DMAC5 is the bus master
For example, a method for making the data transfer bus 2 pass by negating the A permission signal 13 is to input a halt (stop) signal to the DMAC 5, or even if the transfer being performed by the DMAC 5 is due to an external transfer request signal. This can be easily realized by forcibly negating the signal using the DMA permission signal 13.

As described above, according to the present embodiment, an oscillator that generates a rectangular wave with a period T is used to control the period K (0≦K≦T) during which the microprocessor occupies the data transfer bus, and one or more DM
By dividing the bus into AC-occupied periods L (L=T-K), the microprocessor can secure the exclusive right to the data transfer bus at a constant cycle and rate.

In the above embodiment, the frequency divider 6, the counter 8, the comparator 10, and the occupancy setting register 11 are used as the oscillator, but the oscillator is not limited to this, and the output signal is used to perform the oscillator at a constant period. Any device may be used as long as it can divide the data transfer bus 2 into a period in which the microprocessor 1 occupies it and a period in which the DMAC 5 occupies it. For example, it is also possible to use a timer IC or an oscillator with a constant period and duty.

Effects of the Invention As described above, the present invention uses the output signal of the oscillator to determine the period during which the microprocessor occupies the data transfer bus and the DM.
By dividing the AC into periods that can be occupied,
In a system that involves an operation of receiving data from the outside, complicated hardware using a sequencer and a buffer RAM becomes unnecessary. Furthermore, even when a microprocessor with a built-in external interface circuit is used, the microprocessor can periodically secure a data transfer bus at a constant rate, making it possible to prevent reception errors due to overflow.

In addition, by making the oscillator cycle and duty programmable, the microprocessor's data bus occupancy can be set arbitrarily, making it possible to perform tasks that require real-time performance using a microprocessor capable of multitasking. This is very effective because a certain amount of microprocessor processing time can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a bus arbitration device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the inside of a conventional personal computer, centering on the communication section. 1.20...Microprocessor-12,21
...Data transfer bus, 3,22...D
MAC, 4゜25...External interface circuit, 5...Manual clock signal, 7...
Output clock signal, 9-... Count output value, 1
2...Occupancy setting value, 13...DMA
Permission signal, 15.27... Data, 16...
...included signal, 28...first included signal, 29...second included signal. Name of agent: Patent attorney Toshio Nakao Haka1 person 1st rl!
J Figure 2

Claims (2)

[Claims] (1) When a microprocessor and one or more direct memory access controllers use the same data transfer bus, the period K during which the microprocessor occupies the data transfer bus using an oscillator that generates a rectangular wave with a period T (0≦K≦T) and the period L that can be occupied by the one or more direct memory access controllers
A bus arbitration device characterized in that it is used by dividing into (L=T-K). (2) a frequency divider that divides and outputs the input clock signal by an arbitrary frequency division ratio according to instructions from the microprocessor; a counter that counts the output clock signal of the frequency divider; and the microprocessor. The present invention is characterized by using an oscillator that includes an occupancy setting register that sets the occupancy according to the occupancy setting register, and a comparator that compares the set value of the occupancy setting register with the output value of the counter and outputs the comparison result. A bus arbitration device according to claim (1).