JP2996172B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and a direct memory access controller (hereinafter referred to as D).
MAC) connected to the same data bus, and more particularly to a bus arbitration circuit.

[0002]

2. Description of the Related Art In computer systems such as personal computers and workstations, one or more DMACs are provided in addition to a microprocessor in order to speed up processing. In this case, since two or more bus masters exist on the same data bus, a bus arbitration circuit is required. A conventional computer system will be described with reference to FIG. 5 (refer to JP-A-1-150958). In FIG. 5, a microprocessor 2 and a DMAC 3 are connected to a data bus 1 as a bus master. 4 is an input / output interface for inputting / outputting data,
5 is a RAM. The bus arbitration circuit 6 outputs the clock signal C
Frequency divider 61 for inputting LK, counter 62 for counting the output of frequency divider 61, register 63 for storing occupancy CNTR in which DMAC 3 can be a bus master, and counter 6
2 has a comparator 64 for comparing the content CNT of No. 2 with the occupancy CNTR of the register 63. The frequency division ratio N of the frequency divider 61 and the occupancy CNTR of the register 63 are set by the microprocessor 2.

Next, the operation of the bus arbitration circuit 6 will be described.
According to the input of the clock signal CLK, the contents of the counter 62 are 0, 1, 2,..., MAX (maximum value), 0, 1, 2,.
It changes repeatedly as MAX and ─. As a result, the counter 6
2 is smaller than the occupancy CNTR of the register 63 (CNT <CNTR), the DMA permission signal S
1 is asserted. On the other hand, when the content CNT of the counter 62 is equal to or larger than the occupancy CNTR of the register 63 (CNT ≧ CNTR), the DMA enable signal S1
Is negated. If the DMA permission signal S1 is asserted, the DMAC 3 generates a bus occupation request signal S2 to the microprocessor 2, receives the hold state signal S3 of the microprocessor 2 and becomes a bus master, and can occupy the data bus 1. On the other hand, if the DMA permission signal S1 is negated, the DMAC 3 cannot become a bus master,
That is, the microprocessor 2 can occupy the data bus 1 as a bus master. Therefore, if the DMAC 3 is negated while the DMAC 3 is the bus master, the DMAC 3 immediately gives up the data bus 1 and the microprocessor 2 becomes the bus master.

As described above, when the content CNT of the counter 62 changes, the period in which the microprocessor 2 occupies the data bus 1 and the period in which the DMAC 3 can occupy the data bus 1 are periodically divided and repeated. Therefore, the occupation of the data bus 1 by the microprocessor 2 can be ensured periodically. The period and the duty ratio are determined by the setting of the dividing ratio N of the divider 61 and the occupancy CNTR of the register 63 by the microprocessor 2, so that the occupation time of the data bus 1 by the microprocessor 2 is always ensured. .

Another conventional computer system has a bus lock function when a microprocessor wants to occupy a data bus. That is, the microprocessor issues a bus lock instruction to monopolize the right to use the data bus, and prohibits the use of the data bus of another bus master while the microprocessor is executing the instruction following the bus lock instruction. is there.

[0006]

However, in the conventional computer system shown in FIG.
During a period in which the data bus 3 can occupy the data bus 2, the DMA request is accepted and the processing of the microprocessor 2 is forcibly suspended, so that the microprocessor 2 cannot use the data bus 1 preferentially. . Also, DM
Even when the A request is small, the right to use the data bus 1 is transferred to the DMAC 3, and there is a problem that the microprocessor 2 cannot use the data bus 1 preferentially. This is because the period and the duty ratio are changed by the microprocessor 2 and the microprocessor 2
The occupation period of the data bus 1 may be set to 100%.
Another problem arises that the setting load on the microprocessor 2 increases.

Further, when the bus lock function is incorporated into the program of the microprocessor, there occurs a period during which the other bus master cannot use the data bus at all, so that there is a problem that it is difficult to set the period. Accordingly, an object of the present invention is to provide a computer system which can prioritize the processing of a microprocessor while responding to a DMA request.

[0008]

In order to solve the above-mentioned problems, the present invention comprises a counting means for counting DMA requests, and a comparing means for comparing the counted number of DMA requests with a predetermined value. DMA when the number of times matches a predetermined value
C occupies the data bus and processes DMA requests. Furthermore, the end of DMAC data bus occupation
Timer means for measuring a predetermined time after being cleared is provided, and the DMA occupies the data bus for each overflow signal of the timer means. That is, if either the coincidence signal of the comparing means or the overflow signal of the timer means is output, the DMA request is not accepted, and the microprocessor preferentially monopolizes the data bus. Further, the overflow signal of the timer means can be handled in the same manner as the DMA request signal.

[0009]

FIG. 1 is a block circuit diagram showing a first embodiment of a computer system according to the present invention. In FIG. 1, instead of the bus arbitration circuit 6 of FIG.
A bus arbitration circuit 7 is provided. In the bus arbitration circuit 7, a counter 71 that receives and counts an external DMA request signal REQ, a DMA request reception count (CNT)
R ') register 72 for storing, and the content CNT of the counter 71' comparator 73 for comparing the content (CNTR ') of a register 72 are provided, the coincidence signal S 4 of the comparator 73 is an OR circuit DMA permission signal S via
It becomes 1. Also, a timer 75 is provided, and the overflow signal S5 of the timer 75 also becomes the DMA permission signal S1 via the OR circuit 74.

The operation of the computer system shown in FIG. 1 will be described with reference to FIG. Note that the microprocessor 2 sets the number of times of receiving a DMA request CNTR ′ in the register 72 to, for example, 3 and supplies a count clock signal to the timer 75 in advance. Also, as an initial setting,
It is assumed that the content CNT 'of the counter 71 has been cleared as shown in FIG.
Microprocessor (CPU) as shown in FIG.
2. When the DMA request signal REQ is input as shown in FIG.
Changes as shown in FIG. 2 (B). As a result,
When CNT ′ = 3, the comparator 73 generates the coincidence signal S4 shown in FIG. 2C, and the OR circuit 74 turns the DMA enable signal S1 shown in FIG. In response, the DMAC 3 generates a bus occupation request signal S2 shown in FIG.
As a result, after being separated from the data bus 1, the microprocessor 2 outputs the hold state signal S shown in FIG.
3 is sent to DMAC3. As a result, as shown in FIG. 2H, the bus master of the data bus 2 is the DMAC 3. Once the right to use the bus shifts to DMAC3, the DM
AC3 indicates the number of times the DMA request has been suspended (CNTR '=
3) Data transfer is performed continuously from the DMA having the highest priority (DMA1, DMA2, DM in (H) of FIG. 2).
A3). If the next DMA request REQ is received before the data transfer of this DMA is completed, this DM
The A request is also accepted and transferred continuously ((H) in FIG. 2).
DMA4).

When the data transfer of all DMAs is completed, the DMAC 3 clears the counter 71 and the timer 75, and at the same time, as shown in FIG.
C3 resets the bus occupation request signal S2, so that the microprocessor 2 resets the hold state signal S3 as shown in FIG. Therefore, as shown in FIG. 2H, the microprocessor 2 becomes the bus master again.

On the other hand, as shown by X1 in FIG.
When the overflow signal S5 of the timer 75 is generated, the OR circuit 74 again generates the DMA permission signal S1 shown in FIG. In response, the DMAC 3 generates a bus occupation request signal S2 shown in FIG. 2 (F) to the microprocessor 2, and as a result, after being separated from the data bus 1, the microprocessor 2 ) Is sent to the DMAC3. As a result, FIG.
As shown in (H) of FIG.
MAC3. When the right to use the bus shifts to the DMAC3, the DMAC3 continuously performs data transfer by the number of times the DMA request is suspended from the higher DMA priority (see the DMA in (H) of FIG. 2). When the DMA data transfer is completed, the DMAC 3 clears the counter 71 and the timer 75, and at the same time, as shown in FIG. 2F, the DMAC 3 resets the bus occupation request signal S2. As shown in FIG. 2G, the microprocessor 2 resets the hold state signal S3. Therefore, as shown in FIG. 2H, the microprocessor 2 becomes the bus master again.

Further, as shown by X2 in FIG. 2 (D),
Even when the overflow signal S5 of the timer 75 is generated, the OR circuit 74 again generates the DMA permission signal S1 shown in FIG. 2E. However, since there is no DMA request, the bus occupation request signal S2 is not generated. Therefore, the hold state signal S
No 3 is generated. As a result, as shown in FIG. 2H, the bus master of the data bus 2 continues to be the microprocessor 2.

As described above, in the first embodiment of the present invention, the match signal S4 of the comparator 73 or the timer 7
The DMA request is not accepted until one of the overflow signals S5 of No. 5 is output, and the microprocessor 2 monopolizes the data bus 1 preferentially. That is, when a plurality of DMA requests are suspended, the DMA request is accepted. On the other hand, even when the number of DMA requests is small, if a certain period of time has passed, the DMA request is accepted by the overflow signal S5.
The MA request is not extremely waited.

FIG. 3 is a block circuit diagram showing a second embodiment of the computer system according to the present invention. FIG.
In the bus arbitration circuit 7 ', an OR circuit 76 is provided instead of the OR circuit 74 in FIG. Thereby, the overflow signal S5 of the timer 75 is changed to the DMA request signal REQ.
And the match signal S4 of the comparator 73 is
The permission signal S1 was used.

The operation of the computer system shown in FIG. 3 will be described with reference to FIG. Also in this case, the microprocessor 2 stores the number of DMA request receptions CN in the register 72 in advance.
TR ′ is set to, for example, 3 and the timer 75
Is supplied with a count clock signal. As an initial setting, the content CNT 'of the counter 71 is assumed to have been cleared as shown in FIG. 4B, and the bus master has a microprocessor (CPU) 2 as shown in FIG. It is. As shown in FIG.
When the DMA request signal REQ is input, the content CNT ′ of the counter 71 changes as shown in FIG. As a result, when CNT ′ = 3, the comparator 7
3 generates a coincidence signal S4, which becomes the DMA permission signal S1 shown in FIG. In response, DMAC3
Generates a bus occupation request signal S2 shown in FIG. 4 (E) to the microprocessor 2, and as a result, after being separated from the data bus 1, the microprocessor 2 outputs the hold state signal shown in FIG. Send S3 to DMAC3. As a result, the bus master of the data bus 2 becomes the DMAC 3, as shown in FIG. Once the bus use right is DMAC
3, the DMAC 3 continuously performs data transfer by the number of times the DMA request is suspended (CNTR ′ = 3), starting from the one with the highest DMA priority (DMA in FIG. 4 (G)).
1, DMA2, DMA3). If the next DMA request REQ is received before this DMA data transfer is completed, this DMA request is also received and transferred continuously (see DMA4 in FIG. 4 (G)).

When the data transfer of all DMAs is completed, the DMAC 3 clears the counter 71 and the timer 75, and at the same time, as shown in FIG.
C3 resets the bus occupancy request signal S2, so that the microprocessor 2 resets the hold state signal S3 as shown in FIG. Therefore, as shown in FIG. 4G, the microprocessor 2 becomes the bus master again.

On the other hand, when the overflow signal S5 of the timer 75 is generated as shown by Y1 and Y2 in FIG. 4C, the content CNT 'of the counter 71 is incremented by +1 as shown in FIG. 4B. As a result, CNT ′ =
When the value becomes 3, the comparator 73 generates the coincidence signal S4, which becomes the DMA permission signal S1 shown in FIG. In response, the DMAC 3 generates a bus occupation request signal S2 shown in FIG.
As a result, after being separated from the data bus 1, the microprocessor 2 outputs the hold state signal S shown in FIG.
3 is sent to DMAC3. As a result, the bus master of the data bus 2 becomes the DMAC 3, as shown in FIG. When the right to use the bus shifts to DMAC3, DMAC3
Performs data transfer continuously from the one with the highest DMA priority as many times as the number of times the DMA request is suspended (see DMA in FIG. 4 (G)). When this DMA data transfer is completed,
DMAC3 clears counter 71 and timer 75,
At the same time, as shown in FIG.
Resets the bus occupancy request signal S2, so that the microprocessor 2 resets the hold state signal S3 as shown in FIG. Therefore, as shown in FIG. 4G, the microprocessor 2 becomes the bus master again.

In the above-described second embodiment of the present invention, the number of accepted DMA requests CNTR 'of the register 72 may be set to be slightly larger than that of the first embodiment of the present invention, for example, four. . Further, the cycle of the overflow signal S5 of the timer 75 may be set to be longer than that of the first embodiment. In the embodiment of the present invention, the bus arbitration circuits 7 and 7 'are external circuits of the DMAC 3,
The internal circuit of the DMAC 3 may be used. Furthermore, DMAC
A plurality of 3s may be provided.

As described above, in the second embodiment of the present invention, the DMA request is not accepted until the match signal S4 of the comparator 73 is output, and the microprocessor 2
Preferentially monopolizes the data bus 1. That is, if multiple DMA requests are pending, the DMA request is accepted,
On the other hand, even if the number of DMA requests is small, after a certain time has elapsed, the overflow signal is handled in the same manner as the DMA request signal, so that the DMA request is not extremely waited.

[0021]

As described above, according to the present invention, D
The processing of the microprocessor can be preferentially performed while responding to the MA request.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of a computer system according to the present invention.

FIG. 2 is a timing chart showing an operation of the computer system of FIG. 1;

FIG. 3 is a block circuit diagram showing a second embodiment of the computer system according to the present invention.

FIG. 4 is a timing chart showing an operation of the computer system of FIG. 3;

FIG. 5 is a block circuit diagram showing a conventional computer system.

[Explanation of symbols]

 1 Data bus 2 Microprocessor 3 Direct memory access controller 4 I / O interface 5 RAM 6, 7, 7 'Bus arbitration circuit 71 Counter 72 Register 73 Comparator 74 OR circuit 75 Timer 76 {OR circuit S1} DMA enable signal S2 {Bus occupancy request signal S3} Hold state signal S4} Match signal S5} Overflow signal

Claims (9)

(57) [Claims] In a computer system in which a microprocessor (2) and a direct memory access controller (3) are connected to the same data bus (1), counting means (71) for counting a direct memory access request (REQ). And the counted number of direct memory access requests ( CN
T ′ ) with a predetermined value ( CNTR ′ ).
And 3) comprises a timer means (75) for a total side for a predetermined time, calculating said direct memory access controller when said direct memory access request count matches the predetermined value occupies the data bus direct so as to process the memory access request, direct Memoria each overflow of the timer means
Access request when there is an access request
A controller occupies the data bus and
And the direct memory access controller processes the data memory request.
A computer system wherein the timer means is cleared each time the tabus is occupied . 2. The computer system according to claim 1, wherein said microprocessor changes said predetermined value. 3. The computer system according to claim 1, wherein said direct memory access controller clears said counting means every time the occupation of said data bus is completed. 4. The computer according to claim 1, wherein when the direct memory access controller receives the direct memory access request while occupying the data bus, the computer occupies the data bus to continue processing the direct memory access request. system. 5. The computer system according to claim 1 , wherein the microprocessor changes the predetermined time. 6. In a computer system in which a microprocessor (2) and a direct memory access controller (3) are connected to the same data bus (1), timer means (75) for measuring a predetermined time; Counting means (7) for equally counting the overflow signal and the direct memory access request (REQ)
1) and the counted number of direct memory access requests ( CN
T ′ ) with a predetermined value ( CNTR ′ ).
3) wherein the direct memory access controller occupies the data bus and processes the direct memory access request when the number of times of the direct memory access request matches the predetermined value. Computer system. 7. The computer system according to claim 6 , wherein said microprocessor changes said predetermined value and said predetermined time. 8. The computer system according to claim 6 , wherein said direct memory access controller clears said timer means and said counting means every time the data bus is occupied. 9. The computer according to claim 6 , wherein when the direct memory access controller receives a direct memory access request while occupying the data bus, the computer occupies the data bus so as to continue processing the direct memory access request. system.