JP2000259556A - Bus arbitrating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the bus use opportunity of a low-order device all the time, to set priority so as to generally use it and to automatically cancel the continuous occupancy of a bus by a single device. SOLUTION: This device is constituted so as to arbitrate bus access request signals from a plurality of devices and to permit access to one device. In this case, the device is provided with a means (CPU 202) for setting the priority to devices, a means (CPU 202) for setting the mask time of individual devices, change means (R7-R10 and A11-A14) for masking the bus use request of a device which uses the bus, assigning the other device higher priority and determining the priority set by the order setting means (CPU 202) when all the devices are masked, a means 203 for measuring how long the bus is continuously used and special setting means (203, FF, A3, A31-A34 and R3-R6) for determining the priority of the bus access request of a specified device CPU as the highest order when the measured length reaches a prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for arbitrating bus contention when a bus for transmitting information is shared by a plurality of electric, electronic circuits and electronic elements (hereinafter referred to as devices). The present invention relates to a bus arbitration device that gives a bus use permission for each device.

[0002]

2. Description of the Related Art Conventionally, a bus arbitration device that arbitrates bus access request signals from a plurality of devices to give use of a bus to one device has been designed according to a usage form of a system including those devices, and Generally, fixed setting is performed on an electronic circuit (hardware) or software (program). This is because the bus use mode and the urgency of bus use of each device are different for each system. However, when designing for each system, there is a problem that efficiency is low, and it has been desired to provide a bus arbitration device that can be used for general purposes.

[0003] Japanese Utility Model Laid-Open No. 5-66755 discloses a DMA processing apparatus in which priorities can be changed in a programmable manner. Since the priority is determined by referring to the contents of the priority holding register, the priority can be changed without changing the circuit by rewriting the contents of the priority holding register. However, the priorities can be changed programmably.

[0004]

Since priorities are set in the priority holding register and arbitration is performed according to the priorities, for example, when a device having a high priority continuously issues a bus use request, A problem arises in that lower priority devices cannot use the bus. Of course, even if one high-priority device does not issue requests continuously, if a request is issued at a high frequency (short period), the probability that the bus use permission is given to the device of lower priority is drastically reduced. As a result, a state occurs in which the right to use does not substantially come around.

The first object of the present invention is to constantly secure a bus use opportunity for a lower-rank device,
The second is to provide a bus arbitration device that can be used for general purposes.
The third purpose is to automatically cancel an abnormal situation where the bus use is substantially continuously occupied by one device.
The purpose of.

[0006]

(1) The present invention provides a bus arbitration device (106) for arbitrating bus access request signals from a plurality of devices (101 to 104) to permit one device to use a bus. A mask setting means (101, 202) for setting a mask time (mask field) of the device (101 to 104);
When a device uses a predetermined bus (use once), means (PC1 to PC1) for starting timing of a mask time addressed to the device
PC4), and a change means (R7 to R10, A11
To A14). In addition, in order to facilitate understanding, in the parentheses, reference numerals or corresponding items of the corresponding elements of the embodiment shown in the drawings and described later are added for reference. The same applies to the following.

According to this, the priority order of the bus use is given to a device different from the device using the predetermined bus, so that it is possible to prevent only a device having a higher priority from monopolizing the bus use. As a result, a bus use opportunity is created for a lower-order device.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (2) The bus arbiter (106) includes priority setting means (101, 202) for setting priorities (priority fields) for devices; the changing means (R7 to R10,
A11-A14), when all devices (101-104) have started timing the mask time addressed to each,
Bus arbitration is performed in the priority order set by the order setting means (101, 202).

If all the devices that have issued the bus access request have been in the mask period, the bus use right is given to the devices in the order set by the order setting means (101, 202) regardless of the mask. The unreasonable situation that the bus is idle while there is a bus access request from the device is avoided. (3) A bus arbitration device (106) for arbitrating bus access request signals from a plurality of devices (101 to 104) and permitting one device to use the bus, for measuring the length of continuous use of the bus ( 203) and, when the measured length reaches a predetermined value, a special order setting means (20) for setting the priority of the bus access request of the specific device (101) to the highest order.
3, FF, A3, A31-A34, R3-R6).

According to this, for example, even when a device having a higher priority in using the bus runs away or breaks down and the bus is continuously used, for example, the device (101) for monitoring or controlling the device is specially provided. By giving the priority, the subsequent recovery work can be performed. (4) In a bus arbitration device (106) which arbitrates bus access request signals from a plurality of devices (101 to 104) and permits one device to use the bus, a mask time (mask filter) of the devices (101 to 104) Means for setting a mask (101, 202); means for starting time measurement of a mask time addressed to the device when the device uses a predetermined bus (use once) (PC1 to PC4); start the time measurement Changing means (R7-R10, A11-A14) for prioritizing a device for which similar timing has not been started than a device performing the same; means (203) for measuring the length of continuous use of the bus; and measuring When the length reaches the predetermined value, the special order setting means (2) sets the priority of the bus access request of the specific device (101) to the highest order.
03, FF, A3, A31 to A34, R3 to R6);

This is an embodiment provided with the technical means of the above-mentioned embodiments (1) and (3), and the above-mentioned functions and effects of the above-mentioned embodiments (1) and (3) can be obtained. (5) Bus arbitration device (106) has priority over devices
Order setting means (101, 202) for setting (priority field)
The change means (R7 to R10, A11 to A14), when all the devices (101 to 104) have started timing the mask time addressed to each, the order setting means (101, Two
Bus arbitration is performed according to the priority set in 02).

This is an embodiment provided with the technical means of the above (1), (2) and (3).
The above-described functions and effects of the embodiments (2) and (3) are obtained. (6) In the bus arbitration device (106) which arbitrates bus access request signals from a plurality of devices (101 to 104) and permits one device to use the bus, the priority (priority field) is determined. Setting means (202) for setting a mask period (mask field) of the bus access request signal (20).
A bus arbitration device characterized by including (2). According to this, the issue rate of the bus use permission addressed to each device can be limited, and it is possible to prevent a device having a high priority from monopolizing the bus. (7) In the bus arbitration device of (6), when all devices that have issued the bus access request fall within the mask period, the bus arbitration device set to a higher order is independent of the mask. Bus arbitration is performed with priority from. According to this, when all devices that have issued a bus access request fall within the mask period, the bus arbitration is performed in accordance with the priority order from the higher-order bus access request, regardless of the mask. Therefore, it is possible to prevent a situation in which the bus is idle while there is a bus access request. (8) The bus arbitrating device of (6) includes a counter (203) for measuring the number of cycles using the bus,
When the counter value reaches a predetermined value, a specific device (10
The bus access request of 1) is set to the highest priority. According to this, a counter for measuring the number of cycles using the bus is provided, and when the counter value reaches a predetermined value, the bus access request of the specific device (101) is given the highest priority. Therefore, even when a device with a higher priority has failed, the specific device (101) can perform a subsequent recovery operation.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The control circuit 106 shown in FIG. 1 is an embodiment of the bus arbitration device of the present invention. 101 is a CPU. 102 is a DMA controller 1, and 103 is a DMA controller 2. 10
Reference numeral 4 denotes a RAM, and 105 denotes a ROM. Control circuit 106
Are the device CPU 101 and the DMA controller 10
2, 103 and the RAM 104, receive access requests, appropriately arbitrate them, and grant bus use permission to only one device even when there are simultaneous access requests from a plurality of devices. In the following, the DMA controller 1 of 102 is represented as DMAC1, and the DMA controller 2 of 103 is represented as DMAC2.

FIG. 2 shows only the part of the arbitration device in the control circuit 106. 201 is a core part of the arbitration device,
This, the control register 202 and the counter 203 constitute an arbitration device. The control register 202 includes the CPU 1
01 is the data shown in FIG.
1, DMAC1, DMAC2 and RAM 104 are written. In the following, these devices are also referred to as request source 1, request source 2, request source 3, and request source 4, respectively.

As shown in FIG. 4, in the present embodiment, the highest priority after change (changed order in a shortened expression), priority, and mask period (mask in a shortened expression) for request sources 1 to 4 are shown. It is supposed to be set. Here, the highest priority after change refers to a request in which when the number of bus use cycles reaches a specific value, the priority is changed to the previous priority and the bit information “1” is set as the highest priority after change. This is to make the source the highest priority. No priority is given to the request source in which the bit information “0” is set as the highest priority after the change. This “0” means that the grant of the bus use permission is prohibited. In the present embodiment, “1” is set to the request source 1 (CPU), and even if a request source having a higher priority than the request source fails, the CPU 101 uses the bus to perform subsequent recovery. So that they can do their work.

In the priority field, a priority for each request source is set. In this example, it is represented by 2 bits, and 00 is the highest priority. In the setting example here, the first order (00 of 2 bits) is used for refreshing the RAM 104.
The second rank (01) is given to the DMAC1, the third rank (10) is given to the DMAC2, and the fourth rank is given to the CPU 101.

In the mask field, a mask period for each request source is set. If 0 is set here, there is no mask, and if any other value is set, the bus is permitted once, the bus is used, and then the request is masked for the number of cycles set here. However, if all requesters issuing bus access requests are within the mask period, regardless of the mask, bus arbitration is performed according to the priority order from the higher-order bus access request. I have. For this reason, it is possible to prevent a state in which the bus is idle while there is a bus access request.

Referring to FIG. 2 again, the arbitration device core unit 201 arbitrates while using the counter 203 while referring to the value set in the control register 202. The counter 203 is for measuring the number of cycles using the bus. This is, as mentioned above,
When the number of bus use cycles reaches a specific value, the priority is changed to the previous priority, and the request source 1 (CPU 101) in which “1” is set as the changed highest priority is set to the highest priority. Thus, even if the request sources 2 to 4 having a higher priority are out of order, the subsequent recovery work can be performed. The arbitration device core section 201 includes a DMAC
1, DMAC 2, CPU 101, bus use request signal from RAM 104 refresh (high level H DMA1R
EQ, DMA2REQ, CPUREQ, REFREQ)
Xx
Assert GNT. That is, the bus grant signal (high level DMA1GNT, DMA1
2GNT, CPUGNT, REFGNT). These permission signals are DMAC1,
DMAC 2, CPU 101, and RAM 104 are given to refresh. The BUSY input to the arbitration device core section 201 is a logical sum of signals asserted when the permitted request source uses the bus.

FIG. 5 shows a timing chart of this embodiment. CLK is a system lock, and BUSY is a logical sum of signals asserted when the request source permitted as described above uses the bus. DMA1REQ, DMA2
REQ is a bus use request signal from DMAC1 and DMAC2, and DMA1GNT and DMA2GNT are DMAC1 and D
Bus use permission signal for MAC2, DMA1MASK
Is a mask signal for DMAC1, and COUNT is a measurement result of the number of cycles using the bus. Here, in order to simplify the description, the CPU 101 and the RAM 1
04 refresh request has not been issued. At one point (timing) in FIG.
Q and DMA2REQ are asserted. Arbitration device 106
Detects this at two points 1 and 2. At this point, BUSY is asserted and the bus is in use, so no new bus use permission is issued.

It is detected that BUSY has been negated at the point 3 and the DMAC has a high priority and is not a mask period.
The bus use permission is issued by asserting DMA1GNT with respect to 1. Since 0001 0000 (decimal 16) is set in the mask field of DMAC1, DMA1MASK is asserted. mask·
If 0 (0000 0000) is set in the field, DMA1MASK is not asserted. At the point 4, DMAC1 detects that the permission has been granted, and
REQ is negated, and BUSY is asserted to indicate that the bus is being used. 5, the arbitration device 10
The count value of the counter 203 of 6 becomes 1, and the measurement of the number of bus use cycles is started. DMA at 6
C1 completes bus use and negates BUSY.

At the point 7, the arbitration device 106 performs new arbitration and issues a bus use permission to the DMAC2. This is because the priority of DMAC1 is higher,
Since AC1 is set so as to be masked for 16 cycles from the end of bus use, permission is issued to MAC2. If no bus use request has been issued other than DMAC1, DMA1
C1 is allowed. At point 8, the DMAC2 detects that it has been granted, negates DMA2REQ, and asserts BUSY to indicate that the bus is busy. At 9, the count value of the counter 203 of the arbitration device 106 becomes 1, and the measurement of the number of bus use cycles is started. At point 10, since 16 cycles have elapsed since the end of the DMAC bus use, DMA1MASK is negated.

The timing chart of FIG. 5 does not show an example in which the count value COUNT of the counter 203 exceeds a predetermined value. However, if such a case occurs, the priority after the change becomes the highest priority. Request source 1 (C
PU 101) is given the highest priority.

FIG. 3 shows an arbiter core part (ARB) 20.
1 shows one specific example. Register 202 contains a signal port No. for receiving bus use request signals from request sources 1-4.
Is written corresponding to the request source, and the read / write address No. of the data in the register 202 is written. 1 to 4 are determined in the order of priority. The count data of the counter C1 is stored in the register 2
02, the counter C1 sequentially counts up from 1 to 4, and the address No.
The data Nos. 1 to 4 (data loop consisting of priority order, signal port No., changed order and mask period) are sequentially output.

That is, the counter C1 is cleared when the system clock CLK is at a low level L, and can be counted when the system clock CLK rises from L to a high level H. When the system clock CLK rises from L to high level H, the mono-multi vibrator M11
A short H pulse of less than 1/8 of the pulse period of CLK is generated. At this time, if BUSY is L (the bus is vacant), the short H pulse is added to the counter C1 through the AND gate A1, and the counter C1 is output. C1 counts up and the count data becomes address No. 1 will be specified,
From the register 202, the address No. 1 is read out and the signal port No. therein is read out. 4 (request source 4) is given to the decoder D1, the changed rank "0" is given to the AND gate A3, and the mask period 0000 0000 is given to the preset data input terminals of the preset counters PC1 to PC4. Signal port No. 4 (requester 4)
The decoder D1 receives the gate control output lines of the first to fourth gate control output lines, that is, the gate control output lines to the AND gates A14 and A34. ) Is designated as H.

At this time, when there is a bus use request signal REFREQ = H for the request source 4 (RAM 104 refresh), the output of the AND gate A14 becomes H, and this H is passed through the OR gate R6. Enable signal REF
RAM 104 and AND gate A2 with GNT = H
4 and also through AND gate R2 to AND gates A21-214, and AND gate A2
4 generates an H output, and the counter PC4 outputs the mask period data of the preset data input terminal at the rising point of the H output.
0000 0000 is loaded. RAM 104
If BUSY = H (bus busy) for bus use in response to the bus use permission signal REFGNT = H, the AND gate A1 is constrained to be off and the output pulse of the mono-multi M11 falls to L. M12 is CLK
, The pulse width of which is less than 1/8 of the pulse period, this pulse is cut off by the AND gate A1, and the counter C1 does not count up. That is, the RAM 10
Until 4 finishes using the bus and BUSY returns to L, AND gate A1 remains off and counter C1 does not count up, so the data read address of register 202 cannot be advanced (to another device). The process does not proceed to the bus use permission process.)

When the RAM 104 finishes using the bus and the BUSY
Is returned to L, the mono-multi M2 generates one pulse H,
This is the counter PC1 to PC4 that has the downcounter
The counters PC1 to PC3 do not count because there is no preset value load (the same as the load of 0), and the counter PC4 loaded with the preset value is also loaded. Since the code value is 0 (0000 0000), the counting operation is not substantially performed, and the signal L indicating that counting is in progress is not generated. H indicating that it is not counting is
Since the gates R7 to R10 and the NAND gate A4 are added to each other, the gates R7 to R10 supply H indicating gate-on to the AND gates A11 to A14. CPUREQ = H, DM
A1REQ = H, DMA2REQ = H or REFREQ
= H), the corresponding bus use permission signal (C
PUGNT = H, DMA1GNT = H, DMA2GNT
= H or REFGNT = H).

If the mask section data addressed to the RAM 104 is 0001 0000 (decimal 16) and it has been loaded into the preset counter PC4, the RAM 104 finishes using the bus and returns to BUSY.
Is reset to L, CL of the preset counter PC4 is
When the K countdown starts, L indicating that counting is being performed is given to the OR gate R10.
14 is constrained to gate-off, and this continues for 16 pulses of the system clock CLK after BUSY returns to L. That is, in the case of this assumption, the RAM 1
04 has finished using the bus, the system clock CLK
Is generated, even if the RAM 104 generates the bus use request REFREQ = H, no bus use permission is given to this. During this non-permission, the gate-on signals are given to the AND gates A11 to A13 from the OR gates R7 to R9.
A bus use permission is given to U101, DMAC1 and DMAC2 when a bus use request is issued.

As described above, BUSY = L (bus free)
, The system clock CLK rises from L to H, the counter C1 counts up, and the register 202 1 is read out, the address No. 1 is read. 1 (priority 00: first) is addressed to the RAM 104 refresh by the bus use request signal REFR.
When EQ = H is not output (REFREQ =
In L), since the BUSY is not inverted to H (bus busy), the AND gate A1 continues the gate-on state, and the mono-multi M12 outputs one pulse in response to the fall of the output pulse of the mono-multi M11. When this occurs, the counter C1 counts it up, and the count data becomes 2,
The address No. of the register 202 2 (priority 01: second) is read out. At this time, the address No. When the DAMC1 addressed to No. 2 generates the bus use request signal DMA1REQ = H, the AND gate
The output of the gate A12 becomes H, and the bus use permission signal DMA1
GNT = H is provided to DAMC1.

When the bus use request signal DMA1REQ = H has not been generated, since BUSY does not reverse to H (bus busy), the AND gate A1 continues the gate-on state, and the output pulse of the mono-multi M12 is output. When the mono-multi M13 generates one pulse in response to the falling edge, the counter C1 counts it up, the count data becomes 3, and the address No.
3 (priority 10: third) is read out. At this time, the address No. DA addressed to 3
When the MC2 generates the bus use request signal DMA2REQ = H, the output of the AND gate A13 becomes H, and the bus use permission signal DMA2GNT = H is given to the DAMC2.

When the bus use request signal DMA2REQ = H has not been generated, since BUSY does not reverse to H (bus busy), the AND gate A1 continues the gate-on state, and the output pulse of the mono-multi M13 is output. When the mono-multi M14 generates one pulse in response to the falling edge, the counter C1 counts it up, the count data becomes 4, and the address No.
4 (priority 11: fourth) is read out. At this time, the address No. CPU1 addressed to 4
When 01 generates the bus use request signal CPUREQ = H, the output of the AND gate A11 becomes H, and the bus use permission signal CPUGNT = H is given to the CPU 101.

When the bus use request signal CPUREQ = H has not been generated, the system clock CLK goes low.
, The counter C1 is cleared, and the ARB 201 does not perform any special operation until the next clock CLK rises to H.

In the above, the bus use permission signal DMA1
GNT = H, DMA2GNT = H or CPUGNT
After the operation is given to the DMAC1, DMAC2 or the CPU 101, the bus use permission signal REFGNT = H is output to the RAM1.
This is the same as the above-mentioned operation after giving to the 04 refresh.

BUSY = L while no device generates a bus use request signal. During this time, every time the system clock CLK rises from L to H, (BUSY = L)
Every time one pulse is generated), and gates A14, A1
2, a gate on signal to A13 and A11 in this order,
The decoder D1 is sequentially provided, and scanning is performed to determine whether a bus use request signal has been generated from a device having a higher priority (RAM 104: AND gate A14) to a device having a lower priority. If a device in a scan in this priority order generates a bus use request signal, it gives a bus use permission to the device, and while the device keeps BUSY high for bus use, the scan is performed. Stop.

In the example shown in FIG. 3, the request source 4 (the RAM 10
4 refresh) is set to 0, and the request source 2
And 3 (DMACs 1 and 2) have a mask period of 16
(Decimal number), the mask period for the request source 1 (CPU 101) is set to 0, so that all devices are in the mask period, that is, the counter PC
A state in which all 1 to PC4 output L indicating that counting is in progress to the orgates R7 to R10 and the NAND gate A4 does not occur. However, the CPU 101 determines that the address No. In any one of 1 to 4, several cycles of CLK or several tens
Such a situation may occur when mask period data indicating a cycle is written. In such a situation, the output of the NAND gate A4 becomes H and H is applied to all of the gates R7 to R10, thereby instructing the gate signals to the AND gates A11 to A14 to turn on. As in the case where no device is in the masking period, scanning confirmation of whether or not each device has generated a bus use request signal in the order of priority described above is performed in the same manner. This avoids a situation in which a mask period may be set to all devices arbitrarily, and a situation in which all devices are in the mask period and no bus use permission is given to any device. .

By the way, if runaway or failure occurs, 1
Two devices continue to use the bus (BUSY = H)
Then, the scanning for checking the bus use request signal in the priority order described above remains stopped, so that the right to use the bus is not transferred to other devices. To avoid this, a preset counter 203 is used. When the bus is in use (BUSY = H), the AND gate A2 is on due to BUSY = H. Therefore, when BUSY was L first, the preset down counter 203 cleared by BUSY = H is changed to BUSY = H. While continuing, the system clock CLK is counted down from a preset value (predetermined value, predetermined cycle number).

When the count data indicates 0, that is, when the number of arrivals of CLK is counted by the preset value, the counter 203 generates a count over signal, whereby the flip-flop FF is set, and The Q output is inverted from L in the reset state to H in the set state, whereby the AND gates A11 to A14 are output.
Are turned off, and the output of AND gate A14 becomes H
To L. At this time, the Q output = H causes the AND gate A3 to output the changed order bit currently read from the register 202. Here, assuming that the counter 203 counts over while the bus is being used for refreshing the RAM 104, the address No. is stored in the AND gate A3. After the change of 1, the order bit “0” is set to register 2
02, the output of AND gate A3 returns to L, and therefore the outputs of AND gates A31 to A34 remain at L, so that the output of OR gate R6 returns from H to L. That is, the bus use permission signal R addressed to the RAM 104
EFGNT = H is canceled. BUSY = L
However, since the flip-flop FF is in the set state, the AND gates A11 to A14 are gated off.

When BUSY = L, AND gate A1
Is turned on, and the above-described scanning for checking the bus use request signal in the priority order is started. By this scanning, the address N at which the changed order bit “1” is written
o. 4 (request source 1: CPU 101) when scanning proceeds, that is, the de-tag loop of the address is stored in the register 2
When the data is read from the address 02, the output of the AND gate A3 becomes H. At this time, if the CPU 101 generates the bus use request signal CPUREQ = H, the AND gate A3
1 becomes H, and the outputs of the gates R3 and R2 become H.
And the bus use permission signal CPU addressed to the CPU 101
GNT = H occurs. That is, the CPU 101 is permitted to use the bus. In the case of the data setting on the register 202 shown in FIG. 3, only the CPU 101 has the bus use right "1". Therefore, while the flip-flop FF is set as described above, the bus is not used. Only the CPU 101 can be used.

The flip-flop FF receives a power-on reset signal and a system (only 106 or 101 to 10).
6) Reset by the reset signal. For example, C
When the bus use permission is not given for a predetermined time (preset value of the counter 203) after the bus use request signal is generated and the bus use permission is given after the predetermined time elapses (the changed priority bit “1”). ), The system error is notified, or the system is reset, so that when the counter 203 counts over, the system error is generated. Alternatively, the system is reset.

In the above example, the ARB 201 is a disc drive.
Logic circuit configuration, all or a part of which
Alternatively, the above function may be replaced with an operation function by a program of the CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a shared bus system incorporating one embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of an arbitrating device of the present invention in a control circuit 106 shown in FIG. 1;

3 is a core part (ARB) 2 of the arbitration device shown in FIG. 2;
FIG. 2 is a block diagram showing a specific example of the first embodiment.

FIG. 4 shows a control register 202 shown in FIG.
3 is a chart showing an example of data written by 1;

FIG. 5 is a timing chart showing a specific example of bus arbitration of ARB 201 shown in FIG.

[Explanation of symbols]

101: CPU 102: DMA controller 1 103: DMA controller 2 104: RAM 105: ROM 106: Control circuit 201: Core part of the arbitration device 202: Control register 203: Counter FF: Flip-flop M11 to M14, M2: Mono multivibration -Ta

Claims (3)

[Claims] In a bus arbitration apparatus for arbitrating bus access request signals from a plurality of devices and permitting one device to use a bus, mask setting means for setting a mask time of the device, wherein the device uses a predetermined bus usage A means for starting timing of a mask time addressed to the device, and a changing means for prioritizing a device that has not started timing similar to the device. Arbitration device. 2. The bus arbitration apparatus includes priority setting means for setting priorities for devices; said changing means includes means for setting a time when all devices have started timing their respective mask times. 2. The bus arbitration device according to claim 1, wherein bus arbitration is performed according to the priority set by said order setting means. 3. A bus arbitration device for arbitrating bus access request signals from a plurality of devices to permit one device to use a bus, means for measuring the length of continuous use of the bus, and the measured length When a certain value is reached, the bus
A bus arbitration device comprising: special order setting means for setting the priority of an access request to the highest order.