JP4174213B2 - Control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention controls a plurality of processing request sources and their processing requests to be sequentially processed in the order of processing requests. Control circuit It is about.
[0002]
[Prior art]
Digital circuits often include a plurality of processing request sources and an arbitration circuit that controls the processing requests so that the processing requests are sequentially processed in a certain order. For example, there are a plurality of DMA controllers (direct memory access controllers; hereinafter referred to as DMACs), which access memory via a CPU (central processing unit). An access request to a memory from a plurality of DMACs is selected by the arbitration circuit, and one access request is selected. When the access is completed, the next arbitration is entered.
[0003]
There are several methods for mediation. First, arbitration based on a fixed priority is a scheme in which a fixed priority is given to a processing request source and arbitration is performed based on the fixed priority, and the circuit configuration is simple. For example, there are four DMACs, that is, DMAC (0), DMAC (1), DMAC (2), and DMAC (3), and DMAC (0) has the highest priority, and DMAC (1) and DMAC (2) It is assumed that the priority order is sequentially decreased and the priority order that the DMAC (3) is the lowest is given.
[0004]
Then, when there is a memory access request from a plurality of DMACs, one having a higher priority is always selected. Accordingly, a request for a DMAC with a lower priority is not selected as long as there is a request for a DMAC with a higher priority.
[0005]
For this reason, arbitration with a fixed priority order is a system where there is no problem even if processing of a processing request source having a low priority level is held for a long time, or a system in which the number of requests from each processing request source is low and multiple simultaneous requests are extremely rare Adopted.
[0006]
On the other hand, the round robin method is often used in a system that does not allow a processing request source process to be held for a long time.
[0007]
In the round robin method, the priority order for the processing request source is dynamically changed. As in the example described above, as the initial priority, it is assumed that DMAC (0) has the highest priority, DMAC (1), DMAC (2) sequentially lower priority, and DMAC (3) has the lowest priority. Priority shall be given.
[0008]
Then, when there are memory access requests from a plurality of DMACs, the one with the higher priority at that time is selected. For example, if there is a memory access request from DMAC (1), the DMAC (2) having the second highest priority after DMAC (1) has the highest priority after the access is completed, and the priority of DMAC (1) is the highest. Arbitration is performed so that the lowest priority is obtained, that is, the priority order is changed to DMAC (2), DMAC (3), DMAC (0), and DMAC (1), and this is repeated.
[0009]
In this method, if a processing request source issues a request, the request is always processed regardless of the order in which the other processing request sources issue requests.
[0010]
Note that the round robin method is not processed in the order of processing requests. For example, when there is an access request from DMAC (0) and DMAC (3) first, the DMAC (0) access request is processed. If there are further requests from DMAC (1) and DMAC (2) during the processing, they will be processed in the order of DMAC (0), DMAC (1), DMAC (2), DMAC (3). The DMAC (3) access request generated at the end is processed last. As the number of processing request sources increases, the holding time of such processing requests increases.
[0011]
If such processing requests cannot be held, it is necessary to sequentially perform processing in the order of processing requests.
[0012]
FIG. 8 is a block diagram showing the configuration of a conventional digital circuit. In particular, access requests for four DMACs, DMAC (0), DMAC (1), DMAC (2), and DMAC (3), are sequentially processed in the order of processing requests. Corresponds to the case.
[0013]
As shown in the figure, 2 (0), 2 (1), 2 (2), and 2 (3) are DMAs having the same configuration, and DMAC (0), DMAC (1), DMAC (2), and DMAC, respectively. Corresponding to (3), the processing request signal req (n) of each of these DMAC (n) 2 (n) (hereinafter, n = 0, 1, 2, 3) is connected to the arbitration circuit 5, and the arbitration circuit 5 Outputs a selection signal sel (n) so as to be in the order of processing requests, and simultaneously outputs an access request signal req to the bus controller (Bus Controller) 1.
[0014]
In addition, 3 (0), 3 (1), 3 (2), and 3 (3) are AND circuits, and each of these AND circuits 3 (n) is each DMAC (n) 2 (n). The address signal of the address sel (n) is added to the addr (n) of the address signal (represented by the address signal for the sake of explanation, although other signals are actually required). Output. Note that the address signal addr (n) of the DMAC (n) 2 that is not selected is set to logic “0”.
[0015]
The logical sum circuit 4 calculates the logical sum of the address signal addr (n) input from each logical product circuit 3 (n), and addresses the address signal addr (n) of the selected DMAC (n) 2 (n). The signal addr is output to the bus controller 1.
[0016]
The bus controller 1 accesses a memory (not shown) based on the access request signal req from the arbitration circuit 5 and the address signal addr from the OR circuit 4, and when the access to the memory is completed, arbitrates the processing end signal done. Output to the circuit 5.
[0017]
When this processing end signal done is input, the arbitration circuit 5 outputs done (n) to the selected MAC (n) 2 (n), indicating that the memory access has been completed. ) Inform 2 (n).
[0018]
The arbitration circuit 5 includes a request queue 51 and an arbitration control circuit 52. A FIFO (first in first out) memory (not shown) exists in the request queue 51, and the request source identification number of the DMAC (n) 2 for which the access request is made is written. Here, the requester identification numbers of DMAC (0) 2 (0), DMAC (1) 2 (1), DMAC (2) 2 (2), and DMAC (3) 2 (3) are set to 0, 1, respectively. 2 and 3.
[0019]
9 and 10 are timing charts showing timings of main signals at the time of processing request processing in the conventional digital circuit shown in FIG. 8. In particular, there are access requests from DMAC (0) and DMAC (3). This corresponds to the operation when there is a further request from DMAC (1) and DMAC (2) during the processing of the DMAC (0) access request.
[0020]
As shown in the figure, the FIFO memory of the request queue 51 is empty in the initial state, the notempty signal is “Low”, and the arbitration control circuit 52 does not assert req. When access requests from DMAC (0) 2 (0) and DMAC (3) 2 (3), and req0 and req3 are asserted (clk1), the requester identification number of these DMACs is set to “0”. “3” is written (clk2).
[0021]
At the same time, the notempty signal becomes “High” (clk2). The arbitration control circuit 52 asserts req (clk3), and since FIFOout is “0”, sel0 is set to “High” (clk3). Therefore, A which DMAC (0) 2 (0) outputs to addr0 is output to addr.
[0022]
The bus controller 1 executes the access to the memory at the address A by asserting req, and when completed, asserts the processing end signal done (clk8). During this memory access, the DMAC (1) 2 (1) asserts req1 at the timing of clk6, and the DMAC (2) asserts req2 at the timing of clk8. The requester identification numbers “1” and “2” are further written.
[0023]
The arbitration circuit 5 asserts the done0 of DMAC (0) 2 (0), which is the access request source, by asserting the processing end signal done (clk9), and the DMAC (0) 2 (0) deasserts req0 (clk10). ).
[0024]
The arbitration circuit 5 removes one piece of data from the FIFO memory of the request queue 51 by asserting the processing end signal done, and refers to the notempty signal again. Since the notempty signal is “High”, it is known that there is a pending access request.
[0025]
The arbitration circuit 5 asserts req again, and since FIFOout is “3”, sel3 is set to “High” (clk10), and access request processing of DMAC (3) 2 (3) is started.
[0026]
Thereafter, similarly, as shown in the timing chart, access request processing of DMAC (1) 2 (1) and DMAC (2) 2 (2) is performed. When one data is removed from the FIFO memory of the request queue 51 by assertion (clk29) of the processing end signal done when the memory access to the access request of the DMAC (2) 2 (2) is completed, the FIFO memory is in an empty state. The notempty signal returns to “Low” (clk30). The arbitration circuit 5 waits for a new requester identification number to be written to the request queue 51.
[0027]
As described above, the conventional digital circuit shown in FIG. 8 has DMAC (0) 2 (0), DMAC (1) 2 (1), DMAC (2) 2 (2), DMAC (3) 2 (3 ) Four DMAC access requests can be sequentially processed in the order of processing requests.
[0028]
[Problems to be solved by the invention]
However, the conventional digital circuit shown in FIG. 8 requires the arbitration circuit 5 including the request queue 51 in order to process a plurality of DAMC requests in the requested order. There was a point.
[0029]
First, the request queue 51 includes a FIFO memory and its peripheral circuit, but the peripheral circuit is complicated. In particular, the control when there is a request from a plurality of DMAC (n) 2 (n) at the same time as the timing of clk2 in the timing chart is complicated. The conventional digital circuit shown in FIG. 8 has a problem that four simultaneous requests of DMAC (0) 2 (0) to DMAC (3) 2 (3) must be handled.
[0030]
Further, when the number of processing request sources (in the above-described conventional example, DMAC (n) 2 (n)) increases due to specification change or similar system redesign, the arbitration circuit 5 including the request queue 51 needs to be changed. There was a problem that redesign was not easy.
[0031]
The present invention has been made to solve the above-described problems. An object of the present invention is to allow a plurality of processing request sources to latch input request identification numbers when processing requests occur, and When the latched request identification number is equal to the current request identification number, a selection signal is output to start the processing, and the processing request identification number control unit The new request identification number to be given to the request is input as the request identification number of the first processing request source, the request identification number output is input as the next request identification number, and this is repeated at each processing request source connected in a row, and the last processing is performed. The new request identification number output is updated by the request source identification number output, and the processing request identification number control unit updates the current request identification number output based on the processing end notification to With a simple circuit configuration that does not include a complicated circuit, it is possible to process the processing requests from a plurality of processing request sources in the order requested, and even if the number of processing request sources is changed, Easy to design Control circuit Is to provide.
[0032]
[Means for Solving the Problems]
The present invention includes a plurality of processing request means, an execution means for executing processing based on processing requests from the plurality of processing request means, and a control means for controlling processing requests from the plurality of processing request means. And a control circuit for controlling the execution order of processing based on processing requests from the plurality of processing requesting means, wherein the plurality of processing requesting means and the control means are connected via signal lines. Rosary chain And an end signal receiving means for receiving from the execution means an end signal indicating that the processing based on the processing request has been executed by the execution means, and the reception means is the end. First identification number output means for updating a first identification number for identifying a processing request to be processed next by the execution means in response to receiving the signal, and outputting the first identification number to the plurality of processing request means; A second identification number output means for outputting a second identification number for identifying a new process request by the plurality of process request means to a first process request means downstream of the control means among the plurality of process request means; , Receiving the second identification number transferred by the plurality of processing request means after being output by the second identification number output means, and based on the received second identification number, the second identification number output means Updating means for updating the second identification number to be transmitted by And the first processing request means receives the second identification number output from the second identification number output means; When the processing request is generated by the first processing request means First latching means for latching the second identification number received by the first receiving means; and the first receiving means received by the first receiving means when the processing request is generated by the first processing requesting means. 2 When the identification number is updated and transferred to the second process request means subsequent to the first process request means among the plurality of process request means, and no process request is generated in the first process request means Is a first transfer means for transferring the second identification number received by the first receiving means to the second processing request means without updating, and the first identification output by the first identification number output means. Second receiving means for receiving a number; When the processing request is generated by the first processing request unit, Selection for causing the execution means to execute processing based on the processing request when the second identification number latched by the first latch means matches the first identification number received by the second receiving means. First selection signal output means for outputting a signal, wherein the second processing request means is a third receiving means for receiving the second identification number transferred from the first transfer means, When the processing request is generated by the second processing request means Second latch means for latching the second identification number received by the third receiving means; and the second receiving means received by the third receiving means when the processing request is generated by the second processing request means. 2 When the identification number is updated and transferred to the third process request means subsequent to the second process request means among the plurality of process request means, and no process request is generated in the second process request means Is a second transfer means for transferring to the third processing request means without updating the second identification number received by the third receiving means, and the first identification output by the first identification number output means. A fourth receiving means for receiving a number; When the processing request is generated by the second processing request unit, Selection for causing the execution means to execute processing based on the processing request when the second identification number latched by the second latch means matches the first identification number received by the fourth receiving means And a second selection signal output means for outputting a signal.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The present invention will be described below with reference to the drawings.
[0038]
FIG. 1 is a block diagram showing a schematic configuration of a digital circuit showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a detailed configuration of a processing request identification number control unit 6 shown in FIG. FIG. 3 is a block diagram showing a detailed configuration of DMAC (0) 102 (0) to DMAC (3) 102 (3) shown in FIG. 1, which is the same as the conventional digital circuit shown in FIG. The same reference numerals are given.
[0039]
In the conventional digital circuit shown in FIG. 8, the processing request source processing request is managed by the processing request source identification number for the processing request source as described above, but in this embodiment, the processing request source processing is performed. Regardless of the processing request source, a request is assigned a processing request identification number to the processing request and is managed by the processing request identification number. The processing request identification number must be able to distinguish between the maximum number of processing requests generated at the same time or more.
[0040]
Further, the order of processing request identification numbers must be determined. Next to the last processing request identification number is the first processing request identification number. In FIG. 1, since the maximum number of processing requests that can be generated simultaneously is 4, the processing request identification numbers are 0, 1, 2, 3, and the order is 0 → 1 → 2 → 3 → 0 →.
[0041]
The configuration and operation of the digital circuit of the present invention will be described below with reference to FIGS.
[0042]
In FIG. 1, the cur_reqID signal represents the current processing request identification number, and this current processing request identification number is the processing request identification number of the processing request to be processed next.
[0043]
The new_reqID signal represents a new process request identification number, and this new process request identification number is a process request identification number assigned to a process request to be generated next. The current process request identification number and the new process request identification number are initialized to the first process request identification number, and both change in a predetermined order.
[0044]
The cur_reqID signal and the new_reqID signal are controlled by the processing request identification number control unit 6.
[0045]
The processing request identification number control unit 6 has a very simple configuration as shown in FIG.
[0046]
As shown in FIG. 2, when the processing end signal done input is asserted in the processing request identification number control unit 6, the selector 62 is advanced to the next number by a processing request identification number incrementer (request ID Incrementer) 61. The selected processing request identification number is selected and output to the flip-flop (FF) 63. The flip-flop (FF) 63 updates and outputs this processing request number as a cur_reqID signal indicating the current processing request identification number.
[0047]
The new_reqID signal indicating the current process request identification number is output from new_reqID_out of the process request identification number control unit 6 and returns to the new_reqID_in of the process request identification number control unit 6 via each DMAC (n) 102 (n). As described above, it is updated with new_reqID_in for each clock (clk) by the flip-flop 64 of the processing request identification number control unit 6.
[0048]
DMAC (0) 102 (0) to DMAC (3) 102 (3) are DMACs having the same configuration. As shown in FIG. 3, the DMAC (n) 102 (n) is a processing request identification number when an access request req (n) is generated in addition to the conventional DMAC (n) 2 (n) shown in FIG. A processing request identification number latch unit (request ID Latch) 21 for latching (reqID), a processing request identification number incrementer (request ID incrementer) 22 for advancing the processing request identification number (requestID) to the next number, and processing 1 when the matching circuit 23, selector 24, AND circuits 25, 27, and req for comparing the processing request identification number req_ID latched by the request identification number latch unit 21 with the current processing request identification number cur_req are started to assert. A pulse generation circuit (pulse gen. 26 is additionally configurations.
[0049]
When an access request occurs, the DMAC (n) 102 (n) asserts the req (n) signal, and the new_reqID signal (in the case of DMAC (0) 102 (0)) input to reqID_in (n) Latch the processing request identification number of the reqID_out (n-1) signal of DMAC (n-1) 102 (n-1) (in the case other than DMAC (0) 102 (0)) in the processing request identification number latch unit 21; At the same time, the selector 24 selects and outputs the processing request identification number next to the processing request identification number of reqID_in (n) incremented by the processing request identification number incrementer 22 as reqID_out (n).
[0050]
Thus, even when access requests are simultaneously generated for a plurality of DMACs, different processing request identification numbers are assigned to these requests. Of course, the DMAC (n) 102 (n) has the same processing request identification number as reqID_in (n) for reqID_out (n) except when an access request is generated, that is, when the output of the pulse generation circuit 26 is “Low”. Output. This switching is realized by the selector 24. The processing request identification number latched in the processing request identification number latch unit 21 is the processing request identification number assigned to the access request at that time.
[0051]
The DMAC (n) 102 (n) has a processing request number assigned to the request (processing request identification number latched in the processing request identification number latch unit 21) and the processing request identification number control unit 6 during the access request. When the current processing request identification number cur_reqID to be output matches, the matching circuit 23 and the logical product circuit 25 set sel (n) to “High”.
[0052]
That is, when the next access request to be processed is its own access request, sel (n) becomes “High”. The AND circuit 25 is for keeping sel (n) “Low” when an access request is not being made.
[0053]
In addition, the bus controller 1 takes the logical sum of the sel (n) logical sum circuits 104 of each DMAC (n) 102 (n) as an input of req, and outputs it from the logical sum circuit 4 when req is asserted. Based on the addr, access to a memory (not shown) is started, and when the access to the memory is completed, a processing end signal done is asserted. This processing end signal done is sent to all the DMACs 102.
[0054]
Then, each DMAC (n) 102 (n) uses the logical product circuit 27 to set the logical product output by the logical product circuit 27 of the processing end signal done and its own sel (n) to done (n), and done (n) ) Is asserted, it knows that its own access request has been processed and deasserts req (n).
[0055]
FIGS. 4 and 5 are timing charts showing timings of main signals at the time of processing request processing in the digital circuit showing the first embodiment of the present invention shown in FIGS. 1 to 3, and in particular, DMAC (0) 102. There are access requests from (0) and DMAC (3) 102 (3), and further requests from DMAC (1) 102 (1) and DMAC (2) 102 (2) during the access request processing of DMAC (0). This corresponds to the operation in the present embodiment for the case (that is, the same case as shown in FIGS. 9 and 10).
[0056]
First, the cur_reqID signal and new_reqID signal indicating the current process request identification number and the new process request identification number are initialized to “0” which is the first process request identification number.
[0057]
When access requests from DMAC (0) 102 (0) and DMAC (3) 102 (3) and req0 and req3 are asserted (clk1), the processing request identification number is stored in each internal processing request identification number latch unit 21. ReqID_in (0) signal “0” and reqID_in (3) signal “1” indicating “1” are latched (clk2). At the same time, the new_reqID signal indicating the new process request identification signal is updated to “2” (clk2).
[0058]
In DMAC (0) 102 (0), the cur_reqID signal indicating the current processing request identification number is “0”, which is equal to the processing request identification number “0” latched by itself, so sel0 is set to “High” (clk2). Therefore, A output from DMAC (0) 102 (0) to addr0 is output to addr.
[0059]
Since the access request signal req is asserted when sel0 becomes “High”, the bus controller 1 executes the access to the memory at the address A and, when completed, asserts the processing end signal done (clk7).
[0060]
During this memory access, at the timing of clk6, DMAC (1) 102 (1) asserts req1, latches the processing request identification number “2”, and updates the reqID signal indicating the processing request identification number to “3”. Is done.
[0061]
Further, at the timing of clk8, DMAC (2) 102 (2) asserts req2, latches the processing request identification number “3”, and the reqID_out (2) signal indicating the processing request identification number is updated to “0”. .
[0062]
The DMAC (0) 102 (0) deasserts req0 (clk8) because its selection signal sel0 is “High” and the processing end signal done is asserted (clk7).
[0063]
The processing request identification number control unit 6 updates the cur_reqID signal indicating the current processing request identification number to “1” by asserting the processing end signal done (clk8). When the cur_reqID signal is updated to “1”, the processing request identification number “1” latched by the DMAC (3) 102 (3) becomes equal to the cur_reqID signal “1” indicating the current processing request identification number. (3) 102 (3) sets sel3 to “High” (clk8). Again, req is asserted, and the bus controller 1 starts processing the access request for DMAC (3) 102 (3).
[0064]
Thereafter, similarly, as shown in the timing chart, access request processing of DMAC (1) 102 (1) and DMAC (2) 102 (2) is performed.
[0065]
With the above configuration, processing requests from a plurality of processing request sources (DMAC) can be sequentially processed in the order of processing requests without providing a complicated circuit including a request queue (for example, the arbitration circuit 5 shown in FIG. 8). It becomes possible. Therefore, the circuit configuration is simpler than before, and redesign can be easily performed even when the number of processing request sources is changed.
[0066]
[Second Embodiment]
FIG. 6 is a block diagram showing a schematic configuration of a digital circuit showing a second embodiment of the present invention, and FIG. 7 shows DMAC (0) 202 (0) to DMAC (3) 202 (3) shown in FIG. FIG. 4 is a block diagram showing the detailed configuration of FIG. 1, and the same components as those in FIG. 1 and FIG.
[0067]
As shown in FIGS. 6 and 7, the DMAC (n) 202 (n) is a signal req (n) used only inside the DMAC 102 of the first embodiment of the present invention shown in FIG. Is output to the outside.
[0068]
In the first embodiment, the logical sum signal of the selection signal sel (n) of each DMAC (n) 102 (n) is generated by the logical sum circuit 4 and used as the req signal of the bus controller 1. With this configuration, at the timing when the req signal of the bus controller 1 is asserted, the memory address to be accessed also for the input signal addr of the bus controller 1 is determined.
[0069]
When the path controller 1 accesses the memory, normally, in order to obtain the right to use the bus, first, a bus request signal is asserted, and a bus grant signal indicating permission to use the bus is asserted. Wait for the memory access to begin. No memory address is required between the assertion of the bus request signal and the assertion of the bus grant signal.
[0070]
In such a case, as shown in FIG. 6, the logical sum circuit 4 generates a logical sum signal of the access request signal req (n) instead of the selection signal sel (n) of each DMAC (n) 202 (n), Even if the req signal of the bus controller 1 is used, the determination of the addr signal is delayed by one clock with respect to the assertion of the req signal, but the bus controller 1 operates normally.
[0071]
Therefore, in the configuration of the present embodiment, the start of memory access in the bus controller 1 can be accelerated compared to the configuration shown in the first embodiment.
[0072]
In the first embodiment, the process request identification number is normally counted up as 0, 1, 2, 3 (0 → 1 → 2 → 3 → 0 →...). The number is not limited to this, and the processing request identification number to be used depends on the configuration of the processing request identification number incrementer 22 in the DMAC 102 (202) and the processing request identification number incrementer 61 in the processing request identification number control unit 6. .
[0073]
For example, when a Johnson counter having a simpler circuit configuration than a normal counter is used, the processing request identification number is 00B → 01B → 11B → 10B → 00B →... (B indicates that the previous number is a binary number display. ). Further, if a ring counter having a simple circuit configuration is used, 0001B → 0010B → 0100B → 1000B → 0001B →.
[0074]
In each of the above embodiments, the number of processing request identification numbers is four for four processing request sources (DMACs). However, the number of processing request numbers is limited to four if the number is four or more. There is no. For example, the processing request identification number may be set as 0 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0 →.
[0075]
Further, as will be described later, when eight process request identification numbers are used for four process request sources, the number of process request sources is limited to eight when changing or redesigning to increase the process request sources. If so, it will be very easy.
[0076]
Hereinafter, a change that increases the number of processing request sources (DMAC) will be described.
[0077]
When the number of processing request sources (DMAC) increases and the number of processing request identification numbers used so far becomes insufficient, the processing request identification number incrementer 22 and the processing request identification number in the DMAC 102 (202) are used. It is necessary to change the processing request identification number incrementer 61 in the control unit 6.
[0078]
When the number of bits required by the new processing request identification number exceeds the number of bits of the processing request identification number used so far, the latch circuit 21, selector 24, matching circuit 23 and logical product in the DMAC 102 (202) The circuits 25 and 27, the flip-flops (FF) 63 and 64 in the processing request identification number control unit 6, and the selector 62 must be matched to the number of bits. Finally, the number of inputs to the OR circuit 104 is adjusted to the number of processing request sources that have increased. In this way, all changes can only be made mechanically.
[0079]
Furthermore, if the increased number of processing request sources does not exceed the number of processing request identification numbers used so far, the number of inputs of the OR circuit 4 is simply adjusted to the increased number of processing request sources. It is only changed as follows.
[0080]
As described above, according to the present invention, processing requests from a plurality of processing request sources can be processed without using a complicated circuit (for example, the arbitration circuit 5 shown in FIG. 8) including a request queue that has been necessary in the past. Since sequential processing can be realized sequentially, it can be made small with a simple configuration. In addition, redesign can be easily performed even when the number of processing request sources is changed.
[0081]
The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device.
[0082]
In the above-described embodiment, the case where the present invention is applied to a digital circuit that executes memory access processing based on memory access processing requests from a plurality of processing request sources has been described. Any digital circuit that controls the original and their processing requests so as to sequentially process them in the order of processing requests can be applied to a circuit that performs processing other than memory access processing.
[0083]
【The invention's effect】
As described above, according to the present invention, processing requests from a plurality of processing request sources can be sequentially processed in the order of processing requests by using a simple circuit configuration without using a complicated circuit including a request queue. In addition, there is an effect that redesign can be easily performed even when the number of processing request sources is changed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a digital circuit showing a first embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of a processing request identification number control unit shown in FIG.
3 is a block diagram showing a detailed configuration of DMAC (0) to DMAC (3) shown in FIG. 1. FIG.
4 is a timing chart showing the timing of a main signal during processing request processing in the digital circuit showing the first embodiment of the present invention shown in FIGS. 1 to 3; FIG.
FIG. 5 is a timing chart showing the timing of a main signal at the time of processing request processing in the digital circuit showing the first embodiment of the present invention shown in FIGS. 1 to 3;
FIG. 6 is a block diagram showing a schematic configuration of a digital circuit showing a second embodiment of the present invention.
7 is a block diagram showing a detailed configuration of DMAC (0) to DMAC (3) shown in FIG. 6;
FIG. 8 is a block diagram showing a configuration of a conventional digital circuit.
9 is a timing chart showing the timing of a main signal at the time of processing request processing in the conventional digital circuit shown in FIG.
10 is a timing chart showing the timing of the main signal at the time of processing request processing in the conventional digital circuit shown in FIG. 8. FIG.
[Explanation of symbols]
1 Bus controller (Bus Controller)
3 (0) -3 (3) AND circuit
6 Process Request Identification Number Control Unit (Request ID Controller)
21 Processing request identification number latch part (request ID Latch)
22 Process Request Identification Number Incrementer (request ID Incrementer)
23 Matching circuit
24 selector
25 AND circuit
26 Pulse generation circuit
27 AND circuit
61 Process Request Identification Number Incrementer (request ID Incrementer)
62 Selector
63 Flip-flop (FF)
64 Flip-flop (FF)
102 (0) to 102 (3) DMA controller (DMAC)
104 OR circuit
202 (0) to 202 (3) DMA controller (DMAC)

Claims (4)

A plurality of processing request means;
Execution means for executing processing based on processing requests from the plurality of processing request means;
A control circuit for controlling processing requests from the plurality of processing requesting units, and for controlling a processing execution order based on the processing requests from the plurality of processing requesting units,
The plurality of processing request means and the control means are connected in a daisy chain via a signal line,
The control means includes
An end signal receiving means for receiving, from the execution means, an end signal indicating that the processing based on the processing request has been executed by the execution means;
In response to receipt of the end signal by the receiving means, a first identification number for updating a first identification number for identifying a processing request to be processed next by the execution means and outputting the first identification number to the plurality of processing request means. Number output means;
A second identification number output means for outputting a second identification number for identifying a new process request by the plurality of process request means to a first process request means downstream of the control means among the plurality of process request means; ,
The second identification number output means receives the second identification number transferred by the plurality of processing request means after being output by the second identification number output means, and the second identification number output means is based on the received second identification number. Updating means for updating the second identification number to be transmitted ,
The first process request means includes
First receiving means for receiving the second identification number output from the second identification number output means;
First latch means for latching the second identification number received by the first receiving means when the processing request is generated by the first processing request means ;
When the processing request is generated by the first processing requesting unit, the second identification number received by the first receiving unit is updated, and a subsequent stage of the first processing requesting unit among the plurality of processing requesting units. To the second processing request means, and when the processing request is not generated by the first processing request means, the second identification number received by the first receiving means is updated without updating the second identification number. First transfer means for transferring to the processing request means;
Second receiving means for receiving the first identification number output by the first identification number output means;
In the case where the processing request by the first processing request unit occurs, when the first identification number said the latched second identification number the second receiving means has received matches by the first latch means And a first selection signal output means for outputting a selection signal for causing the execution means to execute processing based on the processing request.
The second processing request means includes
Third receiving means for receiving the second identification number transferred from the first transferring means;
Second latch means for latching the second identification number received by the third receiving means when the processing request is generated by the second processing request means ;
When the second processing request means generates the processing request, the second identification number received by the third receiving means is updated, and the second processing request means subsequent to the second processing request means. To the third processing request means, and when the second processing request means does not generate a processing request, the third identification number received by the third receiving means is updated without updating the third identification number. Second transfer means for transferring to the processing request means;
Fourth receiving means for receiving the first identification number output by the first identification number output means;
When the processing request is generated by the second processing request unit, the second identification number latched by the second latch unit matches the first identification number received by the fourth receiving unit. And a second selection signal output means for outputting a selection signal for causing the execution means to execute processing based on the processing request.   2. The control circuit according to claim 1, wherein the execution unit starts processing based on a selection signal output from the first selection signal output unit or the second selection signal output unit.   The control circuit according to claim 1, wherein the control unit initializes the first identification number and the second identification number to the same value.   The control circuit according to claim 1, wherein the execution unit executes a memory access process based on processing requests from the plurality of processing request units.

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