JP4549458B2 - DMA transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DMA (Direct Memory Access) transfer apparatus, and more specifically, a DMA having a DMA control unit that performs DMA transfer control for directly transferring data between a memory and an external request device independently of the operation of a CPU. The present invention relates to a transfer device.
[0002]
[Prior art]
In the DMA transfer, data is directly transferred between peripheral devices such as a main memory and an I / O device (for example, an external request device) without using a CPU. This enables high-speed and large-capacity data transfer without CPU overhead. In general, the DMA transfer is controlled by a direct memory access controller (DMAC) managing the bus.
[0003]
Conventionally, in a system that performs DMA transfer between a DMAC and an external request device, the DMAC receives a DMA request (DREQ) signal output from the external request device so that data can be transferred between the memory device and the external request device. Control other devices.
[0004]
FIG. 32 is a block diagram showing the configuration of a conventional DMA transfer apparatus, taking as an example data transfer between a DMAC and an external request device.
[0005]
In FIG. 32, 1 is a CPU, 2 is a DMAC, 3 and 4 are a plurality of (two) external request devices (external request devices 1 and 2), and 5 is an external memory.
[0006]
Request signals DREQ1 / DREQ2 are output from the external request devices 3 and 4 to the DMAC2. Each DMA request signal DREQ1 / DREQ2 is input to the DMAC 2. The DMAC 2 outputs a bus request (BREQ) signal to the CPU 1 in response to the input of the DREQ signal, and requests the bus to be released.
[0007]
Upon receiving the BREQ, the CPU 1 outputs a bus release permission (BACK) signal, and opens the bus to the DMAC 2. Here, when there are a plurality of external request devices, the number of occurrences of DREQ from each device increases, so the order in which the BREQ signal is generated within the DMAC is adjusted (arbitration), and the DMA transfer of each external request device Is realized.
[0008]
[Problems to be solved by the invention]
However, such a conventional DMA transfer apparatus requires arbitration of the DREQ signal when mounted in a plurality of external request device systems as described above. In addition, the bus occupation rate by the DMA increases depending on the number of external request devices and the DREQ signal generation cycle of the external request device, and there is a possibility that processing by a normal series of CPUs may be extremely prolonged. was there.
[0009]
Hereinafter, this defect will be described.
[0010]
FIG. 33 is a timing chart conceptually showing the timing of DMAC arbitration.
[0011]
In a DMAC having three channels, the time required for one DMA transfer of each CH is T. In the case of FIG. 33, the DMAC arbitrates the DMA of each channel, and uses the channel in a round robin system such as CH1 → CH2 → CH3 → CH1. However, when this method is used, the bus is occupied only for DMA transfer, and the time that the processor is processing using the bus may be extremely extended in time.
[0012]
In the present invention, when there are a plurality of external request devices, or when external request devices having a short DREQ signal generation period exist on the same bus, the bus occupancy rate by DMA is reduced and the bus is made effective in time. An object of the present invention is to provide a DMA transfer apparatus that can be used.
[0014]
[Means for Solving the Problems]
  The DMA transfer apparatus according to the present inventionA CPU, an external memory, a plurality of external request devices each generating a data transfer request signal,Independent of CPU operation,OutsideMemory andThe plurality ofExternal request deviceBetweenDMA transferThecontrolDoDMA controllerA bus connecting the CPU, the external memory, the plurality of external request devices, and the DMA control unit;With
  The DMA control unit,in frontRecordpluralExternal request deviceAny ofData transfer request signalTheWhen it occursIn, Request a bus release by outputting a bus release request signal to the CPU, and when a bus release permission signal is returned from the CPU,The data transfer request signal was generatedSend a data transfer request confirmation signal to the external request deviceTheThe aboveOutsideMemory andThe data transfer request signal was generatedExternal request deviceWithDMA transfer betweenThecontrolBefore andBus request signal by masking the data transfer request signal so as to control the bus occupation state by DMA transferGenerateA mask circuit and a counter for counting a mask time for masking the data transfer request signal.And provided for each of the plurality of external request devicesMask means;in frontThe mask circuit of the mask meansOne ofByGenerationBased on the received bus request signal,The means for controlling the DMA transfer to the CPUBus release request signalAdjust the output of theMediation means to mediate andHave
  The CPU includes means for controlling the mask time according to the number of external request devices that can be operated simultaneously, and task management means for managing a processing load of a task processed by the CPU itself,
The task management means is monitored by the monitoring means for holding information on the mask time set for each task processed by the CPU, a monitoring means for monitoring a task currently processed by the CPU, and the monitoring means. Selection means for selecting the mask time from means for holding information on the mask time according to the task being set, and setting means for setting the selected mask time as a mask time used by the mask circuit. HaveIt is characterized by that.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a block diagram showing the configuration of the DMA transfer apparatus according to the first embodiment of the present invention. The present embodiment is applied to a system that performs DMA transfer between an external memory and an external request device.
[0022]
In FIG. 1, the DMA transfer apparatus includes a CPU 100, a DMAC 110 (DMA control unit), an external request device 111, an external request device 112, and an external memory 113.
[0023]
The DMAC 110 is equipped with two DMA channels, which are CH0 and CH1. Further, CH0 and CH1 are connected to the external request device 111 and the external request device 112, respectively.
[0024]
A DREQ signal mask circuit 121 (mask means) is installed inside the external request device 111, and a DREQ signal mask circuit 122 (mask means) is installed inside the external request device 112, and the DREQ signal mask circuits 121 and 122 are installed. Is controlled by mask signals mask_en0 and mask_en1 from the CPU 100.
[0025]
The mask signals mask_en0 and mask_en1 are signals for controlling enable / disable of the DREQ signal mask circuits 121 and 122, and both signals are active “H” (active signals at “H” level).
[0026]
Also, a BREQ (bus opening request) signal is output from the DMAC 110 to the CPU 100, and a BACK (bus opening permission) signal is output from the CPU 100 to the DMAC 110.
[0027]
The external memory 113 serves as a DMA transfer destination (transfer destination) or source (transfer source).
[0028]
2 and 3 are circuit diagrams showing configurations of the DREQ signal mask circuits 121 and 122. FIG. 2 shows a circuit configuration when the DREQ signal is active “H”, and FIG. 3 shows that the DREQ signal is active “L”. Each of the circuit configurations in the case of (a signal active at “L” level) is shown.
[0029]
In FIG. 2, the DREQ signal mask circuits 121 and 122 when the DREQ signal is active “H” are configured by an AND gate 131. The DREQ signal inside the external request device is DREQ_P_in (in the case of active “H”), and the mask signal for controlling the mask is mask_en.
[0030]
The AND gate 131 takes the AND logic of the inverted signal of the mask signal mask_en and the DREQ_P_in signal and outputs DREQ_P. In this case, the DREQ_P_in signal is masked when mask_en = “H”, and DREQ_P is output as an output.
[0031]
Similarly, in FIG. 3, the DREQ signal mask circuits 121 and 122 when the DREQ signal is active “L” are configured by an OR gate 132.
[0032]
The OR gate 132 takes the OR logic of the mask signal mask_en and the DREQ_N_in signal and outputs DREQ_N. In this case, when mask_en = “H”, the DREQ_N_in signal is masked, and DREQ_N is output as an output.
[0033]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0034]
Here, a case will be described in which the DREQ signal mask circuit 121 of CH0 is enabled by mask_en0 and the DREQ signal mask circuit 122 of CH1 is enabled by mask_en1.
[0035]
FIG. 4 is a timing chart showing the DMA transfer operation of the DMA transfer apparatus. One DMA transfer is performed at time T (for example, 500 ns). In the figure, CH0 and CH1 indicate two DMA channels of the DMAC 110.
[0036]
As shown in FIG. 4, it is assumed that DREGs of CH0 / CH1 are generated at the same time in the interval of T1.
[0037]
In the period T2, the CH0 DREQ0 signal is masked by the mask_en0 signal, and therefore the CH1 DMA transfer is performed. At that time, the mask_en1 signal is in a disabled state (“L”).
[0038]
Next, in the period T3, since both DMA channels are masked, DMA transfer is not performed. In this section, the CPU 100 occupies the bus and performs processing according to the program.
[0039]
Next, in period T4, mask_en1 is enabled ("H"), so the DREQ1 signal of CH1 is masked and DREQ1 is not output, so no DMA sequence is performed. In this section, the DMA transfer of CH0 is performed.
[0040]
Next, in the T5 section, the processing of the CPU 100 is performed as in the T3 section. Therefore, the processing of the CPU 100 is not stopped here either.
[0041]
In this way, mask_en0 and mask_en1 are used to mask the DREQ signal and change the generation period of the DREQ0 / DREQ1 signal.
[0042]
Further, mask_en0 / mask_en1 is controlled by the CPU 100, but such a periodic enable signal can be realized using a built-in timer of the CPU 100. For example, if the mask_en0 / mask_en1 are set to be alternately enabled in the interrupt process of 500 ns, a DREQ occurs once every 2 μs in the DMA of each CH. Furthermore, when the setting interval is shortened, it can be realized not by setting from the CPU 100 but by incorporating a timer for periodically controlling the enable inside the external request device.
[0043]
As described above, the DMA transfer apparatus according to the first embodiment includes the CPU 100, the DMAC 110, the external request device 111, the external request device 112, and the external memory 113, and the external request devices 111 and 112 receive the DREQ signal. Since the DREQ signal mask circuits 121 and 122 for masking are provided, and the DREQ signal mask circuits 121 and 122 are configured to mask the DREQ0 / DREQ1 signals and control the bus occupation state by DMA transfer, the mask_en0 / mask_en1 signal from the CPU 100 (Active “H”) causes the DREQ signal mask circuits 121 and 122 to mask the DREQ0 / DREQ1 signals, thereby periodically generating the DREQ signal, thereby increasing the system bus occupation rate by the DMA. Gosuru can. As a result, it is possible to prevent the DMA from occupying the bus so that CPU processing cannot be performed, and there is an effect of preventing failure due to the intervention of the DMAC of the system.
[0044]
Further, since there is no change in the configuration on the DMAC side, it is possible to improve the throughput and reliability of the entire system without changing the existing CPU system. Moreover, since it can be realized by adding a simple part called a gate circuit, it can be implemented at low cost.
[0045]
In the present embodiment, the DREQ signal mask circuits 121 and 122 for masking the DREQ0 / DREQ1 signals are provided inside the external request devices 111 and 112. These mask circuits 121 and 122 are provided on the external request device side. It does not necessarily have to be installed in the external request device.
Second embodiment
FIG. 5 is a block diagram showing a configuration of a DMA transfer apparatus according to the second embodiment of the present invention. The present embodiment is an example applied to a system that performs DMA transfer between an external memory device and an external request device using DMAC. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0046]
In FIG. 5, the DMA transfer apparatus includes a CPU 100, a DMAC 200, an external request device 240, an external request device 241, and an external memory 113.
[0047]
The DMAC 200 has two DMA channels, which are CH0 and CH1. CH0 and CH1 are connected to an external request device 240 and an external request device 241, respectively.
[0048]
The DMAC 200 is installed for each channel and is controlled by mask signals mask_en0 and mask_en1 from the CPU 100, and an arbitration circuit 230 that arbitrates the BREQ0 and BREQ1 signals of the DREQ signal mask circuits 210 and 220. With.
[0049]
The mask signals mask_en0 and mask_en1 are signals for switching enable / disable of the DREQ signal mask circuits 210 and 220 of CH0 and CH1, and both signals are active “H”.
[0050]
Note that the mask_en signal in the first embodiment means the mask signal itself, but the mask_en signal described in each embodiment to be described later including this embodiment controls whether or not to operate the mask circuit. Signal. Therefore, the mask_en signal can be omitted when the mask circuit is always operated.
[0051]
The CPU 100 outputs the mask signals mask_en0 and mask_en1 to the DREQ signal mask circuits 210 and 220 to control the DREQ signal mask circuits 210 and 220. The CPU 100 can set a timer count value for the DREQ signal mask circuits 210 and 220, and the length of the generated mask signal changes depending on the timer count value set by the CPU 100.
[0052]
The DREQ signal output from the external request device 240 to the DMAC 200 is DREQ0, the DREQ signal output from the external request device 241 to the DMAC 200 is DREQ1, and the DREQ signals returned from the DMAC 200 to the external request devices 240 and 241 are DACK0 and DACK1, respectively. And
[0053]
Also, the BREQN signal (bus release request signal: signal requesting the release of the bus right / active “L” to the CPU) is output from the DMAC 200 to the CPU 100, and the BACKN signal (bus acknowledge signal) is output from the CPU 100 to the DMAC 200. : A signal indicating that the bus right is permitted to be released / active “L” is output to the external DMAC.
[0054]
Here, there are two DMA transfer directions: external request device-> external memory direction and external memory-> external request device direction. This transfer direction can be set for the DMAC 200 by the CPU 100.
[0055]
FIG. 6 is a block diagram showing the configuration of the DREQ signal mask circuits 210 and 220. As shown in FIG. Since the DREQ signal mask circuits 210 and 220 of each channel have the same configuration, the DREQ signal mask circuit 210 will be described as a representative.
[0056]
In FIG. 6, a DREQ signal mask circuit 210 is a counter circuit 211 that counts (decrements) at the rising edge of the sampling clock, compares the count data with a predetermined value “0”, and when the count data matches “0”, the sampling clock The comparator 212 and the mask circuit 213 output a pulse corresponding to the period of time, that is, a counter TC (Terminal Count) signal.
[0057]
The counter circuit 211 receives an initial value for counting from the data bus and a sampling clock for counting. Further, the current count value, which is the data counted by the counter circuit 211, is input to the comparator 212, and the counter TC signal is output from the comparator 212.
[0058]
The counter TC signal is a signal that becomes a pulse of “H” with a width corresponding to one sampling clock in the interval in which the input count data value becomes “0”, and indicates that the count is completed.
[0059]
The mask circuit 213 receives the counter TC signal output from the comparator 212, the DREQ signal and the DACK signal, and outputs the BREQ signal.
[0060]
FIG. 7 is a diagram showing a detailed configuration inside the mask circuit 213 of FIG.
[0061]
In FIG. 7, the mask circuit 213 outputs a mask signal generation circuit 214 that outputs a mask signal that enables a mask signal generated internally when a DACK signal is input based on the counter TC signal, and the generated mask signal. And an OR gate 215 taking OR logic of the DREQ signals.
[0062]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0063]
FIG. 8 is a timing chart for explaining the operation of the DMA transfer apparatus. In the figure, the numbers (1) to (5) are symbols for explaining the operation timing or the operation interval.
[0064]
Of the two channels CH0 and CH1, first, the CH0 DREQ0 signal mask circuit 210 will be described as an example.
[0065]
In the timing chart of FIG. 8, it is assumed that the DREQ0 signal is enabled (“H”) after a lapse of a certain time after the DACK0 signal is disabled (“L”).
[0066]
At timing (1) in FIG. 8, the CPU 100 writes the timer count value to the DREQ0 signal mask circuit 210. In the case of this operation, “5” is written.
[0067]
Next, at the timing of (1) -1 in FIG. 8, the CPU 100 sets mask_en0 to “H”. With the operation of the CPU 100 so far, the DREQ0 signal mask circuit 210 becomes operable.
[0068]
  Next, the DREQ0 signal output from the external request device 240 is input to the timer. At this time, the DREQ0 signal mask circuit 210 does not operate, and the DMAC 200 operates at the input timing of DREQ0.BREQNA signal is output to the CPU 100.
[0069]
The CPU 100 that has received the BREQN signal outputs the BACKN signal at a certain fixed timing (depending on the CPU specifications) (see the section (2) -1 in FIG. 8). This section is a section in which the DMAC 200 occupies the bus, and in this section, the CPU 100 releases the bus right.
[0070]
In section (2) -1 of FIG. 8, the DMAC 200 generates a DACK0 signal from the BACKN signal and outputs it to the external request device 240. At this time, the mask signal is set to “H” at the falling timing of the DACK0 signal (see (3) -1 in FIG. 8). Thereafter, the DREQ0 signal is masked with the mask signal at the timing of (5) -1 in FIG.
[0071]
Here, the mask operation of the DREQ signal mask circuits 210 and 220 will be described with reference to FIGS.
[0072]
In FIG. 6, the CPU 100 sets an initial count value (“5h” in the present embodiment) to the counter circuit 211. At this time, counting is not performed until the DACK signal is input.
[0073]
Counting (decrementing) is performed at the rising edge of the sampling clock, and the comparator 212 compares this count data with a predetermined value “0”. When the count data matches “0”, the counter TC signal is output for the period of the sampling clock.
[0074]
On the other hand, in the mask circuit 213, when the DACK signal is input, the mask signal of the internal mask signal generation circuit 214 (FIG. 7) is enabled (active “H”), and this mask signal and the DREQ signal are output in the OR gate 215. Is output as a BREQ signal. In order to disable the mask signal, the counter TC signal is used to disable the mask signal. This mask signal is a signal generated by the mask signal generation circuit 214, which is “H” by the DACK signal and is “L” by the counter TC signal.
[0075]
Returning to the description of the timing chart of FIG.
[0076]
A BREQN signal is created by using the DREQ0 signal as an input and the output generated from the mask signal.
[0077]
The counter of the counter circuit 211 of the DREQ signal mask circuit 210 is decremented in synchronization with the sample clock from (3) -1 point in FIG. When the counter value becomes “0”, a counter TC signal is generated (active “H”).
[0078]
Using the falling edge of the counter TC signal, the mask signal becomes “L” and the mask is disabled (see (4) -1 in FIG. 8). When the mask signal becomes “L”, the mask signal of the mask circuit 213 becomes “L”, so that the DREQ0 signal passes through the gate and becomes an output. The BREQN signal is output using this output signal (see (4) -1 in FIG. 8 for timing).
[0079]
Here, since BREQN is not output in the interval from the falling edge of the BACKN signal of (5) -1 to (2) -2 in FIG. 8, the bus right is in the CPU 100.
[0080]
The operation sequence after (4) -1 in FIG. 8 is the same as described above.
[0081]
As shown in FIG. 8, the sections (2) -1, (2) -2, and (2) -3 are sections in which the DMAC 200 owns the bus right, and in other sections, the CPU 100 has the bus right. It is the section which is doing.
[0082]
The operation related to the external request device 240 has been described above, but the same operation is performed for the external request device 241 as well.
[0083]
Next, arbitration of the DREQ0 / DREQ1 signals of CH0 and CH1 will be described.
[0084]
FIG. 9 is a timing chart for explaining the arbitration operation of the DMAC 200 of the DMA transfer apparatus. In the figure, ◯ indicates the start of the CH0 DMA sequence, ● indicates the start of the CH0 DMA sequence, and numbers (1) to (2) are codes for explaining the operation timing. The DREQ signal monitoring CH is inside the arbitration circuit 230.
[0085]
In the arbitration of the DREQ0 / DREQ1 signal in the DMAC 200, the arbitration circuit 230 monitors whether the DREQ is input in the order of CH0 → CH1 → CH0 →.
[0086]
Here, a case where DREQ0 and DREQ1 are input at the beginning of the T1 section will be described as an example.
[0087]
First, at the location (1) in FIG. 9, DREQ0 / DREQ1 is input simultaneously when DREQ monitoring is monitoring CH0, so DREQ0 is given priority. Upon receiving DREQ0, the BREQN signal becomes “L” (see the circled portion in FIG. 9).
[0088]
Next, since the DREQ signal monitoring CH indicates CH1 at the time when the DMA sequence of CH0 is completed in the section T3 (see the section (2)), and since the DREQ1 signal is enabled, the section T4 The BREQN signal that received DREQ1 at this time becomes “L” (see the portion ● in FIG. 9). The CH1 DMA sequence ends in the T5 interval.
[0089]
In the period from T6 to T8, the DREQ signal monitoring CH monitors DREQ0 / DREQ1 of CH0 / CH1 every cycle and waits for the DREQ signal to be input. At this time, since the mask signal CH0 and the mask signal CH1 are operating, DREQ0 is masked at T6 and DREQ1 is masked at T8.
[0090]
At T9, since the mask signal CH1 becomes “L”, the BREQN signal is enabled (“L”) in the T10 interval, the CH1 DMA sequence is performed, and the sequence ends in the T11 interval.
[0091]
In addition, since the mask signal CH0 becomes “L” in the T12 interval and the DREQ monitoring CH indicates “0”, the BREQN signal that received DREQ0 in the T13 interval becomes “L”, and the DMA sequence of CH0 is Done.
[0092]
In this way, the DREQ signal is monitored by the DREQ monitoring CH, and when the validated DREQ signal and the monitoring CH are the same, the BREQN signal is set to “L” to start the DMA sequence.
[0093]
As described above, in the DMA transfer apparatus according to the second embodiment, the DREQ signal mask circuits 210 and 220, in which the DMAC 200 is installed for each channel and controlled by the mask signals mask_en0 and mask_en1 from the CPU 100, and the DREQ are provided. And an arbitration circuit 230 for arbitrating the BREQ0 and BREQ1 signals of the signal mask circuits 210 and 220, and the DREQ signal mask circuits 210 and 220 are configured to mask the DREQ0 / DREQ1 signals and control the bus occupation state by DMA transfer. Therefore, by masking the DREQ signal of the external request device on the DMAC side (internal), it is possible to control the system bus occupancy rate by the DMA by periodically generating the DREQ signal. Occupied and CPU Can be avoided that would not be able to process it, there is an effect that can prevent the collapse of the system.
[0094]
Further, in the present embodiment, since the DREQ signal mask circuits 210 and 220 are mounted inside the DMAC 200, when the external request device is newly added, the mask circuit is added every time a new device is mounted. There is an effect that it is possible to prevent an increase in hardware due to the problem.
[0095]
In addition, by installing the DREQ monitoring CH by the arbitration circuit 230 on the DMAC side (internal), it is possible to give priority to the DMA transfer channels and distribute the DMA channels evenly.
[0096]
In the present embodiment, the DREQ signal mask circuits 210 and 220 for masking the DREQ signal are provided in the DMAC 200. However, these mask circuits 210 and 220 may be provided on the DMAC side, and are not necessarily required. The configuration may not be installed inside the DMAC.
Third embodiment
FIG. 10 is a block diagram showing a configuration of a DMA transfer apparatus according to the third embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0097]
In FIG. 10, the DMA transfer apparatus includes a CPU 100, a DMAC 300, an external request device 350, an external request device 351, an external request device 352, and an external memory 113. The DMAC 300 includes a counter-equipped mask circuit 310 that masks the BREQN signal. Configured.
[0098]
The DMAC 300 is equipped with three DMA channels, which are CH0, CH1, and CH3. Further, CH0, CH1, and CH2 are connected to an external request device 351, an external request device 352, and an external request device 353, respectively.
[0099]
The DMA channel of the external request device 351 is CH1, the DMA channel of the external request device 352 is CH2, and the DMA channel of the external request device 353 is CH3.
[0100]
As shown by the broken lines in FIG. 10, DMA request signals DREQ1, DREQ2, and DREQ3 are output from the external request device 351, the external request device 352, and the external request device 353 to the DMAC 300 for each of CH0, CH1, and CH2, and from the DMAC 300 DMA permission signals DACK1, DACK2, and DACK3 are output to the external request device 351, the external request device 352, and the external request device 353.
[0101]
The DMAC 300 outputs a bus release request signal BREQN to the CPU 100, and the CPU 100 outputs a bus release permission signal BACKN to the DMAC 300.
[0102]
The mask_en signal output from the CPU 100 to the DMAC 300 is a signal output from the port of the CPU 100 and is a signal (active “H”) that enables the counter circuit of the counter-equipped mask circuit 310.
[0103]
FIG. 11 is a block diagram showing the configuration of the counter-equipped mask circuit 310. As shown in FIG.
[0104]
In FIG. 11, the counter circuit 311 that counts (decrements) at the rising edge of the sampling clock and the count data is compared with a predetermined value “0”. When “0” and the count data match, a pulse corresponding to the sampling clock period, In other words, the comparator 312 that outputs the counter TC signal, and the mask circuit 313 that generates an OR (logical sum) of the BREQ signal and the mask_en mask signal generated in the DMAC 300 to generate the BREQN signal.
[0105]
The counter circuit 311 receives a data bus, a sample clock, and a BACKN signal, and outputs a current count value.
[0106]
The comparator 312 receives the current count value data output from the counter circuit 311 and outputs a counter TC signal.
[0107]
The mask circuit 313 receives the BREQ signal created from the DREQ signal in the DMAC 300, the BACKN signal from the CPU 100, the mask_en signal, and the counter TC signal from the comparator 312, and outputs the BREQN signal.
[0108]
FIG. 12 is a diagram showing a detailed configuration inside the mask circuit 313 of FIG.
[0109]
12, a mask circuit 313 outputs a mask signal generating circuit 314 that outputs a mask signal that enables a mask signal generated internally when a BACKN signal is input based on the counter TC signal, and the generated mask signal. And an OR gate 315 that takes the OR logic of the BREQ signals.
[0110]
FIG. 13 is a diagram showing a configuration from the DMA request signals DREQ1, DREQ2, and DREQ3 to generation of a BREQN signal.
[0111]
In FIG. 13, reference numeral 316 denotes a DREQ signal arbitration circuit that arbitrates DREQ1, DREQ2, and DREQ3 signals from the external request device 351, the external request device 352, and the external request device 353, and outputs a BREQ signal created in the DMAC 300.
[0112]
The BREQ signal created by the DREQ signal arbitration circuit 316 is output to the mask circuit 313 (FIGS. 11 and 12), and the mask circuit 313 outputs the BREQN signal.
[0113]
Here, similarly to the DREQ signal mask circuits 210 and 220 of the second embodiment, the mask circuit with mask counter 310 of the present embodiment employs a method of determining a mask time by providing a hardware counter (timer). . However, a method of determining the mask time by providing a hardware counter (timer) as in the second embodiment is also possible, and the mask time is utilized by using the CPU port using the CPU's own timer interrupt. It is also possible to control.
[0114]
In this embodiment, the counter value of the counter circuit 311 in the mask circuit 310 with a mask counter is set so as to be a mask time (selected according to the number of external request devices). On the other hand, data is set so as to have a predetermined mask time. This can also be realized using the timer interrupt of the CPU itself.
[0115]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0116]
First, the operation of the counter-equipped mask circuit 310 will be described.
[0117]
As shown in FIG. 11, the CPU 100 sets an initial value to be counted in the counter circuit 311 (in the present embodiment, “5h” is set). Next, when the BACKN signal is input, counting (decrement) is performed at the rising edge of the sample clock. Next, the comparator 312 compares the current count value with “0”, and if they match, a pulse for one cycle of the sample clock is output.
[0118]
On the other hand, in the mask circuit 313, as shown in FIG. 12, the internal mask signal is enabled (active “H”) by the BACKN signal, and the OR gate 315 of the BREQ signal created from the DREQ inside the DMAC 300 and the internal mask signal. Is output as BREQN. Here, the internal mask signal is a signal that is enabled (active “H”) by the BACKN signal and disabled (active “L”) by the counter TC signal.
[0119]
As shown in FIG. 10, the mask_en signal is a signal input from the CPU 100 to the DMAC 300 and is controlled by a port of the CPU 100. This mask_en signal is a signal for controlling whether to enable or disable the entire mask circuit with mask counter 310. When the BREQ is output without using the mask circuit with mask counter 310, the CPU 100 is disabled. ("L").
[0120]
FIG. 14 is a timing chart for explaining the operation of the DMA transfer apparatus.
In the drawing, numbers (1) to (4) are reference numerals for explaining operation timings or operation intervals.
[0121]
In the timing chart of FIG. 14, it is assumed that the DREQ1, DREQ2, and DREQ3 signals are simultaneously enabled at the timing (2) of FIG. The priority of the DMA request of each CH (CH1, CH2, CH3) is a round robin method such as CH1 → CH2 → CH3 → CH1.
[0122]
A case where the counter value of the counter-equipped mask circuit 310 is set to “5” is taken as an example.
[0123]
The count value “5” is set at the timing (1) in FIG.
[0124]
Next, three DREQs (DREQ1, DREQ2, DREQ3) are simultaneously enabled at the timing of (2) in FIG. Here, the section (2) -1 in FIG. 14 is a section in which the CH1 DMA is executed.
[0125]
Next, the mask signal is enabled at the timing (3) -1 in FIG. 14 (rising edge of the BACKN signal), and the BREQ signal is masked. The count is also started at the point (3) -1, that is, at the timing when the BACKN signal becomes “H”. The mask circuit for the BREQ signal is the mask circuit 313 in FIG. 11, and the BREQ signal in the DMAC 300 is masked by the mask signal from the mask circuit 313.
[0126]
Next, at the timing of (4) -1 in FIG. 14, the counter value becomes “0”, the mask signal becomes “L” (disabled), the mask is released, and the BREQN signal is output outside the DMAC 300. In the section (2) -2 in FIG. 14, DMA transfer of CH2 is performed.
[0127]
Next, the mask signal is enabled at the timing (3) -2 in FIG. 14 (the rising edge of the BACKN signal), and the BREQN signal is masked. This mask operation is performed by the mask circuit 313 shown in FIG.
[0128]
Next, at the timing of (4) -2 in FIG. 14, the counter becomes “0”, the mask signal becomes “L” (disabled), the mask is released, and the BREQN signal is output to the outside of the DMAC 300.
[0129]
In this way, the cycle in which BREQN occurs is adjusted by masking the BREQN signal.
[0130]
As described above, in the DMA transfer apparatus according to the third embodiment, the DMAC 300 includes the mask circuit 310 with a counter that masks the BREQN signal, and the mask circuit 310 with a counter masks the BREQN signal and performs a bus by DMA transfer. Since the occupation state is controlled, the same effects as those of the first and second embodiments can be obtained.
[0131]
In particular, according to the present embodiment, the DREQ signal output from the external request device is not masked as in the second embodiment, but the BREQN signal is masked inside the DMAC 300. In this way, as in the second embodiment, it is possible to make one mask circuit rather than adding a mask circuit for each CH, and the hardware is smaller than in the second embodiment. There is an effect that can be done.
[0132]
Further, since the BREQN signal is masked, even when DREQ signals from a plurality of external request devices are frequently overlapped, it is possible to control to output the BREQN signal periodically, and the bus occupancy rate by the DMAC 300 There is an effect that can be made constant.
Fourth embodiment
FIG. 15 is a block diagram showing a configuration of a DMA transfer apparatus according to the fourth embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0133]
15, the DMA transfer apparatus includes a CPU 100, a DMAC 400, a plurality of external request devices (451, 452, 453,..., N−1, N), and an external memory 113.
[0134]
The DMAC 400 is equipped with a plurality of DMA channels, which are CH1, CH2, CH3,..., CHN-1, CHN. Further, CH1, CH2, CH3,..., CHN-1, CHN are connected to corresponding external request devices (451, 452, 453,..., N-1, N), respectively.
[0135]
The DMAC 400 includes a plurality of DREQ signal mask circuits 410,... Installed corresponding to CH1, CH2, CH3,..., CHN-1, and CHN, and an arbitration circuit 230 that arbitrates the BREQ signals of the DREQ signal mask circuits 410,. With.
[0136]
The DREQ signals output from the external request device 451, the external request device 452, and the external request device 453 are DREQ1, DREQ2, and DREQ3, respectively, and the DACK signals corresponding to the request signals are DACK1, DACK2, and DACK3, respectively. At this time, external request device (N-1) and external request device (N) indicate the number of external request devices that DMAC 400 can handle in the sense that there are a plurality of external request devices. The external memory 113 is a memory of the DMA system, and becomes a source device and a destination device of the DMA system.
[0137]
A mask circuit with a mask counter (DREQ signal mask circuit) incorporating a mask counter and a mask circuit is mounted in each DMAC 400 for each channel. The mask circuit has the same circuit configuration as that shown in FIGS. 2 and 3, and the CPU 100 sets a counter value corresponding to the mask time for the mask counter.
[0138]
  Inside the DMAC400DREQThe signal arbitration circuit 230 arbitrates the DREQ signal output from each channel and outputs a BREQN signal to the CPU 100. The arbitration method is the same as that in the second embodiment, and the DMA sequence to be performed is determined according to the input order of the DREQ signals and the DREQ signal monitoring CH (see the operation description in FIG. 9).
[0139]
The DMAC 400 outputs a BREQN signal (bus release request signal: signal requesting the CPU to release the bus right / active “L”) to the CPU 100, and the CPU 100 outputs a BACKN signal (bus release permission signal to the DMAC 400). : A signal indicating that the bus right is permitted to be released / active “L” is output to the external DMAC.
[0140]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0141]
FIG. 16 is a timing chart for explaining the operation of the DMA transfer apparatus.
In the drawing, numbers (1) to (12) are reference numerals for explaining operation timings or operation intervals.
[0142]
Operation when the DREQ1, DREQ2, and DREQ3 signals are output from the external request device 451, the external request device 452, and the external request device 453 at the same time (points (1) and (7) in FIG. 16), respectively. explain.
[0143]
The CPU 100 sets a mask time for the mask timers (Ch1 to ChN) in the DMA controller 400. The set value is a value shown in FIG. In the present embodiment, since the number of external request devices is 3, the mask time is set to 2 μs from the table shown in FIG.
[0144]
Since the DMAC 400 enables only one channel of DMA at an arbitrary timing, the order in which the channels are enabled is enabled in the order of Ch1, Ch2,..., ChN.
[0145]
In the timing chart of FIG. 16, BREQN becomes “L” in response to DREQ1 at points (1) and (7), and a DMA sequence is started. After this DMA sequence is completed, the MASK1 signal is enabled at points (2) and (8). Since the mask time is set to 2 μs, masking is performed for 2 μs.
[0146]
Next, DREQ2 is received at the timings (3) and (9) in FIG. 16, BREQN becomes "L", and the DMA sequence is started. This DMA sequence ends at the timings (4) and (10) in FIG. 16, but the masking is started at this timing.
Again, since the mask time is set to 2 μs, the mask is performed for 2 μs.
[0147]
Similarly, DREQ3 is received at the timing of points (5) and (11) in FIG. 16, the DMA sequence is started, the DMA sequence is ended at points (6) and (12), and masking is started. In this series of flows, there is a section where DMA is not performed between the points (6) and (13). In this section, the CPU 100 performs processing according to the program of the system. be able to. This section is a section that does not exist without a DREQ mask. This interval is determined by the generation period of DREQ1, DREQ2, and DREQ3 and the number of external request devices mounted.
[0148]
  As described above, the DMA transfer apparatus according to the fourth embodiment has a plurality of DREQ signal masks installed corresponding to CH1, CH2, CH3,..., CHN-1, CHN on the DMAC 400 side (inside). , And an arbitration circuit 230 that arbitrates the BREQ signal of the DREQ signal mask circuit 410,..., And a plurality of DREQ signal mask circuits 410,.SameWork whenOutsideSince the mask time is controlled in accordance with the number of request devices, the DMA transfer opportunities of the respective DMA channels can be given equally in time, and the temporal arbitration of the DMA channels becomes possible.
[0149]
That is, when a plurality of operable external request devices exist on the same bus, the time for the DMAC 400 to occupy the bus naturally increases as a system. That is, the bus occupation rate by the DMAC 400 increases. In this embodiment, by controlling the mask time of the DREQ signal by the number of simultaneously operating external request devices, the average DMAC bus occupancy can be controlled, and there are a plurality of external request devices. There is an effect that a significant increase in the bus occupancy rate of the DMAC 400 in the system can be prevented.
[0150]
In this embodiment, the example in which the method of the second embodiment is used as the bus occupancy rate control method of the DMAC 400 has been shown. However, as shown in the method of the first embodiment, an external request device that can operate. It is also possible to control by the side, or by controlling the BREQ of the DMAC 400 by the method of the third embodiment.
Fifth embodiment
FIG. 18 is a block diagram showing a configuration of a DMA transfer apparatus according to the fifth embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0151]
18, the DMA transfer apparatus includes a CPU 500, a DMAC 400, a plurality of external request devices (451, 452, 453,..., N−1, N), and an external memory 113.
[0152]
In the program of the CPU 500, a task management function 510 (management means) for managing processing tasks of the program is mounted.
[0153]
The DMAC 400 is equipped with a plurality of DMA channels, which are CH1, CH2, CH3,..., CHN-1, CHN. Further, CH1, CH2, CH3,..., CHN-1, CHN are connected to corresponding external request devices (451, 452, 453,..., N-1, N), respectively.
[0154]
The DMAC 400 includes a plurality of DREQ signal mask circuits 410,... Installed corresponding to CH1, CH2, CH3,..., CHN-1, and CHN, and an arbitration circuit 230 that arbitrates the BREQ signals of the DREQ signal mask circuits 410,. With.
[0155]
The DREQ signals output from the external request device 451, the external request device 452, and the external request device 453 are DREQ1, DREQ2, and DREQ3, respectively, and the DACK signals corresponding to the request signals are DACK1, DACK2, and DACK3, respectively. At this time, external request device (N-1) and external request device (N) indicate the number of external request devices that DMAC 400 can handle in the sense that there are a plurality of external request devices. The external memory 113 is a memory of the DMA system, and becomes a source device and a destination device of the DMA system.
[0156]
Further, mask_en1, mask_en2, and mask_en3 output from the CPU 500 are signals for enabling masking of the DREQ signal mask circuits 410,... (DREQ signal mask circuits CH1, CH2, and CH3), respectively. The control is performed by the CPU 500 itself by port control.
[0157]
  Inside the DMAC400DREQThe signal arbitration circuit 230 arbitrates the DREQ signal of each channel (CH1 / 2/3...) And outputs the BREQN signal to the CPU 500. The arbitration method is the same as in the second embodiment.
[0158]
Further, a BREQN signal (bus release request signal: active “L”) is output from the DMAC 400 to the CPU 500, and in response to the BREQN signal, the CPU 500 sends a BACKN signal (bus release permission signal: active) to the DMAC 400. “L”) is output.
[0159]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0160]
The CPU 500 performs processing in accordance with a normal program, but the processing load on the CPU differs depending on the task to be processed. The task management function 510 in the CPU 500 has a function of constantly monitoring what task is currently being processed and holding the information. This task management function 510 is realized by software.
[0161]
First, the table of FIG. 19 shows the relationship between the task names T1 to T10 on the program and the processing load and the corresponding mask time.
[0162]
As shown in FIG. 19, the CPU 500 is a program that processes tasks in the order of T1, T2, T3,..., T10, T1,.
[0163]
Hereinafter, the case where the enable interval of DREQ1 when DREQ1 is continuously generated is 1 μs will be described as an example.
[0164]
FIG. 20 is a timing chart for explaining the operation of the DMA transfer apparatus.
[0165]
First, as shown in FIG. 20, while the task T1 is being processed, the mask time is set to 1 μs (see the table in FIG. 19). If the DREQ1 signal is enabled at this time, the DREQ1 signal is always masked by a mask in the DMAC 400 for 1 μs, and DMA transfer is performed. In this case, the mask setting time is 1 μs, but since the enable interval of DREQ1 is 1 μs, there is no effect even if the mask timer is valid.
[0166]
Next, a description will be given of when the task T2 is being processed. At this time, the mask time is set to 2 μs (see the table in FIG. 19). At this time, if the DREQ1 signal is enabled, the DREQ1 signal is always masked by the DREQ signal mask circuit 410 in the DMAC 400 for 2 μs, and DMA transfer is performed. In this case, since the DREQ enable interval is 1 μs, the mask setting time is 2 μs, so that the mask effect can be obtained by 1 μs.
[0167]
Similarly, in the case of task T3, the mask effect comes out by 2 μs, and in the case of task T4, the mask effect comes out by 3 μs.
[0168]
The above operation is performed for each channel. Further, the arbitration operation of each channel is the same as in the second embodiment.
[0169]
As described above, the DMA transfer apparatus according to the fifth embodiment is configured such that the CPU 500 includes the task management function 510 that manages the processing task of the program, and controls the mask time according to the processing load of the CPU. Therefore, the following effects can be obtained.
[0170]
That is, when the CPU processing (task) is complicated and there are many tasks on the system that must be completed within a predetermined time, the BREQ signal output from the DMAC is time-consuming for the CPU processing. It can be inefficient. At this time, as in this embodiment, by performing the mask operation of the DREQ signal for each task, the CPU processing can be completed within a predetermined time, and the temporal processing capability of the CPU on the system can be achieved. There is an effect that can prevent the decrease of.
[0171]
In this embodiment, the operation of the DMAC is controlled by the method of the second embodiment. However, as shown in the first embodiment, the method of controlling the DMAC operation on the external request device side may also be used. As shown in the above, it can be realized by a method of controlling the BREQ signal in the DMAC.
Sixth embodiment
FIG. 21 is a block diagram showing a configuration of a DMA transfer apparatus according to the sixth embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0172]
In FIG. 21, the DMA transfer apparatus includes a CPU 100, a DMAC 600, an external request device 650, and an external memory 113. The DMAC 600 detects a DREQ signal generation circuit and a DREQ cycle detection circuit that detects a generation cycle of a DREQ signal. And a circuit 620 (DREQ cycle detection means).
[0173]
A DREQ signal is output from the external request device 650 to the DMAC 600, and a DACK signal is output from the DMAC 600 to the external request device 650.
[0174]
A BREQ signal is output from the DMAC 600 to the CPU 100, and a BACK signal is output from the CPU 100 to the DMAC 600.
[0175]
The external memory 113 becomes a source device (or destination device) for DMA transfer.
[0176]
The mask_en signal output from the CPU 100 is a signal that enables the DREQ signal mask circuit 610.
[0177]
The CPU 100 outputs the mask signal mask_en to the DREQ signal mask circuit 610 to control the DREQ signal mask circuit 610.
[0178]
FIG. 22 is a diagram showing a circuit configuration of the DREQ cycle detection circuit 620.
[0179]
In FIG. 22, a DREQ cycle detection circuit 620 receives an DREQ signal and logically detects an edge of the DREQ signal, an edge detection circuit 621, a counter 622 that counts (decrements) at the rising edge of the sampling clock, and count data. It consists of a data buffer 623 for storing.
[0180]
The data buffer 623 is a buffer that holds data so that the CPU 100 (FIG. 21) can read the result of the counter 623.
[0181]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0182]
FIG. 23 is a timing chart showing the operation of the DREQ cycle detection circuit 620.
[0183]
  First, from the external request device 650DREQThe signal is input to the DMAC 600, and the input signal is input to the internal DREQ cycle detection circuit 620.
[0184]
In the internal circuit of the DREQ cycle detection circuit 620, as shown in the timing chart of FIG. 23, the edge detection unit 621 detects the rising edge of the DREQ signal, and the counter 622 starts counting using the detected pulse as a trigger.
This count is performed until the next DREQ signal edge.
[0185]
The count data counted by the counter 622 is transferred to the data buffer 623, and the data buffer 623 holds the data after the count is completed.
[0186]
FIG. 24 is a timing chart for explaining the operation of the DMA transfer apparatus.
[0187]
The CPU 100 reads the count data in the data buffer 623 at an arbitrary timing, and performs an operation for enabling / disabling the mask_en signal through the CPU port according to the data. That is, if the read count data is small, the CPU 100 lengthens the time during which the mask_en signal is enabled.
[0188]
As shown in FIG. 24, when the mask_en signal is enabled, the DREQ signal is masked for a certain period (interval), and after the masking is released, the mask_en signal is disabled and output as the BREQ signal to the CPU 100.
[0189]
The CPU 100 that has received the BREQ signal outputs a BACK signal to notify that the bus right has been released.
[0190]
As shown in FIG. 24, the interval in which the mask_en signal is disabled has a shorter BREQ signal generation interval, but the interval in which the mask_en signal is enabled is longer than the interval in which the BREQ generation interval is disabled. I can see that
This section (section in which the mask effect is produced) is a section in which the CPU 100 is processing according to the program.
[0191]
As described above, in the DMA transfer apparatus according to the sixth embodiment, the DMAC 600 includes the DREQ signal mask circuit 610 and the DREQ period detection circuit 620 that detects the generation period of the DREQ signal, and the DREQ period detection circuit 620. Is detected, and the DREQ signal is masked using the counter data value, so that the DMA period (interval) can be widened. This has the effect of reducing the bus occupancy rate.
[0192]
Also, if this method is used, the DMA transfer speed can be controlled by the CPU 100, so that the same applies when an I / O device (external request device) whose DREQ signal generation cycle varies exists on the bus. There is an effect that the BREQ signal is generated in a cycle and the bus occupancy is reduced.
[0193]
In this embodiment, the DMAC operation is controlled by the method of the second embodiment. However, as shown in the method of the first embodiment, the DMAC operation can be controlled by the operable external request device side. Further, as shown in the method of the third embodiment, it can also be realized by a method of controlling the BREQ in the DMAC.
Seventh embodiment
FIG. 25 is a block diagram showing a configuration of a DMA transfer apparatus according to the seventh embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIG.
[0194]
In FIG. 25, the DMA transfer apparatus includes a CPU 100, a DMAC 700, an external request device 751, an external request device 752, and an external memory 113. The DMAC 700 includes a BREQN signal mask circuit 720 (mask means) and a plurality of operations that permit operations. A BREQN cycle detection circuit 720 (BREQN cycle detection means) that detects a generation cycle of a BREQN signal generated in accordance with the DREQ signal of the external request device is configured.
[0195]
The DMAC 700 is equipped with a plurality of (two) DMA channels, which are CH1 and CH2. CH1 and CH2 are connected to an external request device 751 and an external request device 752, respectively.
[0196]
The DMA channel of the external request device 751 is CH1, and the DMA channel of the external request device 752 is CH2.
[0197]
As shown by the broken lines in FIG. 25, the DMA request signals DREQ1 and DREQ2 (active “H”) are output from the external request device 751 and the external request device 752 to the DMAC 700 for each of the CH1 and CH2. DMA permission signals DACK 1 and DACK 2 are output to the request device 751 and the external request device 752.
[0198]
The DMAC 700 outputs a bus release request signal BREQN (active “L”) to the CPU 100, and the CPU 100 outputs a bus release permission signal BACKN (active “L”) to the DMAC 700.
[0199]
The mask_en signal output from the CPU 100 to the DMAC 700 is a signal output from the port of the CPU 100 and is a signal (active “H”) for enabling the counter circuit of the BREQN mask circuit 720.
[0200]
FIG. 26 is a diagram showing a circuit configuration of the BREQN signal cycle detection circuit 720.
[0201]
In FIG. 26, a BREQN signal cycle detection circuit 720 receives the BREQN signal and logically detects an edge of the BREQN signal, a counter 722 that counts (decrements) at the rising edge of the sampling clock, and count data Is stored in the data buffer 723.
[0202]
A count pulse is output from the edge detection circuit 721 to the counter, and the count data is transferred from the counter 722 to the data buffer 723.
[0203]
The data buffer 723 is a buffer that holds data so that the CPU 100 (FIG. 25) can read the result of the counter 723.
[0204]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0205]
FIG. 27 is a timing chart showing the operation of the BREQN signal cycle detection circuit 720, and FIG. 28 is a timing chart for explaining the operation of the DMA transfer apparatus.
[0206]
First, in the present embodiment, the priority of DMA transfer of CH1 and CH2 is a round robin type that rounds in the order of CH1 → CH2 → CH1 → CH2. At the same time, when DREQ (request signal) is input to the DMAC 700, priority is given to CH1, and in other cases, priority is given to the one that receives DREQ (request signal) in time.
[0207]
As an example, DREQ1 and DREQ2 are active at the point (1) in FIG. At this time, the DMA of CH1 is performed.
[0208]
Next, CH2 DMA is performed at point (2) in FIG. At this time, the BREQN signal cycle detection circuit 720 shown in FIG. 26 operates at the falling edge of the BREQN signal shown in FIGS. 28 (1) and (2), and the counter 722 operates. Then, the count data is transferred to the data buffer 723 as shown in the timing chart of FIG.
[0209]
Further, the DMA of CH1 is executed at the point (3) in FIG. 28. At this time as well, the BREQN signal period detection circuit 720 performs the interval between the edges of the BREQN in FIG. 28 (2) and (3). A count is performed. The count data at this time is also overwritten in the data buffer 723.
[0210]
When the DMA transfer of (3) in FIG. 28 is completed, the CPU 100 reads the data in the data buffer 723. With this read value, the CPU 100 can recognize the generation cycle of the BREQN signal of the DMAC 700.
[0211]
Next, at the point of (4) -1 in FIG. 28, that is, when the BACKN signal becomes “H”, the CPU 100 sets the mask_en1 signal to “H”. When mask_en1 is set to “H”, the BREQN signal is masked, and even if DREQ1 and DREQ2 are input, the BREQN signal is not output to the outside (see the section in FIG. 28 where the mask effect is produced).
[0212]
The same applies to points (4) -2 and (4) -3 in FIG.
[0213]
The time during which the CPU 100 sets mask_en1 to “H” is controlled based on the value of the generation period of the BREQ signal read earlier. For example, when the numerical value read from the data buffer 723 is extremely short, the time during which the mask_en1 is set to “H” is lengthened to reduce the bus occupancy by the DMAC 100, and conversely, the data buffer 723 is read. When the numerical value is extremely long, the time during which the mask_en1 signal is set to “H” can be controlled to be short.
[0214]
As described above, the CPU 100 can control the bus occupation rate by the DMAC 700 of the apparatus by recognizing the BREQ generation cycle.
[0215]
As described above, in the DMA transfer apparatus according to the seventh embodiment, the DMAC 700 determines the generation period of the BREQN signal generated in association with the BREQN signal mask circuit 720 and the DREQ signals of a plurality of external request devices that permit operation. A BREQN cycle detection circuit 720 that detects the edge, and the BREQN signal cycle detection circuit 720 receives the BREQN signal and logically detects the edge of the BREQN signal, and counts (decrements) at the rising edge of the sampling clock. Since the counter 722 and the data buffer 723 for storing the count data are configured, the generation period (generation interval) of the BREQN signal is counted using the edge of the BREQN signal, and the count data is held in the data buffer 723. By leaving CPU 100 is able to be aware of the generation period of the BREQ input from DMAC700, the CPU 100, it is possible to control the bus occupancy by DMAC700.
[0216]
Further, as in the sixth embodiment, when a DREQ cycle detection circuit 620 for detecting the generation cycle of DREQ is mounted for each CH (channel), the DREQ cycle detection circuit is configured when a large number of external request devices are mounted. It is necessary to newly add a counter and a data buffer for each CH. According to the present embodiment, since the BREQN cycle detection circuit 720 is mounted on the BREQN signal, even if a large number of external request devices are mounted, one counter or data buffer is included in the BREQN cycle detection circuit. Since only this is necessary, the hardware scale can be reduced.
[0217]
In this embodiment, the DMAC operation is controlled by the method of the third embodiment. However, the control method can be controlled by the CPU, or a masking circuit can be provided with a hardware timer and masked with hardware. It is. In addition, as shown in the method of the first embodiment, control can be performed on the operable external request device side, and as shown in the method of the second embodiment, control can be performed on the DMAC side. is there.
Eighth embodiment
FIG. 29 is a block diagram showing a configuration of a DMA transfer apparatus according to the eighth embodiment of the present invention. In the description of the DMA transfer apparatus according to the present embodiment, the same components as those in FIGS. 18 and 21 are denoted by the same reference numerals.
[0218]
29, the DMA transfer apparatus includes a CPU 800 (setting means), a DMAC 600, an external request device 650, and an external memory 113. The DMAC 600 includes a DREQ signal mask circuit 610 and a DREQ cycle detection circuit 620. The
[0219]
In the program of the CPU 800, a task management function 810 (management means) for managing processing tasks of the program is installed. This task management function 810 is realized by software.
[0220]
The DMAC 600 receives the DREQ signal from the external request device 650. When the mask is enabled, the DMAC 600 masks the DREQ signal for the interval of the mask_en signal and outputs the BREQN signal to the CPU 800. When the CPU 800 releases the bus right, a BACKN signal is output to the DMAC 600.
[0221]
Upon receiving the BACKN signal, the DMAC 600 outputs a DACK signal to the external request device 650.
[0222]
The DREQ cycle detection circuit 620 has the same circuit configuration as that of the sixth embodiment shown in FIG.
[0223]
Hereinafter, the operation of the DMA transfer apparatus configured as described above will be described.
[0224]
First, the bus load factor of the entire system is specified. In order to simplify the explanation, in this embodiment, the bus load factor of the entire system is set to 12% or less. Further, the DREQ signal generation interval of the external request device 650 is set to 5 μs, and the bus occupancy rate of one DMA transfer (for Word) is set to 10%. As a result, the time for occupying the bus by DMA becomes 500 ns.
[0225]
First, the table of FIG. 30 shows the relationship between the task names T1 to T10 on the program, the processing load, the corresponding mask time, and the DMAC load factor.
[0226]
As shown in FIG. 30, the present embodiment is a system that processes using tasks T1 to T10, and processes T1, T3, T5, and T7 among them in the order shown in the timing chart of FIG. Consider the case of going.
[0227]
FIG. 31 is a timing chart for explaining the operation of the DMA transfer apparatus.
[0228]
First, the DREQ signal is input in the task T1 section. In this case, when calculated from the table of FIG. 30, the total bus occupancy is 11% and does not exceed the occupancy of 12% of the present embodiment. Therefore, since it is not necessary to operate the mask circuit, the mask_en signal remains disabled and there is no problem. Therefore, the BREQ signal is generated with the same period as the DREQ signal.
[0229]
Next, when the DREQ signal is generated in the task T3 section, it is 13% when calculated from the table of FIG. 30 and the DMA bus occupation rate. A problem arises because the bus occupancy of this embodiment is 12% or less. To prevent this from happening, the CPU 800 controls the mask_en signal to be output at the timing shown in FIG. 31 when the process enters the task T3. At this time, the DREQ signal is masked by the mask_en signal and output to the CPU 800 as the BREQ signal. In response to this BREQ signal, the CPU 800 outputs a BACK signal to release the bus right. The DMA transfer sequence is executed by such exchanges.
[0230]
Next, a case where the DREQ signal is input in the task T5 section will be described.
[0231]
In this case, if the bus occupancy rate is calculated as in the case of task T3, it becomes 15%. This also does not satisfy the bus occupancy rate of 12% or less of the present embodiment, so in order to satisfy this condition, the mask time is set using the table of FIG.
[0232]
According to this table, in the case of T5, the mask_en enable time is 2.14 μs + 5 μs, and the bus occupation ratio is 12% or less. The CPU 800 controls mask_en so as to satisfy the mask time at this time.
[0233]
Similarly, also in the case of task T7, the mask time is set from the table of FIG. 30, the mask_en time is determined so that the bus occupancy rate set in this embodiment is 12% or less, and the CPU 800 satisfies the mask time. Control mask_en.
[0234]
As described above, in the DMA transfer apparatus according to the eighth embodiment, the CPU 800 has the task management function 810 for managing the processing task of the program, and holds the bus load of a predetermined system according to the processing load of the CPU. Then, because it was configured to control the mask time, calculate the bus occupancy rate when each task is operating in advance, set the limit value of the bus occupancy rate of the entire system from the calculated value, The CPU processing is effective and the DMA cycle can be performed at a value that does not exceed the upper limit of the bus occupancy rate, and the bus occupancy rate is reliably reduced to the bus occupancy value calculated in advance. effective.
[0235]
In this embodiment, the DMAC is controlled by the method of the second embodiment. However, as shown in the method of the first embodiment, the DMAC can be controlled by the operable external request device side. This can also be realized by controlling the BREQ signal in the DMAC by the method of the third embodiment.
[0236]
The mask time can be controlled by the CPU, or can be realized by providing a hardware timer in the mask circuit and setting the timer time from the CPU.
[0237]
Therefore, in a DMA transfer apparatus having such features, for example, in a PC (personal computer) peripheral device represented by a printer, the data transfer speed from the PC and the data processing speed of the peripheral device itself are mutually different. This is effective when high-speed processing is required and it is essential to avoid the failure of the system and to perform data transfer and CPU processing equally in time. Further, it can be used in all systems including data transfer by DMA centering on the CPU.
[0238]
In each of the above embodiments, a mask circuit or the like is installed in the external request device or the DMAC. However, this is an example, and the external request device or DMAC may be installed externally. The DMAC may be a dedicated DMA controller or a general-purpose DMA controller. In particular, when high speed is required, the DMAC may be configured using individual components such as a counter and a buffer.
[0239]
Furthermore, it goes without saying that the types, numbers, etc. of the registers, counters, various control circuits, etc. constituting the DMA transfer device are not limited to the above-described embodiments.
[0240]
【The invention's effect】
In the DMA transfer apparatus according to the present invention, the external request device or the DMA control unit is provided with mask means for masking the DREQ signal, and the mask means masks the DREQ signal to control the bus occupation state by DMA transfer. Therefore, when there are a plurality of external request devices, or when there are external request devices having a short DREQ signal generation period on the same bus, the bus occupancy rate by DMA can be reduced, and the bus is effectively used in terms of time. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a DMA transfer apparatus according to a first embodiment to which the present invention is applied.
FIG. 2 is a circuit diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer apparatus.
FIG. 3 is a circuit diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer apparatus.
FIG. 4 is a timing chart showing a DMA transfer operation of the DMA transfer apparatus.
FIG. 5 is a block diagram showing a configuration of a DMA transfer apparatus according to a second embodiment to which the present invention is applied.
FIG. 6 is a block diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer apparatus.
FIG. 7 is a diagram showing a detailed configuration inside a mask circuit of the DMA transfer apparatus.
FIG. 8 is a timing chart for explaining the operation of the DMA transfer apparatus.
FIG. 9 is a timing chart for explaining the DMAC arbitration operation of the DMA transfer apparatus;
FIG. 10 is a block diagram showing a configuration of a DMA transfer apparatus according to a third embodiment to which the present invention is applied.
FIG. 11 is a block diagram showing a configuration of a counter-equipped mask circuit of the DMA transfer apparatus.
FIG. 12 is a diagram showing a detailed configuration inside a mask circuit of the DMA transfer apparatus.
13 is a diagram showing a configuration from DMA request signals DREQ1, DREQ2, DREQ3 to BREQN signal generation in the DMA transfer apparatus.
FIG. 14 is a timing chart for explaining the operation of the DMA transfer apparatus;
FIG. 15 is a block diagram showing a configuration of a DMA transfer apparatus according to a fourth embodiment to which the present invention is applied.
FIG. 16 is a timing chart for explaining the operation of the DMA transfer apparatus;
FIG. 17 is a diagram showing a table for setting a mask time of the DMA transfer apparatus.
FIG. 18 is a block diagram showing a configuration of a DMA transfer apparatus according to a fifth embodiment to which the present invention is applied.
FIG. 19 is a table showing a relationship between a task name on the program of the DMA transfer apparatus and its processing load and a corresponding mask time.
FIG. 20 is a timing chart for explaining the operation of the DMA transfer apparatus.
FIG. 21 is a block diagram showing a configuration of a DMA transfer apparatus according to a sixth embodiment to which the present invention is applied.
FIG. 22 is a diagram showing a circuit configuration of a DREQ cycle detection circuit of the DMA transfer apparatus.
FIG. 23 is a timing chart showing the operation of the DREQ cycle detection circuit of the DMA transfer apparatus.
FIG. 24 is a timing chart for explaining the operation of the DMA transfer apparatus;
FIG. 25 is a block diagram showing a configuration of a DMA transfer apparatus according to a seventh embodiment to which the present invention is applied.
FIG. 26 is a diagram showing a circuit configuration of a BREQN signal cycle detection circuit of the DMA transfer apparatus.
FIG. 27 is a timing chart showing the operation of the BREQN signal cycle detection circuit of the DMA transfer apparatus.
FIG. 28 is a timing chart for explaining the operation of the DMA transfer apparatus;
FIG. 29 is a block diagram showing a configuration of a DMA transfer apparatus according to an eighth embodiment to which the present invention is applied.
FIG. 30 is a table showing a relationship between a task name on the program of the DMA transfer apparatus and its processing load and a corresponding mask time.
FIG. 31 is a timing chart for explaining the operation of the DMA transfer apparatus;
FIG. 32 is a block diagram showing a configuration of a conventional DMA transfer apparatus.
FIG. 33 is a timing chart conceptually showing arbitration timing of a conventional DMAC.
[Explanation of symbols]
100, 500, 800 CPU, 110, 200, 300, 400, 600, 700 DMAC (DMA controller), 111, 112, 240, 241, 351, 352, 353, 451, 452, 453, 751, 752 External requests Device, 113 external memory, 121, 122, 210, 220, 410, 610 DREQ signal mask circuit (mask means), 131 AND gate, 132 OR gate, 230 arbitration circuit, 211, 311 counter circuit, 212, 312 comparator, 213, 313 Mask circuit, 214 Mask signal generation circuit, 215, 315 OR gate, 310 Mask circuit with a counter (mask means), 316 DREQ signal arbitration circuit, 313 BREQ signal mask circuit, 314 Mask signal generation circuit, 510, 81 0 task management function (management means), 620 DREQ period detection circuit (DREQ period detection means), 621, 721 edge detection circuit, 622, 722 counter, 623, 723 data buffer, 710 BREQN signal mask circuit (mask means), 720 BREQN cycle detection circuit (BREQN cycle detection means)

Claims (1)

CPU,
External memory,
A plurality of external request devices each generating a data transfer request signal;
Independently of the operation of the CPU, a DMA controller for controlling DMA transfer between the external memory and the plurality of external request device,
A bus for connecting the CPU, the external memory, the plurality of external request devices, and the DMA control unit ;
The DMA controller,
When any of the previous SL plurality of external request device has generated the data transfer request signal, and outputs a bus release request signal requesting the release of the bus to the CPU, bus release permission signal from the CPU is returned are the, said generated the data transfer request signal and sent to an external request device data transfer request acknowledge signal, DMA transfer between said external request device and external memory to generate said data transfer request signal Means for controlling
And a counter for counting the previous SL DMA transfer masking time for masking a mask circuit that generates a bus request signal said data transfer request signal by masking the data transfer request signal to control the bus occupation by Mask means provided for each of the plurality of external request devices ;
Before SL on the basis of the bus request signal generated by any of said mask circuit masks means adjusts the output of the bus release request signal to the CPU by means for controlling the DMA transfer, the DMA transfer Mediation means for mediating ,
The CPU
Means for controlling the mask time in accordance with the number of the external request devices operable simultaneously;
Task management means for managing a processing load of a task processed by the CPU itself,
The task management means includes
Means for holding information relating to the mask time set for each task processed by the CPU;
Monitoring means for monitoring tasks currently being processed by the CPU;
Selecting means for selecting the mask time from means for holding information on the mask time according to the task being monitored by the monitoring means;
A DMA transfer apparatus comprising: setting means for setting the selected mask time as a mask time used by the mask circuit .

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