KR101214068B1 - Method and apparatus for controlling a bus in direct memory access controller - Google Patents

Abstract

The present invention relates to a direct memory access control device for determining bus occupancy characteristics for each channel and a method for determining bus occupancy characteristics for each channel in a computer system in which data is transmitted through channels by a bus.

To this end, the channel logic units generate occupancy request signals corresponding to each of the channels, and the control logic unit generates maintenance grant signals as many as the number of channels. AHB (Advanced High-performance Bus) master uses the occupancy request signals generated by the channel logic units and the hold acknowledgment signals generated by the control logic unit to assign bus occupancy characteristics to one of the types of occupied and non-occupied. The bus occupancy characteristic determination signal is determined.

DMA, AHB, Bus

Description

METHOD AND APPARATUS FOR CONTROLLING A BUS IN DIRECT MEMORY ACCESS CONTROLLER}

1 is a block diagram illustrating a general direct memory access (DMA) control unit.

2 is a block diagram showing an advanced high-performance bus (AHB) master in a general DMA controller;

3 is a timing diagram of a DMA-related AHB signal when the AHB control unit according to the related art performs bus occupancy type operation.

4 is a block diagram illustrating a DMA controller according to an exemplary embodiment of the present invention.

5 is a block diagram showing an AHB master in a DMA controller of the present invention.

6 is a timing diagram showing an operation in a DMA controller of the present invention.

The present invention relates to a computer system comprising a central processing unit and peripherals, and more particularly, to a bus control method and apparatus in a direct memory access (DMA) control unit in a computer system.

Central Processing Unit (CPU) In a computer system, the CPU is an essential component of the system that is connected to the peripheral devices of the system to perform data input, data output, and logic operations. . In computer systems, bus structures are used to control data transfer between peripherals. The movement of data in this bus structure is always under CPU control. As a result, when a large amount of data is moved, the CPU is very heavily loaded. Therefore, direct memory access (DMA) method is used to reduce CPU load. The DMA method is a method of directly transferring data through a bus without passing through a CPU when moving data.

Next, an operation method of a DMA controller using an advanced high-performance bus (AHB) in the bus structure will be described.

1 is a block diagram illustrating a general DMA controller 100.

Referring to FIG. 1, the DMA controller 100 includes an AHB slave interface 101, a DMA request and response interface 103, an interrupt request 105, The control logic unit includes a control logic and register bank 107, channel logic and channel register banks 109 and 111 for each channel, and an AHB master 120. The functional block is already known and will be omitted herein. The AHB master 120 converts an internally processed DMA operation into an AHB master signal and connects the bus to the bus. The operation of the AHB master 120 directly affects bus occupancy characteristics. The control logic unit 107 is a part for controlling the operation of the AHB master 120.

The AHB master 120 performs an operation for obtaining permission to transmit using the AHB bus.

In the case of Advanced High-performance Bus (AHB), when one master occupies the bus, the other master cannot use the bus. In the prior art, determining the bus occupancy characteristic of the AHB master 120 is an Arbitration Priority Signal called 'IArbPriority' in the AHB master 120. If the IArbPriority is '1', the DMA operation is performed while occupying the bus exclusively.

Here, the occupancy type is a case where other masters cannot use the DMA operation, and the non-occupation type indicates a case where other masters can use the interrupt even during the DMA operation.

For example, in the case of the existing DMA controller 100 such as PrimeCell PL081, the characteristics of bus occupancy are different for each channel, so that a channel having a characteristic suitable for the purpose is selected and used.

In the case of channel0, while the DMA control unit 100 is transferring data, another master such as a CPU cannot use the bus and operates in an occupied type. In the case of channel1, it is possible for another master such as a CPU to use the bus while the DMA control unit 100 transfers data.

Channel0 and Channel1 output the signals '1' such as Ch0ReqM and Ch1ReqM, respectively, to request the DMA operation to the AHB master 100. The implementation operation of the AHB master 120 will be described with reference to FIG. 2. FIG. 2 is a block diagram illustrating the AHB master 120 of FIG. 1, showing an example.

Referring to FIG. 2, the AHB master 120 is composed of two interleavers 121 and 125 and one end gate 123. In this process, when channel0 and channel1 request the operation together, channel0 has a high priority, so the request of channel0 is transmitted, which indicates that CombCh1Gnt is '1'.

Referring to the process of determining the occupancy characteristics of the bus, when Ch0ReqM is '1', the AND gate 123 is inputted '0' unconditionally by the first inverter 121, so that CombCh1Gnt is independent of the value of Ch1ReqM. It has a value of '0', and thus IArbPriority becomes '1' due to the second inverter 125, so that the DMA operation is performed while occupying the bus exclusively.

Next, when Ch0ReqM is '0' and Ch1ReqM is '1', CombCh1Gnt has a value of '1' by the AND gate 123. Accordingly, IArbPriority has a value of '0' by the second inverter 125 so that the AHB master 120 operates in a bus non-occupancy type.

3 is a timing diagram of a DMA-related AHB signal when the AHB control unit 100 according to the related art performs a bus occupancy type operation.

Referring to FIG. 3, each signal will be described. HCLK is a bus synchronization clock of an AHB connected to a DMA master port, HBUSREQ is a signal requesting permission to use a bus to operate as an AHB master, and HGRANT is a bus used from a bus Arbiter. Signal to be granted. In addition, HTRANS is a control signal indicating the AHB transaction characteristics, HADDR is a signal indicating the AHB address.

Referring to FIG. 3, it can be seen that the DMA controller 100 receives HGRANT 1 by continuously maintaining HBUSREQ 1 while operating as the AHB master 120, so that other masters cannot use the bus.

As can be seen from the timing diagram of FIG. 3, the conventional DMA controller 100 has a problem in that it is impossible to change the characteristics of the channel according to the situation because the bus occupancy characteristics are fixed for each channel. For example, it is not possible to use both channels as bus occupied or non-bus occupied.

Accordingly, an object of the present invention is to provide a method and apparatus for fluidly controlling bus resources in a DMA controller.

Another object of the present invention is to provide a method and apparatus for controlling bus resources in software in a DMA controller.

A direct memory access control apparatus for determining bus occupancy characteristics for each channel in a computer system in which data transmission is performed through channels by a bus according to the present invention for achieving the above-mentioned, includes an occupancy request signal corresponding to each of the channels. Channel logic units for generating (Ch0ReqM, Ch1ReqM), control logic unit for generating hold grant signals (HoldGrant0, HoldGrant1) as many as the number of channels, and occupancy request signals generated by the channel logic units ( A bus occupancy characteristic determination signal (IArbPriority) for determining a bus occupancy characteristic as one of the occupied type and the non-occupied type based on Ch0ReqM and Ch1ReqM) and the holding grant signals HoldGrant0 and HoldGrant1 generated by the control logic unit. Includes an advanced high-performance bus (AHB) master that occurs.

In a computer system in which data is transmitted through channels by a bus according to the present invention for determining the above, a method of directly determining a bus occupancy characteristic of each channel by a memory access control apparatus includes: corresponding to each of the channels. Generating request signals Ch0ReqM and Ch1ReqM, generating hold grant signals HoldGrant0 and HoldGrant1 as many as the number of channels, and generating the occupancy request signals Ch0ReqM and Ch1ReqM. And generating a bus occupancy characteristic determination signal (IArbPriority) that determines the bus occupancy characteristic as one of an occupied type and an unoccupied type based on the retained acknowledgment signals HoldGrant0 and HoldGrant1.

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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that the same configurations of the drawings denote the same reference numerals as possible whenever possible. Specific details are set forth in the following description, which is provided to aid a more general understanding of the invention. And in describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention is characterized in that the occupancy characteristics of the bus can be flexibly controlled to be used by other external masters even when the bus is occupied by the existing DMA controller. Next, a description will be given of the DMA control unit according to the present invention and a control method according to the present invention with reference to the accompanying drawings.

4 is a block diagram illustrating a DMA controller 400 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the DMA controller 400 generates a control signal in software so that the control logic unit 407 can control various types of occupation. In the following description, the control signals generated by the control logic unit 407 will be referred to as HoldGrant0 and HoldGrant1. In addition, the description of each functional block is not the gist of the present invention, detailed description thereof will be omitted.

Table 1 below shows an example of controlling the occupancy characteristics by the control signal in the DMA controller 400 of the present invention.

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Referring to Table 1, by adding the control signals HoldGrant0 and HoldGrant1, the bus occupancy characteristics can be variously configured for each channel.

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5 shows an example of a detailed configuration of the AHB master 420 constituting the DMA control unit 400 of the present invention. On the other hand, the specific operation of the AHB master 420 will be described by the bus occupancy characteristics for each channel illustrated in Table 1.

Referring to FIG. 5, the AHB master 420 is composed of three inverters 421, 425, and 429, three AND gates 423, 427, and 431, and one Noah gate 433. The logic circuit constituting the AHB master 420 is merely proposed as an example, and it will be apparent that various implementations may be made by other configurations.

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In the present invention, the signal output from the AHB master 420 to finally determine the occupancy characteristic is IArbPriority. For this purpose, the control logic unit 407 includes a register that can be set by software. The register included in the control logic unit 407 generates signals of HoldGrant0 and HoldGrant1. The HoldGrant0 and HoldGrant1 signals generated by the registers included in the control logic unit 407 are logically operated by the AHB master 420 with the Ch0ReqM and Ch1ReqM signals to output IArbPriority. Therefore, the user can arbitrarily adjust the IArbPriority to be output by the AHB master 420 by adjusting the HoldGrant0 and HoldGrant1 signals to be generated by the control logic unit 407.

For example, first, if the value of HoldGrant0 is '1' and the value of Hold Grant1 is '1', if the value of Ch0ReqM is '1', the output value of the first inverter 421 will always be '0' so that Ch1ReqM Regardless of the value, the value of CombCh0Gnt is always '0'. Accordingly, the values input to the second and gate 427 are all '1'. This is because the output value of the CombCh0Gnt passes through the second inverter 425. Since the output value of the second end gate 427 is always '1', the value of IArbPriority, which is the output value of the Noah gate 433, is always '1', so that the bus occupancy characteristic is determined to be occupied. Under the above conditions, if the value of Ch0ReqM is '0' and the value of Ch1ReqM is '1', the value of CombCh1Gnt is '1' because it is an output signal of the first and gate 423. Accordingly, the output signal of the second end gate 427 becomes '0'. However, since the value of CombCh1Gnt is '0' and both input signals of the third and gate are '1', the output signal is '1'. Therefore, the IArbPriority value, which is the output signal of the NOR gate 433, outputs '1', so that the bus occupancy characteristic is determined to be the occupation type.

For example, secondly, when the HoldGrant0 value is '0' and the Hold Grant1 value is '1', the output value of the second end gate 427 is always '0' because the HoldGrant0 value is '0'. Here, if the value of Ch0ReqM is '1', the input value of the third and gate 431 is '0' by the third inverter 429. Accordingly, the IArbPriority value, which is the output value of the NOR gate 433, becomes '0' regardless of the CombCh1Gnt value, so that the bus occupancy characteristic is determined as the non-occupying type. If the Ch0ReqM value is '0' and the Ch1ReqM value is '1' under the above conditions, the value of CombCh0Gnt becomes '0' and the output value of the third inverter 429 becomes '1'. Then, since the input values of the third and gates 431 are all '1', the IArbPriority value, which is the output value of the Noah gate 433, becomes 1, so that the bus occupancy characteristic is determined as the occupation type.

For example, when HoldGrant0 is '1' and HoldGrant1 is '0', if the value of Ch0ReqM is '1', CombCh1Gnt is an output value of the first and gate 423 by the first inverter 421. The value is '0'. The CombCh1Gnt value is input to the second end gate 427 via the second inverter 425. Since the value of HoldGrant0 is '1', the output value of the second and gate 427 becomes '1'. Therefore, the IArbPriority value, which is the output value of the NOR gate 433, becomes '1', so that the bus occupancy characteristic is determined as the occupation type. If the value of Ch0ReqM is '0' and the value of Ch1ReqM is '1' under the above conditions, the input values of the first and gates 423 are all '1' and the value of CombCh0Gnt is '1'. The CombCh0Gnt value is '0' by the second inverter 425 and the output value of the second and gate 427 is '0'. In addition, since the third end gate 431 receives a HoldGrant1 value, the third end gate 431 always outputs a '0' value. Accordingly, the value of IArbPriority, which is the output signal of the NOR gate 433, becomes '0', so that the bus occupancy characteristic is determined as the non-occupied type.

For example, if the value of HoldGrant0 is '0' and HoldGrant1 is '0', the value of IArbPriority, which is the output signal of Noah gate 433, is always 0, regardless of the values of Ch0ReqM and Ch1ReqM. Occupancy characteristics are determined by non-occupation type. This is because when the value of HoldGrant0 is '0' and the value of HoldGrant1 is '0', output signals of the second and third end gates 427 and 431 are always '0', respectively.

As described above, the occupancy characteristic of the bus can be set for each channel according to the values of HoldGrant0 and HoldGrant1, so that the occupancy and non-occupancy types can be operated for the channel 0 and the channel 1, respectively.

Fig. 6 is a timing diagram showing an example of operation in the DMA control section 400 of the present invention, which is set to non-occupied type and operated.

Referring to FIG. 6, whenever the DMA reads and writes data, the HGRANT is changed to 0 by changing HBUSREQ to '0' once. At this moment DMA returns the bus's right to use. If another master requests the use of the bus at this moment, the bus can be transferred to another master. However, if there is no other master requesting the bus license, as shown in FIG. 6, the DMA acquires the bus license again and continues the remaining DMA process.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

As described above, according to the present invention, the DMA controller can support various types of bus occupancy so that the bus resource can be more efficiently used in the system to which the present invention is applied.

Claims (6)

A direct memory access control apparatus for determining bus occupancy characteristics for each channel in a computer system in which data is transmitted through channels by a bus, Channel logic units generating occupancy request signals Ch0ReqM and Ch1ReqM corresponding to each of the channels; A control logic section for generating hold grant signals HoldGrant0 and HoldGrant1 as many as the number of channels; Based on the occupancy request signals (Ch0ReqM, Ch1ReqM) generated by the channel logic units and the hold grant signals (HoldGrant0, HoldGrant1) generated by the control logic unit, the bus occupancy characteristic may be one of the occupation type and the non-occupancy type. A direct memory access control device that includes an Advanced High-performance Bus (AHB) master that generates a bus occupancy characteristic determination signal (IArbPriority) that is determined by type. The method of claim 1, wherein the AHB master, The bus occupancy characteristic determination signal IARrbPriority is performed by performing logic operation on the occupancy request signals Ch0ReqM and Ch1ReqM generated by the channel logic units and the hold grant signals HoldGrant0 and HoldGrant1 generated by the control logic unit. And a combination of logic gates for generating a direct memory access control device. 3. The method of claim 2, And the combination of logic gates is configured to generate the bus occupancy characteristic determination signal (IArbPriority) according to Table 2 below. <Table 2>

A method of determining a bus occupancy characteristic of each channel by a direct memory access control device in a computer system in which data is transmitted through channels by a bus, Generating occupancy request signals Ch0ReqM and Ch1ReqM corresponding to each of the channels; Generating as many hold grant signals HoldGrant0 and HoldGrant1 as the number of channels; A bus occupancy characteristic determination signal for determining a bus occupancy characteristic as one of an occupied type and an unoccupied type based on the occupied request signals Ch0ReqM and Ch1ReqM and the generated hold grant signals HoldGrant0 and HoldGrant1. A method of determining bus occupancy characteristics including generating IArbPriority. 5. The method of claim 4, The bus occupancy characteristic determination signal IArbPriority is generated by a logic operation inputting the occupancy request signals Ch0ReqM and Ch1ReqM generated and the hold grant signals HoldGrant0 and HoldGrant1 generated by the control logic unit. Bus occupancy characteristics determination method characterized in that. 6. The method of claim 5, And a logical operation for generating the bus occupancy characteristic determination signal (IArbPriority) is performed by Table 3 below. <Table 3>

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