JPS63214860A - Dma device - Google Patents

Abstract

PURPOSE:To avoid the deterioration in the performance of the entire controller by adopting the constitution such that a DMA operating period of a DMA (direct memory access) controller is to be changed. CONSTITUTION:When a signal DMAREQ representing a DMA request is made active by a bus adaptor (not shown), a clock signal CLK is inputted to a down- counter 53 via an AND gate 55 and counted down. As result, when the count of the counter 53 reaches 0, sine a signal OUTZ reaches an H level, the DMAREQ is sent to a DMA controller 47 via an AND gate 56 to attain the DMA operation. Then the operating period of the DMAC 47 is changed by changing properly the data set to the counter 53 in response to the processing state of the microprocessor itself to avoid the reduction in the performance of the entire controller.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is provided in a control device with a built-in microprocessor connected to a high-speed system bus, and has a DMA (direct memory access) controller. Equipped with DMA
Regarding equipment.

(Prior art) In recent years, even relatively small-scale computer systems have a plurality of microprocessors under a high-performance central processing unit (hereinafter referred to as CPU), and it is becoming increasingly difficult to organically combine these microprocessors. Many are aimed at improving performance. An example of this type of system is shown in FIG. In the figure, 11 is a high-speed CPU, 12 is a magnetic disk controller, 13 is a floppy disk υ11111 device, 14 is a communication line controller, 15 is a main storage device, and 16 is an input/output unit.
1JIII device.

Each of these devices is connected to a system bus 17.

Since this system bus 11 affects the performance of the computer system, it has a configuration that allows high-speed data transfer according to the requests of each device (for example, a configuration that allows 32-bit or 64-bit parallel transfer). ing.

Now, each of the above control devices connected to the system bus 11 generally uses the internal bus of the microprocessor to perform DM control.
It is equipped with a DMA controller that performs A transfer. The microprocessor mentioned above generally has an 8-bit or 16-bit configuration, and its processing speed is high-speed CP LJ.
It is slow compared to 11. Therefore, if a data transfer request is received from the system bus 17 while a control device is controlling a device under its control,
There is a problem in that the load on the microprocessor in the control device increases, resulting in poor device control. This problem will be explained using the communication line tllJIm device 14 as an example, with reference to the block diagram of FIG.

In FIG. 5, 2) is a microprocessor (hereinafter referred to as μP) that controls the entire communication line control device 14. It is now assumed that μP2) is performing multi-processing transmission/reception services to the line control units 23-1 to 23-4 via the internal bus 22. For example, the line control unit 23-
1 sends a message to the bus adapter 25 connecting the system bus 17 and the internal bus 22 in order to read data to be transferred from the host II device 15 connected to the system bus 17 to the line L1 into the local memory 24. information is set, and the DMA controller (hereinafter referred to as DMAC) 27 that constitutes the DMA device ff1f26 is activated. At the same time, the other line control units 23-2 to 23-4 control the lines 12 to L.
Controls reception of data from 4.゛Now then, DMAC
27 is activated, since the system bus 17 is high speed, requests to use the bus for the operation of the DMAC 27 are frequently generated for the μP 2). In this case, μP2)
However, there was a problem that sufficient service could not be provided to the line control units 23-2 to 23-4. Conventionally, in order to solve this type of problem, the amount of data transferred per activation of the DMAC 27 was limited, and the system bus 11
When sending and receiving data with the line l1III section 23-1~2
It was necessary to avoid serving 3-4.

However, in this method, the line aim sections 23-1 to 23-
There was a problem that caused a decrease in the efficiency of 4. This kind of problem is
The same applies to control devices other than the WAIIIg device, such as the input/output control device 1116.

(Problems to be Solved by the Invention) As mentioned above, conventionally, when data transfer with a high-speed system bus is required, a DMA controller (DMA
Since bus usage requests frequently occur from C> to the microprocessor (μP) that forms the core of the control device equipped with the controller, the load on this microprocessor increases and the performance of the entire control device decreases. .

The present invention has been made in view of the above circumstances, and an object thereof is to provide a DMA device that can vary the DMA operation cycle and thereby prevent performance deterioration of a control device connected to a high-speed system bus.

[Structure of the Invention] (Means and Effects for Solving Problems) According to the present invention, a DMA device is provided in a control device with a built-in microprocessor (μP) connected to a high-speed system bus. This DMA device includes a register means in which arbitrary time data is set, a count means that is activated by an external DMA request and counts only the value indicated by the time data set in the register means, and a 1-circuit. and is provided. This gate circuit allows input of an externally applied DMA request to the MA controller (DMAC) when the counting means finishes counting. According to the above configuration, the DMA controller
The operating cycle can be varied by time data set in the register means.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings, taking a DMA device provided in a communication line control device as an example. Note that the same parts as in FIGS. 4 and 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows a block configuration of a DMA device, and FIG. 2 shows a block configuration of a communication circuit Ill control device equipped with the DMA device of FIG. In FIG. 2, 34 is a communication line control device corresponding to the communication line control device 14 shown in FIGS. 4 and 5. In FIG. It is assumed that this communication line control device 34 is connected to the system bus 17 shown in FIG. 4 instead of the communication line control device 14. The communication line system a unit @34 includes a μP (microprocessor) which controls the entire unit 34 (corresponding to μP2 shown in FIG. 5). The bus (internal bus) 42 of this μP 41 includes line control units 23-1 to 23-4, a local memory 24,
and a bus adapter 25 are connected. Also connected to the internal bus 42 is a DMA device 46 that is directly related to the present invention. The DMA device 46 is a DMA device shown in FIG.
DMAC4 equivalent to AC (DMA controller) 27
In addition to γ, an operation cycle variable circuit 48 for varying the DMA operation cycle of the DMAC 47 is provided. In this embodiment, DMAC 47 is a separate integrated circuit element;
It is also possible to incorporate the variable operation cycle circuit 48 into the same element.

As shown in FIG. 1, the operation cycle variable circuit 48 of the DMA device 46 includes a register 51 connected to the internal bus 42 and for holding data for an arbitrary time, and a response signal BLJ to the bus use request signal BLISREQ from the DMAC 47.
Monostable multivibrator (hereinafter referred to as monomulti) 52 that generates one pulse in response to the rise of SACK
and register 5 according to the output signal of this monomulti 52.
Load the retained data of 1 and use the AND gate 55, which will be described later.
The down counter 53 performs a down-count operation using the output signal from the clock signal as a clock signal. The variable operation cycle circuit 48 further controls the level of the output zero signal 0UTZ, which is output from the output terminal OZ of the down counter 53 and becomes "H" level < H+ah level during the period when the count value of the down counter 53 is 0 (zero). Inverting inverter (
1) DMA from the inverter 54 and the output signal of the inverter 54 and the bus adapter 25 in FIG. lReimbursement DMA
An AND gate (AND
) 55, and an AND gate (AND) 56 for controlling the output of the signal DMAREQ to the DMAC 47 in accordance with the output zero signal 0UTZ.

Next, the operation of the configurations shown in FIGS. 1 and 2 will be explained with reference to the timing chart shown in FIG. 3 as appropriate.

Now, while the down counter 53 of the variable operation cycle circuit 48 is loaded with time data other than 0, the bus adapter 25 requests data transfer with the system bus 17 (to be more specific, the system Bus adapter 25° local memory 24 for data transfer with bus 17
DM, a signal indicating a DMA request (for data transfer between
Assume that AREQ is set to "H" level (active). When the content of the down counter 53 is not 0, the output zero signal 0LJTZ output from its output terminal oz is at the "high" level. This signal 0tJTZ is inverted in level by an inverter 54 and supplied to an AND gate 55, and is also supplied as is to an AND gate 56. The AND gate 56 is turned off when the signal 0LJTZ is at the "low" level, and the signal DMARE is turned off.
Q is prohibited from being transmitted to the DMAC 47. On the other hand, in the AND gate 55, the signal 0LJTZ is at the "L" level (that is, the output signal of the inverter 54 is at the H" level).
, and is turned on only while the signal DMAREQ is at the "H" level.

As a result, the clock signal CLK supplied to the AND gate 55 is outputted from the same gate 55 as is, as shown in FIG. 3, and supplied to the down counter 53. The down counter 53 receives a clock signal C output from the AND gate 55 while the AND gate 55 is in the on state.
A down count operation is performed by LK.

Eventually, when the count value of the down counter 53 becomes 0,
As shown in FIG. 3, the output zero signal 0UTZ transitions to the "H" level. When the signal 0tJTZ goes to "H" level,
Since the output signal of the inverter 54 becomes "L" level, the AND gate 55 is turned off and output of the clock signal CLK to the down counter 53 is prohibited. As a result, the counting operation of the down counter 53 is stopped.

Further, when the signal 0LJTZ goes to H" level, the AND gate 56 turns on and transmits the signal DMAREQ outputted from the bus adapter 25 as it is to the DMAC 47.

As a result, the DMAC 47 is activated, and the bus use request signal BLIS is issued to request the use (release request) of the internal bus 42.
Set REQ to “L” level (active). That is, according to this embodiment, the signal DMAR is transmitted from the bus adapter 25.
Even if EQ is issued, the down counter 53 is
Until the number of pulses of the discount signal CLK indicated by the time data loaded in
C47 activation is maintained.

Bus use request signal BLIS output from DMAC47
REQ is transmitted to the μP 41 via the internal bus 42 (one line of the internal control bus).

When the μP 41 detects that the signal BLISREQ has gone to the "L" level, it determines a request to release the internal bus 42, and if it is possible to release the internal bus 42, it sends a response signal BUSACK as an acknowledgment response to the signal @BUSREQ as shown in FIG. “L”
(active) to release the internal bus 42.

The signal B and USACK are transmitted to the DMAC 47 and the monomulti 52 in the variable operation cycle circuit 48 via the internal bus 42 (one line of the control bus therein).

When the signal BUSACK reaches the "LIT" level, the DMAC 47 executes data transfer (DMA transfer) between the bus adapter 25 and the local memory 24 using the internal bus 42. Then, as shown in FIG. 3, the bus use request signal BUS
REQ is returned to "H level" and the right to use the internal bus 42 is set to μ.
Return to P41. In μP41, the signal BUSREQ is “H”
When detecting the level, the response signal BUSACK is returned to the "H" level as shown in FIG. signal BIJ
When SACK changes to the "l-1" level, one pulse is output from the monomulti 52 as shown in FIG. The pulse signal from this monomulti 52 is guided to the load terminal of the down counter 53, and thereby the register 51
The time data set in is loaded into the down counter 53. Thereafter, the same operation as above is repeated.

In this repetition, the μP 41 appropriately changes the setting data in the register 51 according to its own processing state. By doing this, the operating cycle of the DMAC 47 can be varied according to the processing state (i.e., the degree of load) of the μP 41, so that, for example, the data in the main storage device 15 shown in FIG. Even if a DMA transfer operation by the DMAC 47 is required for transfer to the line L1 via the line L1, it is possible to prevent service to the line II control units 23-2 to 23-4 from deteriorating. Note that the operations in the time periods indicated by diagonal lines in the timing chart of FIG. 3 are the same as those in the conventional DMA operation, and are not directly related to the present invention, so a description thereof will be omitted.

The above has described the DMA device 46 provided in the communication line 11J II @ W 34, but this invention can be applied to other devices such as input/output control devices as long as the tiII 1ml device is connected to the system bus 17 and has a DMA device. It can be similarly applied to other control devices. Furthermore, the present invention can be applied to a control device equipped with a plurality of DMA devices.

[Effects of the Invention] As detailed above, according to the present invention, the cycle of the DMA operation required for data transfer with a high-speed system bus in a control device with a built-in microprocessor can be varied. It is possible to prevent a significant increase in the load on the microprocessor due to frequent bus use requests from the DMAC (DMAC), and the performance of the control device can be fully demonstrated.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block configuration diagram of a DMA device according to an embodiment of the present invention, FIG. 2 is a block configuration diagram showing a communication line control device equipped with the DMA device of FIG. 1, and FIG. 3 is a timing chart for explaining the operation, FIG. 4 is a block diagram showing the basic configuration of the computer system, and FIG. 5 is a block diagram of a conventional communication line control device. 11... CPU, 15... Main storage device, 11...
System bus, 25...Bus adapter, 41...μ
P (microprocessor), 42...internal bus, 46
DMA device, 41 DMAC (DMA controller), 48 variable operation cycle circuit, 51 register, 53 down counter, 55, 56...
And gate. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5

Claims (2)

[Claims] (1) A DMA device installed in a control device with a built-in microprocessor connected to a high-speed system bus,
In a DMA device equipped with a DMA controller that issues a bus usage request to the microprocessor when an MA request is input and performs a DMA operation when the usage request is accepted, register means for setting arbitrary time data; a counting means that is activated when the DMA request is applied from the outside and counts only the value indicated by the time data set in the register means; A DMA device comprising: a gate circuit that permits input of a request to the DMA controller. (2) Setting the above time data to the above register means,
2. The DMA device according to claim 1, wherein said DMA device is operated by said microprocessor.