JP2556290B2 - Bus arbitration device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer in a system using a microprocessor, and more particularly to a bus arbitration device for arbitrating bus use requests from a plurality of input / output devices.

[0002]

2. Description of the Related Art In a conventional system using a microprocessor, when each of a plurality of input / output devices connected to a bus attempts to transfer data, the input / output device attempting the transfer is a processor. A bus use request is issued to, and the actual data transfer is performed after the bus use permission is obtained from the processor. Since only one I / O device can transfer data at the same time, when multiple I / O devices issue bus use requests at almost the same time, the I / O device is the one other than the one that received the first permission. Will have to wait until the bus permission is obtained.

FIG. 3 shows a conventional system having a plurality of inputs and outputs.
The operation when the bus use requests from the power system overlap.
It is a timing chart shown. All negative logic in this figure
Indicated by. Here are two I / O devices A and B?
These figures show the case where the bus use requests overlap. By the way
In general, I / O devices are
Is not configured to perform the actual data transfer
Yes. That is, the illustrated D _A, D_BThere is a delay time shown in
I do. From permission to use until data transfer starts
The delay time is relatively large, and the bus is
Since it is not used in
This is a major cause of lowering the sales. Also, the actual day
Data may still occupy the bus even after the
This also causes a decrease in throughput.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus arbitration device capable of improving the effective use rate of the bus when the bus use requests overlap each other and improving the throughput of the entire system. is there.

[0005]

A bus arbitration device of the present invention comprises a processor, a bus connected to the processor, and a plurality of input / output devices connected to the bus for performing data transfer via the bus. In a bus arbitration device in a system provided with, when a bus use request from the input / output device is received, a bus use right is requested to the processor, and bus use requests from two or more input / output devices overlap. In this case, a bus use request control unit that determines the acceptance order of the bus use request and outputs the device number of the input / output device with which the bus use request overlaps and the acceptance order, and A storage unit that stores information regarding the occupied time of the bus of the input / output device and the time required for the actual data transfer; Enter the number and the acceptance precedence, by referring to the storage means reads the information input and output device corresponding to the device number and the input, starts timing upon receiving the bus grant signal from said processor,
The time after the bus occupancy time of the I / O device with the highest acceptance order minus the time from when the bus of the I / O device with the next highest acceptance order is occupied until the actual data transfer is performed Counter means for outputting a timing end signal of 1 and outputting a second timing end signal after the bus occupancy time of the input / output device with the highest reception order has elapsed from the start of the timing, and bus use request control When the device number and the reception order are input from the means, and the bus use permission signal from the processor is received, the bus for the input / output device whose reception order is the highest until the second timing end signal is received. Bus use permission control means for validating the use permission signal and validating the bus use permission signal for the input / output device having the next highest reception order when the first timing end signal is received. .

[0006]

In the second order of acceptance, the actual data transfer from the second order of input / output device starts immediately after the end of the actual data transfer from the first order of input / output device. Since the bus use permission signal for the I / O device is issued ahead of time, the actual data transfer from each I / O device can be performed continuously, the bus usage rate improves, and the throughput of the entire system improves. To do.

The present invention is a so-called DMA (Direct Memory Access) in which a memory is connected to a bus and an input / output device directly transfers data to this memory without passing through a processor.
Is also preferably applied to. Further, the information stored in the storage means can be set from outside the storage means.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a bus arbitration device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the bus arbitration device.

The bus 2 has a processor 1, a memory 3 and an n.
Number of input and output devices 4 ₁ to 4 _n are connected. More this device, a storage unit for a bus use request control unit 5 for receiving the bus request signals REQ ₁ ~REQ _n from output devices 4 ₁ to 4 _n, the necessary information is set from the outside and stores it 6 and first and second timing end signals 9 described later
The counter unit 7 that outputs ₁ , 92 and each input / output device 41 to
Bus grant control unit 8 issues a bus grant signal ACK ₁ ~ACK _n is provided for 4 _n.

The bus use request control unit 5 includes an input / output device 4₁
~ 4_nBus request signal REQ from ₁~ REQ_nReceive
Request the bus right to the processor 1 when
Bus use permission signal REQ₀To output
Has been established. Then, the bus from two or more input / output devices
Bus usage requests overlap, these bus usage requests
The reception order of the
Priority / device number indicating the device number and reception order
The signal 93 is output.

The storage unit 6 stores, for each of the input / output devices 4 ₁ to 4 _n , information regarding the bus occupation time of the input / output device and the time required for actual data transfer. Typically, the value of the bus occupation time and the value of the time (delay time) from the reception of the bus use permission signal to the start of the actual data transfer are stored.

The bus use permission signal ACK ₀ from the processor 1 and the priority / device number signal 93 from the bus use request control unit 5 are input to the counter unit 7. The counter unit 7 reads out from the storage unit 6 the information of the input / output device corresponding to the device number designated by the priority / device number signal 93. Then, the counter unit 7 starts timing from the time when the bus use permission signal ACK ₀ from the processor 1 is received, and the input / output device having the next highest reception priority is the bus occupancy time of the I / O device having the highest reception priority. After the lapse of the time obtained by subtracting the delay time of, the first time measurement end signal 91 is output, and
After the bus occupancy time of the I / O device with the highest order of acceptance has elapsed from the start of the above timing, the second timing end signal 92
Is configured to output.

The bus use permission control unit 8 includes a processor 1
A bus grant signal ACK ₀ from, and priority / device number signal 93 from the bus request control unit 5, and the first and second count end signal 91, 92 from the counter portion 7 is inputted. When the bus use request control unit 8 receives the bus use permission signal ACK ₀ from the processor 1, the bus use request control unit 8 uses the bus for the input / output device having the highest reception order until it receives the second timing end signal 92. When the permission signal is validated and the first clocking end signal 91 is received, the bus use permission signal for the input / output device having the next highest reception priority is validated.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG. In FIG. 2, all operations are shown in negative logic. Here, a case where bus use requests overlap when the input / output devices 4 ₁ and 4 ₂ transfer data to the memory 3 will be described as an example. Here, it is assumed that towards the bus use request from the output device 4 ₁ is accepted earlier.

The bus use request control unit 5 includes an input / output device 4 ₁ ,
4 receives the bus request signal REQ _1, REQ ₂ from _2,
The bus use request signal REQ ₀ is output to the processor 1. Also, the acceptance order of the bus use requests from these input / output devices 4 ₁ and 4 ₂ is determined, and the device number and acceptance order of these input / output devices 4 ₁ and 4 ₂ are treated as a priority / device number signal 93 by a counter section. 7 and the bus use permission control unit 8. At this point, the counter unit 7 reads out from the storage unit 6 information about the bus occupation time for the input / output devices 4 ₁ and 4 ₂ and the time required for actual data transfer.

Receiving the bus use request signal REQ ₀ , the processor 1 performs the necessary processing and then issues the bus use permission signal ACK ₀ . This bus use permission signal ACK ₀
By receiving the, the counter section 7 starts timing for the first and second timing end signals 91 and 92.
The output device 4 output a value obtained by subtracting the actual data transfer time of the input and output device 4 _{2 2} bus occupation time 4 ₂
When the delay time of T _A, from the start of time measurement, (input-output device 4 _first bus occupation time T _B) - a first count end signal when the (input-output device 4 _second delay time T _A) has elapsed 91 outputs, also outputs the second count end signal 92 at the time of the lapse of the bus occupation time T _B of the input and output device 4 ₁ from the start of counting.

On the other hand, the bus use permission control unit 8 is
Bus use permission signal ACK from server 1 ₀When you receive
I / O that has the highest priority and should be allowed to transfer data first
Force device (in this case, input / output device 4₁) To use the bus
Permission signal ACK₁Is sent. And the counter section 7
When the first time end signal 91 from
The controllable unit 8 controls the input / output device 4 having the higher priority.₁To
Bus permission signal ACK₁Priority remains active
Lower input / output device 4₂Use permission signal A to
CK₂To enable. At this point, the first
Output device 4₁Is transferring data to memory 3 or
The other input / output device 4 is in the preparation period for ₂Is day
Transition to the period for preparing the data transfer.

Then, the bus use permission control section 8 receives the second timing end signal 92, and invalidates the bus use permission signal ACK ₁ for the input / output device 4 _{1 which is} permitted _first .
At this point, the input / output device 41 ₁ has just finished the data transfer, and the other input / output device 41 ₂ is about to start the data transfer after the delay time T _A has elapsed. Therefore, by continuously enabling the bus use request signal REQ ₀ from the bus use request control unit 5 to the processor 1, data transfer of the input / output device 4 ₂ is continuously performed without opening the bus 2. Become.

[0019]

As described above, according to the present invention, when bus use requests are generated almost at the same time, after issuing the bus use permission signal to the I / O device having the higher priority,
By issuing the bus use permission signal to the I / O device with the lower priority, ahead of time, the waiting time for the I / O device from obtaining the bus use right to transferring the actual data can be reduced. Since this is apparently unnecessary, the time required for the input / output device to occupy the bus can be reduced, the effective utilization rate of the bus is improved, and the throughput of the entire system is improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a bus arbitration device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device of FIG.

FIG. 3 is a timing chart showing the operation of a conventional bus arbitration device.

[Explanation of symbols]

1 processor 2 bus 3 memory 4 ₁ to 4 _n input / output device 5 bus use request control unit 6 storage unit 7 counting unit 8 bus use permission control unit

Claims (3)

(57) [Claims] 1. A bus arbitration device in a system comprising: a processor; a bus connected to the processor; and a plurality of input / output devices connected to the bus for transferring data via the bus. Request bus usage right to the processor when receiving a bus usage request from
A bus that determines the acceptance order of the bus use requests when the bus use requests from two or more I / O devices overlap, and outputs the device number and the acceptance order of the I / O devices that overlap the bus use requests. A use request control means; a storage means for storing, for each of the input / output devices, information about the bus occupation time of the input / output device and the time required for actual data transfer; The device number and the reception order are input, the information of the input / output device corresponding to the input device number is read out by referring to the storage means, and when the bus use permission signal from the processor is received, timing is started. , From the bus occupancy time of the I / O device with the highest reception order to the time when the actual data transfer is performed after the bus of the I / O device with the next highest reception order is occupied The first count end signal output after the lapse of a time obtained by subtracting,
Counter means for outputting a second timing end signal after the bus occupancy time of the input / output device having the highest reception order has elapsed from the start of the time counting, and the device number and the reception order from the bus use request control means. When the bus use permission signal from the processor is received, the bus use permission signal for the input / output device having the highest reception priority is validated until the second time end signal is received. A bus arbitration device, comprising: a bus use permission control means for enabling a bus use permission signal for an input / output device having the next highest reception order when receiving a time end signal of 1. 2. The bus arbitration device according to claim 1, wherein a memory is connected to the bus, and the data transfer is a data transfer between the input / output device and the memory without passing through the processor. 3. The bus arbitration device according to claim 1, wherein the information stored in the storage unit is set from outside the storage unit.