JPH11143825A - Bus arbitration mechanism - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrate the using right of a bus without introducing system down. SOLUTION: When a processor 12 outputs 'bus use request' to a bus arbiter 20 by a signal br12 , the bus arbiter 20 shows 'bus use permission' by a signal bg to give the processor 12 by way of a processor 11. When the processor 12 cancels the 'bus use request', 'bus use permission' which is not received by any processor is left outputted but a conversion means 21 inputs this 'bus use permission' and validates bus under-use information BBSY to inform the bus arbiter of 'a bus is under use'. The bus arbiter 20 receiving 'a bus is under use' cancels 'bus use permission'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration mechanism for arbitrating the right to use a bus shared by a plurality of processors in a computer system or the like.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional bus arbitration mechanism. This bus arbitration mechanism includes a bus arbiter 1 for arbitrating the right to use the bus B. In a computer system or the like, a plurality of processors 2, 3, and 4 are connected to a bus B. Each of these processors 2 to 4 is a signal line L
1, L2 and L3 are connected to the bus arbiter 1. Each of the processors 2 to 4 inputs and outputs data from the other processors 2 to 4 or an interface unit (not shown) via the bus B. That is, the configuration is such that the bus B is shared. However, since the bus B can input / output data to only one processor at a time, means for adjusting the right to use the bus B is required. The bus arbiter 1 is provided in a bus adjusting mechanism for adjusting the right to use the bus B. Signal line L1, the bus request signals br _2, br _3, br ₄ it is then output from the processor 2-4 is intended to transmit to the bus arbiter 1, the signal line L1, processor 2 4 are connected by a wired OR. The signal line L2 transmits bus busy information bbsy ₂ , bbsy ₃ , bbsy ₄ output from each of the processors 2 to 4 to the bus arbiter 1. The signal line L2 is connected to the processors 2 to 4. 4 are connected by a wired OR. Signal line L3 is for transmitting a bus grant signal bg ₁ output from the bus arbiter 1 to processor 3-4 for the signal lines L3, the processor 2-4 in turn daisy chain (Daisy Chain )It is connected.

FIG. 3 is a time chart showing the operation of FIG. 2 by waveforms. The operation of the bus arbitration of FIG. 2 will be described with reference to FIG. Each of the processors 2 to 4 sends a bus use request signal br ₂ , br when it becomes necessary to use the bus.
₃ and br ₄ are respectively set to valid “L” levels.
“L” level bus use request signals br ₂ , br ₃ , br
Numeral ₄ indicates a "bus use request", which is transferred to the bus arbiter 1 via the signal line L1. For example, when the two processors 3 and 4 simultaneously transfer the "bus use request" to the bus arbiter 1 as shown at time t1 in FIG. 3, the bus arbiter 1 that has input the "bus use request" changes the bus use permission signal bg1 to a valid "L" level. Set to level. As a result, "bus use permission" is output. The "bus use permission" is first input to the processor 2, but since the processor 2 has not output the "bus use request", the "bus use permission" is not received, and the "bus use permission" is not changed. Transfer to processor 3. The processor 3 receives the “bus use permission” transferred from the processor 2 and occupies the bus B, and at time t2,
Set the bus busy information BBSY ₃ valid "L" level to transfer to the bus arbiter 1 via the signal line L2 by. That is, valid bus busy information bbsy ₃ is input to the bus arbiter 1. Each bus busy information bbsy ₂ , bbs
The signals y ₃ and bbsy ₄ are signals indicating that the bus B is in use (“bus in use”) in a valid state, and indicating that the bus B is not in use in an invalid state.
The processor 3 outputs “bus in use” in parallel with
The bus use request signal br ₃ is set to the “H” level to cancel the “bus use request”.

After the processor 3 has finished using the bus B, the bus arbiter 1 sets the bus busy information bbsy ₃ to an invalid “H” level at time t, cancels “bus busy”, and then returns to “bus busy”. "Use permission" is output from the signal line L3.
At this time, the “bus use permission” output from the bus arbiter 1 is transferred to the processor 4 that outputs the “bus use request” through the processors 2 and 3. The processor 4 outputs the time t
With occupying the bus B by entering the "bus use permission" at 4, to set the bus used in the information bbsy ₄ to a valid "L". Further, the processor 4 outputs a bus use request signal br ₄
Is set to the “H” level to cancel the “bus use request”. Here, while the processor 4 occupies the bus B,
When the processor 2 sets the bus use request signal br ₂ to the “L” level and outputs a “bus use request”, the time t5
, The processor 4 withdraws “bus in use” and
Until is released, the processor 2 continues to issue the "bus use request". When the processor 4 withdraws "bus in use", the bus arbiter 1 outputs "bus use permission" again, and causes the processor 2 to occupy the bus B.

[0005]

However, the conventional bus arbitration mechanism has the following problems. FIG.
3 is a time chart showing a waveform of the problem in FIG. 2. recent years,
Due to the necessity of improving the bus performance, burst transfer for transferring a large number of data during one bus use right acquisition is performed, and each of the processors 2 to 4 occupies the bus B for a long period of time. May be. When the processors 2 to 4 perform multitask processing, a task with a higher priority is processed with a higher priority than a task with a lower priority. FIG. 4 shows each processor 2 to 2 when this multitasking is performed.
4 shows the waveforms of the input / output signals. Note that bgin _{2 to} bgin ₄ in FIG. 4 indicate the timing at which each of the processors 2 to 4 inputs the bus permission signal bg output from the bus arbiter 1 via the signal line L3, and bgout ₂ to bgout ₂
Gout ₄ indicates the timing at which each of the processors 2 to 4 outputs to the subsequent stage.

For example, the processor 3 transmits the “L” bus use permission signal bg from the bus arbiter 1 via the processor 2 to b
Received at gin ₃ timing, bus busy information bbs
Set y ₃ to a valid "L" level, it is assumed that is performing burst transfers occupy the bus B. In this state, when the processor 4 sets the bus use request signal br ₄ to “L” to generate a “bus use request”, the bus arbiter 1
Does not generate a "bus use permission" corresponding to the "bus use request" of the processor 4 until the "bus use" is canceled after the end of the burst transfer. That is, the bus use permission signal b
The processor 4 is made to wait without setting the level of g to valid “L”. Here, the processor 4, when another higher priority than the access to the bus B task is generated, because the processor 4 to process the high priority task, the bus request signal br ₄ Set to “H” to cancel “bus use request”. Therefore, “bus use” of the processor 3 is canceled and “bus use permission” output by the bus arbiter 1 in response to “bus use request” of the processor 4
And the timing at which the processor 4 cancels the “bus use request” occurs at the same time. In such a case, the processor 4 sets “bus use permission”.
Do not receive On the other hand, bus arbiter 1 is "bus busy"
The bus arbiter 1 does not drop the "bus use permission" on the signal line L3 unless "is input".
Keep issuing. On the other hand, each of the processors 2 to 4 newly adds the bus arbiter 1 in response to the “bus use request” issued by itself.
Since only the "bus use permission" transferred from is received as valid, any processor 2-4 continues to be unable to occupy the bus B, resulting in a system down.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a bus busy information indicating that a bus is in use in a valid state and indicating that the bus is not in use in an invalid state. A bus arbiter for inputting a bus use request and issuing a bus use permission for permitting occupation of the bus when the bus use request is invalid when the bus busy information is invalid; daisy chain connection to the bus arbiter The bus use permission is sequentially transferred, and the bus use request is generated when the necessity of use of the bus occurs, and the bus use permission is given in response to the bus use request generated by itself. When the bus use permission is received, the bus use permission is received without being transferred, the bus is occupied, the valid bus busy information is generated, the bus use request is canceled, and the occupation of the bus is terminated. The plurality of processors to disable each said bus busy information when, in the bus arbitration scheme for arbitrating use right of the bus is provided with a conversion means such as the following. The conversion means is connected to an end of the plurality of processors connected in a daisy chain, and when the bus use permission is given from the plurality of processors, the bus use permission is changed to the valid bus use. It is converted into information and transferred to the bus arbiter. According to the present invention, since the bus arbitration mechanism is configured as described above, even if a bus use permission which is not received by any processor occurs, it is input to the conversion means. The bus use permission input to the conversion means is converted into valid bus use information and transferred to the bus arbiter. As a result, the bus arbiter does not generate a new bus use permission, and a state in which the bus use permission is continued is avoided. Therefore, the above problem can be solved.

[0008]

FIG. 1 is a block diagram of a bus arbitration mechanism showing an embodiment of the present invention. This bus arbitration mechanism arbitrates the right to use the bus B among the three processors 11, 12, and 13 connected to the bus B, and includes the same bus arbiter 20 as the conventional one. These processors 11 to 13
Is connected to the bus arbiter 20 by the signal lines L1, L2, L3.
It is connected to the. The bus arbiter 20 is connected to the signal lines L1,
There are a configuration in which the logic gate group connected to L2 and a buffer for setting the level of the signal line L3 and the like are provided, and a configuration in which similar functions are developed by software. Signal line L1 is a bus request signal br _11, br _12, br ₁₃ respectively output from the processor 11-13 intended to transmit to the bus arbiter 20, the signal line L1, the processing unit 11 to 13 Are connected by a wired OR. The signal line L2 is used for bus in-use information bbsy ₁₁ , bbsy ₁₂ , and bbsy ₁₃ output from the processors 11 to 13, respectively.
And the bus in-use information BBSY described later
0, and the signal line L2 is connected to the processor 1
1 to 13 are connected by a wired OR. Bus busy information bbsy ₁₁ , bbsy ₁₂ , bbsy ₁₃ , BBS
Y is a signal indicating that the bus B is in use (“bus in use”) in a valid state, and indicating that the bus B is not in use in an invalid state. The signal line L3 is
A bus use permission signal bg output from the bus arbiter 20 is transmitted to the processors 11 to 13, and the signal line L3
, The processors 11 to 13 are sequentially daisy-chain connected. The conversion means 21 is provided at a position where the processors 11 to 13 connected in a daisy chain of this bus arbitration mechanism are terminated. The conversion means 21 is a processor 1
A buffer 2 that drives a bus use permission signal bg given from the side 1 to 13 and outputs it as bus use information BBSY
1a. The output terminal of the buffer 21a is connected to the bus arbiter 20 via the signal line L2.

FIG. 5 is a time chart showing the operation of FIG. 1 by waveforms. The operation of the bus arbitration mechanism of FIG. 1 will be described with reference to FIG. Incidentally, in FIG. 5, bgin ₁₁ ~
The waveform shown as bgin ₁₃ is a bus permission signal bg output from the bus arbiter 20 via the signal line L3.
The timing at which each of the processors 11 to 13 inputs is indicated by bg
out ₁₁ ~bgout ₁₃ shows the timing of each processing unit 11 to 13 is output to the subsequent stage. Each processor 11-
When the bus use information bbsy _{11 to} bbsy ₁₃ output by the output unit ₁₃ and the bus use information BBSY output by the conversion unit 21 are at the invalid “H” level, for example, the processor 12 sets the bus request signal br ₁₂ to the valid “H” level. When a “bus use request” is generated at L level and transmitted to the bus arbiter 20,
The bus arbiter 20 sets the bus use permission signal bg to a valid “L” level and generates “bus use permission”. At this time, since the processor 11 has not generated the “bus use request”, the processor 11 transfers the “bus use request” to the processor 12 without receiving the “bus use permission”. The processor 12 receives the “bus use permission” transferred from the processor 11 and does not transfer it to the processor 13. The processor 12 that has received the “bus use permission” receives a bus use right, occupies the bus B, and performs burst transfer via the bus B. In parallel with this, processor 12, both bus use request signal br ₁₂ to "H" level withdraw the "bus request" valid bus busy information BBSY ₁₂ indicating that the use of the bus B “L” is set and “bus in use” is output to the bus arbiter 20. "Bus in use"
Are output to the bus arbiter 20 until the processor 12 completes the burst transfer.

[0010] period processor 12 occupies the bus B, processor 13 is set to "L" level bus request signals br ₁₃ also generates a "bus request", the bus arbiter 20 Until "bus in use" is canceled by the processor 12, the "bus use permission" corresponding to the "bus use request" of the processor 13 is not generated. If another high-priority task that must be processed inside the processor 13 occurs while waiting for the “bus use permission”, the processor 13 sets the bus use request signal br ₁₃ to “ H ”level. In other words, "bus use request"
Cancel This processor 13 is "bus use request"
Immediately before canceling, the bus occupation of the processor 12 ends and the “bus busy information” output by the processor 12 is canceled, and “bus use permission” is output from the bus arbiter 20 correspondingly. The “bus use request” of the processor 13 has been canceled. Therefore, even if “bus use permission” is input to the processor 13 via the processor 12, the processor 13 does not receive the “bus use permission” and sends this “bus use permission” to the conversion unit 21 side. Forward. Also, for example,
Even if the processor 11 generates a “bus use request” immediately before the processor 13 cancels the “bus use request”, if the “bus use permission” has already been output to the processor 12, the processor 11 Does not receive a "bus permission".

In such a state, the “bus use permission” output from the bus arbiter 20 is input to the conversion means 21. Buffer 21a in conversion means 21
Drives the input “bus use permission” and converts it into valid “L” level bus use information BBSY. That is, the conversion means 21 sets the “bus use permission” to the valid “L”
The information is converted into the bus busy information BBSY of the level, and "bus busy" is indicated to the bus arbiter 20. The bus arbiter 20
When the "bus busy" provided by the conversion means 21 is received, the "bus use permission" output so far is temporarily canceled. That is, the bus arbiter 20 outputs the bus use permission signal b
g is returned to the “H” level. As a result, the level of the signal input to the conversion means 21 also becomes “H” level, and the bus busy information BBSY output from the conversion means 21 also becomes “H” level, and “bus busy” on the signal line L2. Are all canceled. When the “bus in use” is canceled, the bus arbiter 20 generates a new “bus use permission” corresponding to the “bus use request” generated by the processor 11.
That is, the level of the bus use permission signal bg is changed to a valid "L" level.
Set to level. Thereby, the bus B is connected to the processor 12,
13, the processor 11 uses the bus B as usual.

As described above, in the present embodiment, "bus use permission" is converted to "bus busy" by the bus arbitration mechanism for arbitrating the bus B of the processors 11 to 13 connected in daisy chain. Since the conversion means 21 is provided,
When the "bus use request" is canceled, even if a "bus use permission" occurs in which none of the processors 11 to 13 is received, it is converted to "bus busy" and the subsequent bus B
Arbitration function can be prevented from stopping. Therefore, the reliability of the system can be guaranteed. In addition, the present invention
The present invention is not limited to the above embodiment, and various modifications are possible. For example, the number of daisy-chain connection processors 11 to 13 is not limited to three, and may be further increased. Further, each bus use request signal br ₁₁ -br ₁₃ , each bus use information b
bsy ₁₁ ~bbsy _13, BBSY, and bus grant signals bg may be constituted by a positive logic without negative logic.

[0013]

As described above in detail, according to the present invention, since the bus arbitration mechanism having the bus arbiter is provided with the conversion means at the terminal side of a plurality of processors daisy-chain connected to the bus arbiter. Even if a bus use permission that cannot be received by any processor occurs due to multitask processing or the like, it is converted into valid bus use information, and the bus use permission is canceled. Therefore, system down of a computer system or the like including the bus arbitration mechanism can be avoided, and reliability is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a bus arbitration mechanism according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional bus arbitration mechanism.

FIG. 3 is a time chart showing the operation of FIG. 2 by waveforms.

FIG. 4 is a time chart showing the waveform of the problem in FIG. 2;

FIG. 5 is a time chart showing the operation of FIG. 1 by waveforms.

[Explanation of symbols]

11-13 processor 20 bus arbiter 21 converting means 21a buffer br ₁₁ ~br ₁₃ bus request signals bg bus grant signal bbsy11~bbsy13, BBSY bus busy information B bus

Claims (1)

[Claims] In the valid state, bus use information indicating that the bus is in use and in the invalid state indicating that the bus is not in use and a bus use request are input, and the bus use information is invalid. A bus arbiter for generating a bus use permission for permitting the occupation of the bus when the bus use request is issued. The bus arbiter is daisy-chained to the bus arbiter to sequentially transfer the bus use permission and to use the bus use. When the need arises, the bus use request is generated, and when the bus use permission is given in response to the bus use request generated by itself, the bus use permission is received without transferring the bus use permission. A plurality of occupied bus valid information is generated, the bus use request is canceled, and the bus occupied information is invalidated when the occupation of the bus is completed. A bus arbitration mechanism for arbitrating the right to use the bus with respect to the master device, wherein the bus arbitration mechanism is connected to the ends of the plurality of daisy-chain-connected processors and the bus use permission is given from the plurality of processors; A bus arbitration mechanism provided with conversion means for converting the bus use permission into the valid bus use information and transferring the information to the bus arbiter.