JPH09138773A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optionally set the priority order of acquiring the using right of a data transfer bus by generating a bus acquiring signal and transferring it to a bus controller when an identification signal given from the bus controller coincides with a set identification signal. SOLUTION: A bus requiring source signal/REQID given from the control circuit of a data transfer controller and an enable signal ENB given from an ID comparator 364 are inputted in an AND circuit 360 within a bus requiring circuit 312. The AND circuit 360 outputs a bus requiring signal/REQ onto a bus requiring signal line 320 corresponding to these signals/REQID, ENB. An ID comparator 364 compares an ID number registered in a register 365 and an ID number held by a latch 366 with each other and when both of them coincide with each other, activates the enable signal ENB. Then the data transfer controller starts transfer by a fast bus 208.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a plurality of data transfer controllers.

[0002]

2. Description of the Related Art A so-called DMA (Direct Memory Access) controller is known as a data transfer controller that occupies a bus and transfers data.
Further, a data transfer controller called a bus master is used in a bus called a PCI bus.

[0003]

When the computer system has a plurality of data transfer controllers, each data transfer controller requests a bus request signal to the bus arbiter (bus arbitration circuit) when it wants to occupy the bus. The bus arbiter performs control for assigning the bus use right according to the bus request signal. Note that such allocation of bus usage rights is called "bus arbitration."

In order to perform bus arbitration, a signal line dedicated to bus arbitration is used. For example, in the PCI bus, a pair of bus request signal lines for transmitting a bus request from each bus master to the bus arbiter and a bus permission signal line for transmitting a bus use permission from the bus arbiter to the bus master are used. The bus request signal line and the bus permission signal line are
One pair is required for each bus master. For this reason, conventionally,
When the number of bus masters increases, the number of bus request signal lines and the number of bus permission signal lines must be increased accordingly, which makes it difficult to add a large number of bus masters (data transfer controllers). there were.

The present invention has been made to solve the above problems in the prior art, and an object thereof is to provide a computer system in which a large number of data transfer controllers can be easily added.

[0006]

In order to solve at least a part of the above-mentioned problems, a first invention is a computer system, which is a data transfer bus including an address bus and a data bus. A plurality of data transfer controllers connected to the data transfer bus and each having a function of occupying the data transfer bus and transferring data, and in response to a request from at least one of the plurality of data transfer controllers. A bus controller for controlling the data transfer bus to be occupied by any of the plurality of data transfer controllers, and an identification signal for identifying each of the plurality of data transfer controllers from the bus controller. An identification signal bus for transferring to the data transfer controller and the plurality of data buses. Is OR connected to the transfer controller, at least one of said plurality of data transfer controller
And a bus request signal line for transferring a bus request signal generated when one of the plurality of data transfer busses occupies the data transfer bus, and an OR connection to the plurality of data transfer controllers. A bus acquisition signal line for transferring to the bus controller a bus acquisition signal generated to indicate that one is occupying the data transfer bus, the bus controller comprising the plurality of data transfer controllers. A priority register for storing the priority of each data transfer controller when permitting occupation of the data transfer bus, and stored in the priority register according to a bus request signal given via the bus request signal line. One of the plurality of data transfer controllers according to the assigned priority
Identification signal generating means for sequentially generating an identification signal indicating
Each data transfer controller is provided from the bus controller via the identification signal bus in the state of generating an identification signal register storing a preset setting identification signal and the bus request signal. Bus acquisition signal generation means for generating the bus acquisition signal and transferring it to the bus controller when the identification signal matches the setting identification signal.

Since the bus request signal line is OR-connected to the plurality of data transfer controllers, when at least one data transfer controller generates the bus request signal, the bus request signal is sent to the bus controller via the bus request signal line. Transmitted. The identification signal generating means of the bus controller sequentially generates the identification signals of the plurality of data transfer controllers in accordance with the predetermined priority order in response to the bus request signal. This identification signal is transferred to each data transfer controller via the identification signal bus. And
The bus acquisition signal generating means of the data transfer controller which is generating the bus request signal switches the data transfer bus when the same identification signal as the setting identification signal preset in its own identification signal register appears on the identification signal bus. A bus acquisition signal indicating occupancy is generated and output to the bus acquisition signal line. Since the bus acquisition signal line is OR-connected to the plurality of data transfer controllers, when at least one data transfer controller generates the bus acquisition signal, the bus acquisition signal is transmitted to the bus controller via the bus acquisition signal line. . To arbitrate bus requests and acquisitions,
Since only one bus request line, one bus acquisition signal line, and the identification signal bus are used, a large number of data transfer controllers can be easily added without adding signal lines.

In the first invention, the priority register includes an identification signal table for storing identification signals of the plurality of data transfer controllers at least once in an arbitrary order, and the identification signal generation is performed. The means is operable by the bus request signal and cyclically updates a count value in synchronization with a predetermined clock signal; and an identification corresponding to the count value by giving the count value to the identification signal table. And a means for outputting a signal.

With this configuration, each time the count value of the counter circulates once, the respective identification signals of the plurality of data transfer controllers are output at least once. The identification signal registered in the identification signal table a plurality of times is output a plurality of times each time the count value circulates once. Therefore,
By rewriting the registered contents of the identification signal table, each data transfer controller can arbitrarily set the priority order for acquiring the right to use the data transfer bus.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

A. First Embodiment: Next, an embodiment of the present invention will be described based on an embodiment. FIG. 1 is a block diagram showing the configuration of a computer system as a first embodiment of the present invention. In this computer system, a CPU 200 and a main memory 202 are connected to a host bus 204. The host bus 204 is connected to the high speed bus 208 via the bus bridge 206. This highway bus 208
Is a bus in which addresses and data are transferred in a time division manner by a common signal line. The high-speed bus 208 is a synchronous bus that operates in synchronization with a clock signal, but the frequency of the clock signal may be 33 MHz or less, and the clock frequency can be changed during the operation.
The host bus 204 and the high speed bus 208 correspond to the data transfer bus in the present invention.

A video controller 212 and an expansion bus bridge 214 are connected to the high speed bus 208. A video RAM (VRAM) 222 as a frame memory and a color CRT 224 or a color liquid crystal display (LCD) 226 as a display device are connected to the video controller 212. The video controller 212 has a writing function of writing a digital video signal (video data) given via the high-speed bus 208 to the VRAM 222, and a video signal read from the VRAM 222 to read a color CRT 224 or a liquid crystal display 226.
It has a display function of displaying an image by giving it to the.

The expansion bus bridge 214 is used for the high speed bus 20.
8 is a bridge for connecting the low speed bus 230.
Various I / O controllers 232, connectors (not shown), etc. are connected to the low-speed bus 230. Low-speed bus 23
0 has a lower data transfer rate than the high speed bus 208,
A relatively low speed input / output device such as a floppy disk device or a keyboard is connected.

Three moving image transfer controllers 250, 260 and 270 are further connected to the high speed bus 208. The first video transfer controller 250 has a compression / compression
The expansion circuit 252 is connected, and the compression / expansion circuit 252 is connected to the modem 254. The compressed moving image video signal supplied from the external communication line to the modem 254 is expanded by the compression / expansion circuit 252, and the expanded video signal is transferred by the moving image transfer controller 250.

The second moving image transfer controller 260 includes
An A-D converter 262 is connected, and a video decoder 264 is connected to the A-D converter 262. A television tuner 266 is further connected to the video decoder 264, and a video camera is connected to its input terminal. The video decoder 264 is a TV tuner 2
By decoding the composite video signal VS given from the moving picture video signal supply device such as 66 or a video camera,
A component video signal (YUV signal or RGB signal), synchronization signals VSYNC and HSYNC, and a field instruction signal FIS are generated. Field instruction signal FIS
Is a signal indicating an odd field or an even field in the case of interlaced scanning. Video decoder 264
A color signal conversion circuit for converting a YUV signal into an RGB signal is provided therein. The AD converter 262 converts the analog component video signal into the digital component video signal DS. The digital component video signal DS is transferred by the second moving image transfer controller 260. Alternatively, it is compressed by the compression / expansion circuit 252, and the first moving image transfer controller 250 performs M compression.
It is transmitted to a communication device such as an ODEM or transferred to an external storage device (not shown) such as a hard disk. A CD-ROM device 272 is connected to the third moving image transfer controller 270 and transfers a moving image signal supplied from the CD-ROM device 272.

Three moving image transfer controllers 250, 26
Each of 0 and 270 is able to acquire the right to use (occupy right) the high-speed bus 208 and transfer the moving image signal. The video controller 212 is also the high-speed bus 2.
It is possible to acquire the usage right of 08 and transfer the moving image signal. That is, the video controller 212 and the moving image transfer controllers 250, 260, 270 correspond to the data transfer controller in the present invention. Hereinafter, the video controller 212 and the moving image transfer controllers 250, 260, 270 are simply referred to as “data transfer controller”.

FIG. 2 is a block diagram showing a circuit configuration related to request and acquisition of the right to use the high-speed bus 208. The bus bridge 206 assigns the right to use the high-speed bus 208 to the four data transfer controllers 212, 250, 260, 270.
A bus controller 300 for performing control assigned to any of the above. The four data transfer controllers 212, 250, 260, 270 respectively include bus request circuits 311 to 314. The bus controller 300 and the four bus request circuits 311 to 314 are connected to each other by one bus request signal line 320, one bus acquisition signal line 322, and an ID bus 324 having a multiple bit width. The bus request signal line 320 and the bus acquisition signal line 322 are wired-OR connected to the data transfer controllers 212, 250, 260, 270.

FIG. 3 is a block diagram showing the internal configuration of the bus controller 300 and the bus request circuit 312. The bus controller 300 includes a ring counter 340 and an ID.
Table register 342 and 3-state buffer 344
An AND circuit 346, a negative logic OR circuit (that is, an AND gate) 348, and a D-type flip-flop 350.
And

The bus request circuit 312 includes a negative logic AND circuit (that is, an OR gate) 360 and a NAND circuit 36.
1, an inverter 362, and an ID comparator 364
And a latch 366. The other bus request circuits 311, 313, 314 also have the same circuit configuration as the bus request circuit 312 shown in FIG. The ring counter 340 of the bus controller 300 and the bus request circuit 312
The system clock signal CLK of the computer system is commonly input to the latch 366 of the.

AND circuit 360 in bus request circuit 312
A bus request source signal / REQID given from a control circuit (bus request signal generating means) (not shown) of the data transfer controller 250 and an enable signal ENB given from the ID comparator 364 are input to the. A
The ND circuit 360 receives these signals / REQID, ENB.
Bus request signal / REQ depending on the bus request signal line 3
Output on 20. In this specification, a signal name preceded by "/" means negative logic (low active). The NAND circuit 361 has the bus request source signal / R inverted by the inverter 362.
The EQID and the enable signal ENB are input. The NAND circuit 361 outputs the bus acquisition signal / ACK on the bus acquisition signal line 322 according to these signals.

The bus request signal line 320 is pulled up, and the bus request signal line 320 is wired-OR connected to each of the bus request circuits 311 to 314. Therefore, when any one of the four bus request circuits 311 to 314 (FIG. 2) activates the bus request signal / REQ (L level), the bus request signal line 320 becomes active (L level). The same applies to the bus acquisition signal line 322.

The procedure from the bus request of the data transfer controller to the acquisition of the bus use right is as follows. In the initial state, the enable signal ENB is at L level, and the bus request source signal / REQID, the bus request signal / REQ, and the bus acquisition signal / ACK are at H level (non-active). The data transfer controller 250 uses the bus request source signal /
When REQID is activated (L level), AND
The bus request signal / REQ output from the circuit 360 becomes active (L level). As a result, the output of the OR circuit 348 in the bus controller 300 becomes L level, and this output is inverted and given to the D input terminal of the D-type flip-flop 350. The D-type flip-flop 350 is
The Q output is raised to the H level in synchronization with the next rising edge of the system clock signal CLK. This Q output is input to the AND circuit 346 together with the bus acquisition signal / ACK. In the initial state, the bus acquisition signal / ACK is at H level, so the Q output of the D-type flip-flop 350 is at H level.
When the level becomes high, the counter enable signal CNE output from the AND circuit 346 becomes high. The ring counter 340 is enabled (operable) by this counter enable signal CNE. The Q output of the D-type flip-flop 350 is also input to the control input terminal of the 3-state buffer 344. The 3-state buffer 344 enters a low impedance state when the Q output of the D-type flip-flop 350 becomes H level, and outputs the output of the ID table register 342 to the ID bus 324. The ID bus 324 is pulled up.

The ring counter 340 of the bus controller 300 is a counter that cyclically counts the number of pulses of the system clock signal CLK. For example, when a 4-bit counter is used as the ring counter 340, the count value CNT cyclically changes in the range of 0-15.
The count value CNT is given to the ID table register 342.

The ID table register 342 generates an ID number (also called "identification number" or "identification signal") for identifying the data transfer controller according to the count value CNT given from the ring counter 340.
FIG. 4 shows IDs registered in the ID table register 342.
It is explanatory drawing which shows the content of the table. The ID number of the data transfer controller is registered for each value of the count value CNT in the ID table. In FIG. 4A, for the sake of convenience, the ID number is preceded by “#” to distinguish it from the count value CNT. As shown in FIG. 2, four data transfer controllers 212, 250, 260 and 270 are connected to the computer system of this embodiment, and ID numbers # 1 to # 4 are respectively assigned. In the ID table, these four ID numbers # 1 to #
4 is registered by the CPU 200. Each ID number is I
It only needs to be registered at least once in the D table,
The same ID number may be registered multiple times. In addition, as the ID number corresponding to the maximum value (= 15) of the count value CNT, a specific value indicating that neither data transfer controller is permitted to use the bus (see FIG. 4).
In the example of (A), # 15 ('F' in hexadecimal notation) is registered. This specific ID number (= # 15 = '
F ′) means that the bus controller 300 uses the high speed bus 208. Therefore, each time the count value CNT circulates once in the range of 0 to 15, the bus controller 300 acquires the right to use the high-speed bus 208 once.

Count value CNT of ring counter 340
Is circularly updated in the range of 0 to 15, the value of the ID number output from the ID table register 342 is as shown in FIG.
As shown in (B), it appears cyclically in the order registered in the ID table. Therefore, the data transfer controller corresponding to the ID number registered many times in the ID table has a high probability of acquiring the right to use the high-speed bus 208. I output from the ID table register 342
The D number is output to the ID bus 324 via the 3-state buffer 344. Since the ID bus 324 is pulled up, when the three-state buffer 344 is kept in a high impedance state, the signal value of the ID bus 324 is the high speed bus of the bus controller 300 (that is, the bus bridge 206). A specific ID number (= # 15 = ') indicating that the usage right of 208 is acquired.
F ').

The ID table register 342 has a function as a priority order register for storing the priority order of each data transfer controller. In addition, ring counter 3
The 40 and the 3-state buffer 344 correspond to the identification signal generating means in the present invention.

The latch 366 of the bus request circuit 312 is I
The ID number transferred via the D bus 324 is held in synchronization with the falling edge of the system clock signal CLK. The ID number held by the latch 366 is the ID comparator 364.
Given to. Register 3 in ID comparator 364
65, the ID number (= # 2) assigned to the data transfer controller 250 including the bus request circuit 312 is C.
Written by PU200. The ID comparator 364 compares the ID number registered in the register 365 with the ID number held by the latch 366, and activates the enable signal ENB when they match. When the enable signal ENB becomes active, the data transfer controller 250 occupies the high speed bus 208 and starts data transfer.

The NAND circuit 361 has an enable signal E.
When NB becomes H level, the bus acquisition signal / ACK which is its output is made active (L level). As a result,
The bus acquisition signal line 322 becomes active (L level). On the other hand, the AND circuit 360 outputs the enable signal EN.
When B becomes H level, the output is the bus request signal /
Make REQ non-active (H level). At this time,
Bus request signal / R output from another bus request circuit
When all EQs are also non-active, the bus request signal line 320 also becomes non-active (H level).

The register 365 in the ID comparator 364 corresponds to the identification signal register in the present invention. In addition, the ID comparator 364 and the NAND circuit 36
1 corresponds to the bus acquisition signal generating means in the present invention.

FIG. 5 is a timing chart showing the operations of the bus controller 300 and the bus request circuit. In this example, as shown in FIGS. 5A and 5B, the ID number is #
The bus request source signals / REQID (# 4), / in the two bus request circuits 314, 313 (4, # 3) (FIG. 2).
This is an example when the REQID (# 3) is sequentially activated (L level). As shown in FIG. 5C, the bus request signal / REQ on the bus request signal line 320 is the bus request source signal / REQID (# 4), / REQID (#
While at least one of 3) is active (L level), it is kept active.

When the bus request signal / REQ goes low, the counter enable signal CNE output from the AND circuit 346 is synchronized with the next rising edge (time t1) of the system clock signal CLK (FIG. 5 (g)). Is H
The level is reached, and the ring counter 340 starts operating. After this, the count value CNT of the ring counter 340
(FIG. 5 (e)) increases by 1 in synchronization with the rising edge of the system clock signal CLK. The ID number is read from the ID table register 342 according to the count value CNT. This ID number is output to the ID bus 324 via the 3-state buffer 344 (FIG. 5 (f)).

In the example of FIG. 5, the bus request source signal / REQI
The ID numbers of the data transfer controller outputting D are # 3 and # 4. Therefore, until the ID number output on the ID bus 324 matches one of these two ID numbers # 3 and # 4, the count value CNT (see FIG.
(E)) and the ID number (FIG. 5 (f)) are sequentially updated in synchronization with the system clock signal CLK. And I
When the ID number output on the D bus 324 becomes # 4,
At time t2 (the next rising edge of the clock signal CLK), the bus request circuit 314 (FIG. 2) whose ID number is # 4 causes the bus acquisition signal / ACK (FIG. 5 (d)) to fall to active (L level). . In addition, the bus request circuit 31
The data transfer controller 270 including the high speed bus 2
The usage right of 08 is acquired and data transfer is started. In addition,
When the bus acquisition signal / ACK goes low, the counter enable signal CNE output from the AND circuit 346 in the bus controller 300 goes low. Therefore,
While the bus acquisition signal / ACK is kept at L level,
The operation of the ring counter 340 is suspended.

The data transfer controller 270, which has acquired the right to use the bus, activates the bus request source signal / REQID (# 4) (L level) until the data transfer is completed.
, While the enable signal ENB in the data transfer controller 270 is also maintained at H level. Therefore, the NAND circuit 361 receives these signals / REQID.
(# 4), the bus acquisition signal / ACK is kept active (L level) according to ENB.

When the data transfer is completed at time t3, the data transfer controller 270 makes the bus request source signal / REQID (# 4) non-active (H level).
As a result, the bus acquisition signal / ACK output from the NAND circuit 361 also becomes non-active (H level). As a result, the counter enable signal CNE becomes high again.
A level is reached and the ring counter 340 is enabled. Then, the ring counter 340 restarts counting up in synchronization with the rising edge of the system clock signal CLK. At time t3, since the bus request source signal / REQID (# 3) from the other data transfer controller 260 is kept active (L level), the bus request signal / REQ is also kept active. There is.

When the ID number on the ID bus 324 becomes # 3, time t4 (the next rising edge of the clock signal CLK)
In this case, the data transfer controller 260 (FIG. 2) having this ID number receives the bus acquisition signal / ACK (FIG. 5).
(D)) is activated (L level) to acquire the right to use the high-speed bus 208 and start data transfer. When the data transfer is completed at time t5, the bus request source signal / REQID (# 3) and the bus acquisition signal / AC
K is made inactive (H level). As a result, there is no data transfer controller that activates the bus request signal / REQ, so the bus request signal line 32
0 becomes non-active (H level).

When any of the data transfer controllers activates the bus request signal / REQ after time t5, the count value CNT (FIG. 5 (e)) is counted up to 6 and the ID number corresponding to the count value CNT is increased. It is output to the ID bus 324. In other words, the ring counter 34
The count value CNT of 0 is not initialized and the count value C
The update of NT is resumed from the suspended state. Therefore,
Even when the bus request signal / REQ becomes intermittently active (L level), all the ID numbers registered in the ID table shown in FIG. 4A are sequentially read and used.

As described above, when a plurality of data transfer controllers request the right to use the high-speed bus 208, the bus controller 300 outputs the ID number of each data transfer controller onto the ID bus 324 according to the preset priority order. . Each data transfer controller acquires the right to use the high-speed bus 208 and executes data transfer when an ID number (setting identification signal) preset in itself is output to the ID bus 324. Further, the other data transfer controller requesting the right to use the bus has its own set ID number I
It waits until output to the D bus 324. As a result,
According to the priority order set in the ID table register 342, the right to use the high-speed bus 208 can be successfully assigned to the plurality of data transfer controllers.
In particular, as the signal line for arbitrating the right to use the high-speed bus 208, only the ID bus 324, one bus request signal line 320, and one bus acquisition signal line 322 are required, and the data transfer controller is used. When expanding,
It is not necessary to add these signal lines 324, 330, 322. Therefore, (2 ⁿ -1) (n is the ID bus 324)
It is possible to add more data transfer controllers up to the number of bits). Such a feature is particularly advantageous when each data transfer controller is expanded in the form of an expansion board (expansion card) of a computer system.

Since the ID number of each data transfer controller and its priority can be arbitrarily set by the CPU 200, the priority of each data transfer controller can be appropriately set according to the application software. Is. The CPU 200 is
The ID number (identification signal) is registered in the ID table register 342 and also has a function as an identification signal setting means for setting each ID number in each bus request circuit.

B. Second Embodiment: FIG. 6 is a block diagram showing the configuration of a computer system as a second embodiment of the present invention. This computer system is provided with four sets of external buses 410, 420, 430, 440 centering on a main microprocessor unit (M-MPU). Each external bus includes a data transfer bus (including an address bus, a data bus, a control bus) and a bus arbitration bus (including an ID bus, a bus request signal line, and a bus acquisition signal line). A plurality of microprocessors (MPUs) as data transfer controllers are connected to each external bus. Each MPU is provided with a bus request circuit similar to the bus request circuit 312 shown in FIG. Note that, hereinafter, the signal line including the data transfer bus and the bus arbitration bus is also referred to as “integrated bus”.

FIG. 7 is a block diagram showing the internal structure of the main microprocessor unit 400 shown in FIG. The main microprocessor unit 400 has an external bus 41
Four external bus controllers 412, 422, 432, 44 connected to 0, 420, 430, 440, respectively.
2 and external bus controllers 412, 422, 432
Four microprocessors (MPUs) 414, 424, 434, 444 respectively connected to 442 are provided. External bus controllers 412, 422, 432
The 442 has the same internal configuration as the bus controller 300 shown in FIG.

Four MPUs 414, 424, 434, 4
44 are mutually connected by an internal bus 402. The internal bus 402 is an integrated bus including a data transfer bus (including an address bus, a data bus, and a control bus) and a bus arbitration bus (including an ID bus, a bus request signal line, and a bus acquisition signal line). . Also, the first MPU
The 414 includes an internal bus controller 416.
The second to fourth MPUs 424, 434, 444 respectively include internal bus request circuits 426, 436, 446.

Four external bus controllers 4 shown in FIG.
The reference numerals 12, 422, 432, 442 arbitrate bus usage rights among a plurality of MPUs (data transfer controllers) connected to the respective external buses 410, 420, 430, 440. Further, the internal bus controller 416 in the first MPU 414 has four MPUs 414, 4
Arbitrate for the right to use the internal bus 402 between 24, 434 and 444.

As shown in FIGS. 6 and 7, if a plurality of integrated buses including a data transfer bus and a bus arbitration bus are provided, bus arbitration between the data transfer controllers is performed for each integrated bus. be able to. Therefore, it is possible to easily add a data transfer controller to each integrated bus. Further, there is an advantage that the processing can proceed in parallel for each of the plurality of integrated buses.

The present invention is not limited to the above-described examples and embodiments, but can be implemented in various modes without departing from the scope of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a computer system as a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration related to requesting and acquiring a right to use a high-speed bus 208.

FIG. 3 shows a bus controller 300 and a bus request circuit 312.
Block diagram showing the internal configuration of FIG.

FIG. 4 is an ID registered in an ID table register 342.
Explanatory drawing which shows the content of a table.

FIG. 5 is a timing chart showing operations of a bus controller 300 and a bus request circuit.

FIG. 6 is a block diagram showing the configuration of a computer system as a second embodiment of the present invention.

FIG. 7 is a block diagram showing an internal configuration of a main microprocessor 400.

[Explanation of symbols]

200 ... CPU 202 ... Main memory 204 ... Host bus 206 ... Bus bridge 208 ... High speed bus 212 ... Video controller (data transfer controller) 214 ... Expansion bus bridge 222 ... VRAM (frame memory) 224 ... Color CRT 226 ... Liquid crystal display 230 ... Low-speed bus 232 ... I / O controller 250, 260, 270 ... Video transfer controller (data transfer controller) 252 ... Compression / expansion circuit 254 ... Modem 262 ... A / D converter 264 ... Video decoder 266 ... TV tuner 272 ... ROM device 300 ... Bus controllers 311 to 314 ... Bus request circuit 320 ... Bus request signal line 322 ... Bus acquisition signal line 324 ... ID bus 340 ... Ring counter 342 ... ID table register 346 AND circuit 348 ... OR circuit (negative logic) 350 ... D-type flip-flop 360 ... AND circuit (negative logic) 361 ... NAND circuit 362 ... Inverter 364 ... ID comparator 365 ... Register 366 ... Latch 400 ... Main microprocessor unit (M- MPU) 402 ... Internal bus 410, 420, 430, 440 ... External bus 412, 422, 432, 442 ... External bus controller 414, 424, 434, 444 ... Microprocessor (MPU) 416 ... Internal bus controller 426, 436, 446 ... internal bus request circuit / ACK ... bus acquisition signal CLK ... system clock signal CNE ... counter enable signal CNT ... count value ENB ... enable signal / REQ ... bus request signal / REQID ... bus request source signal

Claims (2)

[Claims] 1. A computer system, comprising: a data transfer bus including an address bus and a data bus; and a plurality of data transfer buses connected to the data transfer bus and occupying the data transfer bus to transfer data. A data transfer controller; and a bus controller for controlling the data transfer bus to be occupied by any one of the plurality of data transfer controllers in response to a request from at least one of the plurality of data transfer controllers. An identification signal bus for transferring an identification signal for identifying each of the plurality of data transfer controllers from the bus controller to the plurality of data transfer controllers; and an OR connection to the plurality of data transfer controllers, At least one of the data transfer controllers is A bus request signal line for transferring a bus request signal generated when requesting occupancy of the data transfer bus to the bus controller, and an OR connection to the plurality of data transfer controllers, and one of the plurality of data transfer controllers Bus acquisition signal line for transferring a bus acquisition signal generated to indicate that one is occupying the data transfer bus to the bus controller, wherein the bus controller is connected to the plurality of data transfer controllers. A priority register that stores the priority of each data transfer controller when permitting occupation of the data transfer bus, and a priority register that is stored in the priority register according to a bus request signal given through the bus request signal line. Identification signals indicating one of the plurality of data transfer controllers in sequence according to the priority order. Each data transfer controller includes an identification signal register that stores a preset setting identification signal, and an identification signal register that generates a bus request signal via the identification signal bus. Bus acquisition signal generating means for generating the bus acquisition signal and transferring it to the bus controller when the identification signal given from the bus controller matches the setting identification signal. 2. The computer system according to claim 1, wherein the priority register includes an identification signal table that stores identification signals of each of the plurality of data transfer controllers at least once in an arbitrary order. The identification signal generating means is operable by the bus request signal and cyclically updates a count value in synchronization with a predetermined clock signal; and a counter that applies the count value to the identification signal table. And a means for outputting an identification signal corresponding to the count value.