JP2004213142A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for keeping the high processing efficiency as a whole to arbitrate bus use right, among a plurality of bus masters in a semiconductor integrated circuit device, such as microcomputers. <P>SOLUTION: The means has a first bus 19, a second bus 20 or a third bus 21 which are divided to enable parallel operations, includes a bus arbiter 23 for arbitrating the bus use right of a plurality of bus masters on the first bus 19, e.g., a CPU 11 and a DMAC 12, and enables the arbitration of the priority order of bus use right to be changed, depending on whether the second bus 20 or the third bus 21 is in an operation. During a period where the operation of the second bus 20 is conducted in parallel with the first bus 19, by not giving bus use right to the DMAC 12, and giving bus use right to the CPU 11, reading instructions etc. from a ROM 13 on the first bus 19 become possible, the frequency of the occurrence of undesired standby statuses is reduced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technology effective when applied to a microcomputer or the like having a central processing unit and a data transfer device built therein.
[0002]
[Prior art]
For example, as a technique studied by the present inventor, the following technique can be considered in a semiconductor integrated circuit device such as a microcomputer.
[0003]
The single-chip microcomputer mainly includes a central processing unit (CPU), a ROM (read only memory) for holding a program, a RAM (random access memory) for holding data, and an input / output circuit for inputting and outputting data. Are formed on one semiconductor substrate, and are used for device control and the like (for example, see Non-Patent Document 1).
[0004]
Some of such microcomputers incorporate a direct memory access controller (DMAC) as a data transfer device and perform data transfer independently of a CPU (for example, see Patent Document 1).
[0005]
Such a DMAC can be started by an interrupt request, and can perform a repeat mode, a block transfer mode, and the like. In a system such as a printer, it is suitable for controlling a stepping motor, controlling print data of a printer, and storing received data in a memory.
[0006]
In such an example, transfer of up to eight channels can be performed. The DMAC transfer is independent of the CPU, but is arbitrated by a bus arbiter as bus arbitration means because the bus is shared, and performs a data transfer operation when the bus usage right is given.
[0007]
In the bus arbitration, usually, the DMAC is set to have a higher bus precedence than the CPU. Alternatively, the priority order may be changed in a predetermined order, such as round robin.
[0008]
When performing device control, the DMAC often performs data transfer between a memory and an internal I / O register of a so-called peripheral function such as a timer.
[0009]
The microcomputer bus is divided into an I bus to which a CPU or a DMAC is connected, a P bus to which peripheral function blocks are connected, and an external bus, and performs a write operation to the P bus or the external bus. In this case, a so-called write buffer function is known in which the I bus, that is, the CPU or the DMAC advances the operation without waiting for its completion. In recent years, while the speed of the CPU has been increased, the I bus operates with a faster clock and the P bus or external bus operates with a slower clock in order to reduce power consumption. Becomes important.
[0010]
[Patent Document 1]
JP-A-5-307516 (page 4, FIG. 1)
[0011]
[Non-patent document 1]
Ed., The Institute of Electronics, Information and Communication Engineers, "LSI Handbook", 1st edition, Ohmsha Co., Ltd., November 30, 1984, p. 540-541
[0012]
[Problems to be solved by the invention]
By the way, as a result of studying the technology of the semiconductor integrated circuit device such as the microcomputer as described above by the present inventor, the following became clear.
[0013]
The CPU frequently reads instructions from a memory such as a ROM connected to the I bus, and then reads / writes to a memory such as a RAM. As described above, the DMAC often transfers data between a memory such as a RAM connected to the I bus and peripheral function blocks.
[0014]
For example, if the write buffer function on the P bus is being executed when the DMAC is given the right to use the bus, the DMAC may transfer data between the memory and the peripheral function block unless the write buffer function is completed. In some cases, the transfer cannot be completed and a standby state is set. On the other hand, at this time, if the CPU is given a bus use right, the CPU can read an instruction from a memory on the I bus and read / write data.
[0015]
Accordingly, an object of the present invention is to provide means capable of maintaining high processing efficiency as a whole in arbitrating bus use rights among a plurality of bus masters in a semiconductor integrated circuit device such as a microcomputer.
[0016]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0017]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0018]
That is, the semiconductor integrated circuit device according to the present invention has a divided first bus (first bus) and second bus (second bus or third bus), which can operate in parallel. Bus arbitration means for arbitrating bus usage rights of a plurality of bus masters on the first bus, for example, a central processing unit (CPU) and a direct memory access controller (DMAC) as a data transfer device; In use right arbitration, the priority of bus right arbitration can be changed depending on whether or not the second bus is operating.
[0019]
Further, at least one of the bus masters may indicate the bus to be used when requesting the bus use right.
[0020]
Therefore, according to the semiconductor integrated circuit device, the right to use the bus is given to the data transfer device while the second bus is operating in parallel with the first bus as in the write buffer function. An undesired waiting state that occurs can be avoided. At this time, by giving the right to use the bus to the central processing unit, it becomes possible to read an instruction from the memory on the first bus, and the frequency of occurrence of an undesired standby state is reduced.
[0021]
Further, when the data transfer device requests the right to use the bus, it indicates whether or not to use the second bus, so that the frequency of occurrence of an undesired standby state is further reduced.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0023]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 shows a logical description of a bus arbiter as a bus arbiter in the semiconductor integrated circuit device of the first embodiment. FIG. 3 and FIG. 3 are timing charts showing an example of bus operation in the semiconductor integrated circuit device according to the first embodiment.
[0024]
First, the configuration of the semiconductor integrated circuit device (microcomputer) according to the first embodiment will be described with reference to FIG.
[0025]
The semiconductor integrated circuit device according to the first embodiment is, for example, a microcomputer, and includes a central processing unit (CPU) 11, a DMA controller (DMAC) 12 as a data transfer device, a read-only memory (ROM) 13, a random access memory. (RAM) 14, peripheral function block 15 including a timer, a pulse output circuit, a serial communication interface (SCI), an A / D converter (A / D), an input / output port (IOP) 16, a bus controller (BSC) 17 , A clock oscillator (CPG) 18 and other functional blocks or modules.
[0026]
There are a CPU 11 and a DMAC 12 as bus masters that perform read / write using a bus. The operation is mainly performed by the CPU 11, which mainly reads instructions from the ROM 13 and operates. The DMAC 12 shares a bus with the CPU 11 and performs data transfer on behalf of the CPU 11.
[0027]
Next, the configuration of the bus will be described. Each functional block of the microcomputer is interconnected by an internal bus. The internal bus includes an address bus, a data bus, a bus use right request signal, a bus acknowledge signal, and a bus command (read signal, write signal, bus size signal), not shown.
[0028]
The internal bus includes a first bus (I bus) 19, a second bus (P bus) 20, and a third bus (external bus) 21. These buses are interfaced by a bus controller (BSC) 17.
[0029]
The first bus (IAB, IDB) 19 is connected to the CPU 11, the DMAC 12, the ROM 13, the RAM 14, and the bus controller 17, and the IAB is used as an address bus of an external bus, and the IDB is used as a data bus of the external bus. To be connected to the BUF 22 in the IOP 16. The first bus 19 is designed to reduce the load, widen the bus width (for example, 32 bits), and operate in a unit state in order to connect the bus master and the built-in memories (ROM 13 and RAM 14) at high speed. Have been.
[0030]
The second bus (PAB, PDB) 20 is connected to a bus controller (BSC) 17, a DMAC 12, a timer, a pulse output circuit, an SCI, an A / D converter, an interrupt controller, and an IOP (A to F, 1 to 5) 16. It is connected. Since the second bus 20 has a large number of connected functional blocks and is not used as frequently as the first bus 19, the bus width is limited (for example, 16 bits) and an operation based on a plurality of states (for example, two states) is performed. I do.
[0031]
The third bus (EXAB, EXDB) 21 is connected to the bus controller 17 and the IOPs (AC) 16. Similarly to the second bus, the third bus limits the bus width (for example, 16 bits), performs an operation based on a plurality of states (for example, two states), and can insert a predetermined wait state. The number of bus access states and the presence or absence of a wait can be specified according to the area into which the address space is divided.
[0032]
The bus controller 17 includes a bus arbiter 23, a first bus controller (not shown), a second bus controller 24, a third bus controller 25, a refresh timer (not shown), and the like.
[0033]
The DMAC 12 can request the right to use the first bus 19, and performs read / write via the first bus 19. The second bus 20 is connected as a bus slave, and is read / written by the CPU 11.
[0034]
The CPU 11 can request the right to use the first bus 19. The CPU 11 and the DMAC 12 can use the second bus 20 and the third bus 21 via the first bus 19.
[0035]
The CPU 11 is normally given the right to use the bus. The bus arbiter 23 notifies the CPU 11 of granting the right to use the bus by a puack signal.
[0036]
The DMAC 12 requests a bus use right to the bus arbiter 23 by a dmareq signal, and the bus arbiter 23 informs the DMAC 12 that the bus use right is given by a dmaack signal. At the same time, the cpuack signal is deactivated.
[0037]
ROM 13, RAM 14, timer, pulse output circuit, SCI, A / D converter, IOP (A to F, 1 to 5) 16, each functional block of interrupt controller, and DMAC 12 are read / write by CPU 11 or DMAC 12 as slaves. Is done.
[0038]
Read / write to the second bus 20 and the third bus 21 is performed by the CPU 11 and the DMAC 12 via the first bus 19 as described above. In the case of writing, the CPU 11 and the DMAC 12 output a bus command, an address, and data to the first bus 19, and the second bus controller 24 or the third bus controller 25 corresponding to the specified address transmits the bus width and the bus width. The write operation corresponding to the bus access specification is executed. At this time, the state on the first bus 19 can proceed. This is called a write buffer function.
[0039]
Other functions of the microcomputer according to the first embodiment are outlined below.
[0040]
The input / output port is also used as an external bus signal and an input / output signal of an input / output circuit. The external address (EXAB) and the external data (EXDB) are connected to IAB and IDB of the first bus 19 via a buffer circuit (BUF) 22 included in these input / output ports. PAB and PDB of the second bus 20 are used to read / write the register of the input / output port, and have no direct relation to the external bus. The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, a bus acknowledge signal, and the like. The bus control input signal includes a wait signal, an external bus request signal, and the like. These input / output signals are not shown. The extension of the external bus is selected depending on the operation mode and the like, and the functions of these input / output ports are also selected.
[0041]
IOP (1) is used for timer input / output, IOP (2) is used for pulse output, IOP (3) is used for SCI input / output, IOP (4) is used for analog input, and IOP (5) is also used for DMAC input / output. The DMAC 12, timer, SCI, pulse output, input / output signals between the A / D converter and IOPs (1 to 5), internal interrupt request signals, and the like are not shown.
[0042]
The CPG 18 outputs a clock φI for the bus master, a clock φP for the functional block connected to the second bus (P bus) 20, and a clock φE for the third bus (external bus) 21. It outputs a SYNC signal indicating the synchronization timing of φI and clock φP, and a SYNC signal indicating the synchronization timing of clock φI and clock φE. The frequency of the clock φP and the clock φE can be selected under the condition of the frequency of the clock φI or less.
[0043]
Further, although not shown, it has an interrupt controller, inputs a timer, an SCI, an A / D converter, an interrupt signal output from an input / output port, sends an interrupt request signal to the CPU 11, and a start request signal to the DMAC 12. Output. Also, it inputs a clear signal output from the DMAC 12 and outputs an interrupt clear signal. These interrupt signals and the like are not shown. Although not shown, inputs such as power supply terminals Vcc and Vss, analog power supply terminals AVcc and AVss, reset input RES, standby input STBY, interrupt input NMI, clock inputs EXTAL and XTAL, and operation mode inputs MD0, MD1, and MD2. There are terminals.
[0044]
Next, the function of the bus arbiter 23 as bus arbitration means in the first embodiment will be described with reference to FIG. As described above, the bus arbiter 23 receives the dmareq signal, and outputs the cpuack signal and the dmaack signal. Also, pwrbf and ewrbf signals indicating the write buffer operation of the second bus controller 24 and the third bus controller 25 are input.
[0045]
The right to use the bus to the DMAC 12 is determined when the DMAC 12 requests the right to use the bus (dmareq = 1) and the write buffer operation is not performed on the second bus 20 and the third bus 21 (pwrbf = 0, ewrbf = 0). ) (Dmaack = 1). The right to use the bus to the CPU 11 is given as a logical inversion of the right to use the bus to the DMAC 12.
[0046]
Next, an example of the timing of the bus operation of the microcomputer according to the first embodiment will be described with reference to FIG. The following is an example of a case where φP is φI divided by 2 in the first bus 19 and the second bus 20.
[0047]
The bus arbitration, the IAB output and the IDB input / output of the first bus 19 are pipelined, and this state transits when the ready signal ready is active. That is, when ready = 1, the bus master granted the right to use the bus by the dmark or cpuack signal outputs an address using the IAB from the next clock. The address is used when ready = 1, and the bus master that has output the address inputs and outputs data using the IDB from the next clock.
[0048]
When the CPU 11 performs writing to the address wa1 corresponding to the second bus 20 at the timing T1 in the clock φI, the write data wd1 is output at the timing T2, and these are output to the PAB and PDB of the second bus 20 and The write operation on the second bus 20 is executed. To perform the write buffer operation, the second bus controller 24 sets the pwrbf signal to an active state (pwrbf = 1).
[0049]
On the other hand, the CPU 11 performs the next address output (for example, the instruction read from the ROM 13) at the timing T2. The DMAC 12 makes the dmareq active (dmareq = 1) and requests the right to use the bus. However, the bus arbiter 23 does not give the right to use the bus to the DMAC 12 because the write buffer is in operation.
[0050]
Thereafter, at a timing T4, the second bus controller 24 sets the pwrbf signal to an inactive state (pwrbf = 0), the bus arbiter 23 sets the dmaack signal to an active state (dmaack = 1), and gives the DMAC 12 a right to use the bus.
[0051]
At timing T5, the DMAC 12 starts reading the address ra corresponding to the second bus 20.
[0052]
At timing T6, the DMAC 12 sets the dmareq signal to an inactive state (dmareq = 0) and cancels the bus use request. The bus arbiter 23 sets the dmaack signal to the inactive state (dmaack = 0), sets the cpuack to the active state (cpuack = 1), and returns the bus use right to the CPU 11.
[0053]
Note that the pwrbf signal and the dmareq signal may be changed at a predetermined timing according to the state transition of the second bus controller 24 or the DMAC 12. As described above, the bus arbitration, IAB output, and IDB input / output are pipelined, and therefore need to be changed in advance of the actual use timing.
[0054]
Therefore, according to the semiconductor integrated circuit device of the first embodiment, while the second bus or the third bus is operating in parallel with the first bus as in the write buffer function, the DMAC is not given a bus use right. By giving the right to use the bus to the CPU, the processing performance of the microcomputer or the like can be improved.
[0055]
(Embodiment 2)
FIG. 4 is a diagram showing a register configuration of a DMAC in a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 5 is a bus arbiter as a bus arbiter in the semiconductor integrated circuit device according to the second embodiment. FIG. 6 is a diagram showing a logical description of a DMAC bus use right request in the semiconductor integrated circuit device of the second embodiment, and FIG. 7 is a semiconductor integrated circuit device of the second embodiment. 3 is a timing chart showing an example of a bus operation.
[0056]
The semiconductor integrated circuit device of the second embodiment is, for example, a microcomputer, and has the same basic configuration as that of the first embodiment shown in FIG. The difference is in the register configuration of the DMAC 12 and the configuration of the bus arbiter 23.
[0057]
First, the register configuration of the DMAC 12 in the second embodiment will be described with reference to FIG. FIG. 4 shows a register configuration for one channel.
[0058]
The register group of the DMAC 12 includes a source address register (SAR) 41, a destination address register (DAR) 42, a transfer counter (TCR) 43, a DMA control register (DMCR) 44, and the like.
[0059]
The source address register (SAR) 41 and the destination address register (DAR) 42 specify the source and destination addresses, respectively. When one data transfer is performed, for example, increment is performed.
[0060]
The transfer counter (TCR) 43 specifies the number of transfers. When the data transfer is performed once, decrement is performed. When the content of the counter becomes 0, the DTE bit of the DMA control register (DMCR) 44 is cleared to 0 and an interrupt request is generated.
[0061]
The DMA control register (DMCR) 44 includes DTE bits, DMAP bits, DMAE bits, SZ1-0 bits, and DTS2-0 bits. The DTE bit permits data transfer of the channel. The DMAP bit is set to 1 when the destination or source address corresponds to the second bus. Similarly, the DMAE bit is set to 1 when the transfer destination or transfer source address corresponds to the third bus. The SZ1-0 bits specify the data transfer size (byte, word, longword). DTS2-0 bits specify the source of the transfer request.
[0062]
In addition, a control register is provided in common to the DMAC, but a detailed description is omitted.
[0063]
Next, the function of the bus arbiter 23 according to the second embodiment will be described with reference to FIG.
[0064]
The bus arbiter 23 inputs the dmap and dmae signals corresponding to the contents of the DMAP bit and the DMAE bit of the DMA control register (DMCR) 44 together with the dmareq signal from the DMAC 12. These indicate that the second bus and the third bus are used in the data transfer of the DMAC 12 to be executed after the bus use right is given.
[0065]
Regarding the bus use right to the DMAC 12, the DMAC 12 requests the bus use right (dmareq = 1) and the DMAC 12 does not use the second bus (dmap = 0), or the write buffer operation is not performed on the second bus. At the time (pwrbf = 0) and when the DMAC 12 does not use the third bus (dmae = 0), or when the write buffer operation is not performed on the third bus (ewrbf = 0), the signal is given (dmaack = 1). The right to use the bus to the CPU 11 is given as a logical inversion of the right to use the bus to the DMAC 12.
[0066]
Next, the function of the DMAC 12 for requesting the right to use the bus will be described with reference to FIG. In this example, it is assumed that the DMAC 12 has two channels (channel 0 and channel 1).
[0067]
As in the conventional case, the DMAC 12 accepts a transfer request signal and determines the priority order between channels when a plurality of transfer requests occur.
[0068]
The bus use right request of the DMAC 12 is the logical sum of the transfer request signals treq0 and treq1 of the channels 0 and 1.
[0069]
If a transfer request is made to two channels at the same time, channel 0 has priority. The signals dmap and dmae output control bits dmap0 or dmap1, dmap0 or dmap1 of the selected channel from the DMAC 12 to the bus arbiter 23 in accordance with the priority of the channel. For example, dmap0 is output from the DMAP bit shown in FIG.
[0070]
Next, an example of the timing of the bus operation in the microcomputer according to the second embodiment will be described with reference to FIG.
[0071]
The following is an example of a case where φE is the 分 frequency division of φI for the first and third buses.
[0072]
When the CPU 11 performs writing to the address wa2 corresponding to the third bus 21 at the timing T1 in the clock φI, the write data wd2 is output at the timing T2, and these are output to EXAB and EXDB of the third bus 21 and A write operation on three buses is performed. In order to perform the write buffer operation, the third bus controller 25 sets the ewrbf signal to an active state (ewrbf = 1). This writing is executed by three clocks φE.
[0073]
On the other hand, the DMAC 12 has already set dmareq to the active state (dmareq = 1) according to channel 0, requests the right to use the bus, and indicates that dmae is inactive (dmae = 0) to indicate that the third bus is not used. . The bus arbiter 23 is executing the write buffer on the third bus, but since the DMAC 12 does not use the third bus 21, the bus arbiter 23 activates dmaack (dmaack = 1) to give the bus use right.
[0074]
The DMAC 12 outputs an address for data transfer (for example, transfer from the RAM 14 to the peripheral function block 15 on the second bus 20) at timings T2 and T3, and performs data input / output at timings T3 and T4.
[0075]
At the timing T3, the DMAC 12 cancels the bus use right request. The bus arbiter 23 sets the dmaack signal to the inactive state (dmaack = 0), sets the cpuack to the active state (cpuack = 1), and returns the bus use right to the CPU 11.
[0076]
The DMAC 12 subsequently sets dmareq to the active state (dmareq = 1) at timing T5 according to channel 1, requests the right to use the bus, and sets dmae to the active state (dmae = 1) to use the third bus 21. Shown. When the ewrbf signal becomes inactive (ewrbf = 0) at the timing T6, the bus arbiter 23 sets dmaack to the active state (dmaack = 1) and gives the right to use the bus.
[0077]
At timing T7, the DMAC 12 starts reading the address ra corresponding to the third bus 21.
[0078]
At timing T8, the DMAC 12 sets the dmareq signal to the inactive state (dmareq = 0) and cancels the bus use right request. The bus arbiter 23 sets the dmaack signal to an inactive state (dmaack = 0), sets the cpuack signal to an active state (cpuack = 1), and returns the bus use right to the CPU 11.
[0079]
Therefore, according to the semiconductor integrated circuit device of the second embodiment, by specifying the control bit of the DMAC, the arbitration of the bus usage right of the bus arbiter can be controlled, and the processing performance of the microcomputer or the like can be improved.
[0080]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0081]
For example, in the above-described embodiment, the DMAC has been described as a data transfer device. However, the present invention is not limited to this, and may be a device called a data transfer controller. It may have an arithmetic function or the like.
[0082]
Also, any device that can acquire the bus use right and use the bus instead of the CPU may be used.
[0083]
Also, a plurality of data transfer devices can be provided on the first bus, and the logical description of the bus arbiter can be easily modified.
[0084]
The information referred to at the time of arbitration of the right to use the bus is not limited to the write buffer function, and may be information indicating that a bus cycle is being executed on the second and third buses. For example, it may include information indicating that another data transfer device is present on the second bus and data transfer of the another data transfer device is being performed. The third bus may also include the release of the right to use the external bus.
[0085]
Also, the method by which the DMAC indicates the bus to be used can be variously modified. In addition to the setting by the control register, the bus to be used may be determined from the address information of the source address register and the destination address register. The signal line and timing for notifying the bus arbiter can also be modified.
[0086]
The bus is divided into three, and may be four or more. The first and second buses may be integrally configured. Only one of the second and third buses may have a write buffer function.
[0087]
Further, the operation timing of the bus, the control signal, and the like can be variously changed.
[0088]
Further, the configuration of the microcomputer is not limited. In addition, various functional blocks and the like can be changed.
[0089]
In the above description, the case where the invention made by the present inventors is mainly applied to a single-chip microcomputer as a technical field to which the invention belongs has been described. However, the present invention is not limited to this, and other semiconductor integrated circuit devices, for example, It is also possible to apply the present invention to a semiconductor integrated circuit device mainly using a digital signal processor (DSP). The present invention can be applied at least to a semiconductor integrated circuit device having a built-in data transfer device connectable to a data processing device.
[0090]
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0091]
(1) While the second bus is performing an operation in parallel with the first bus, such as a write buffer function, the right to use the bus is not given to the data transfer device but to the central processing unit. By giving the instruction, an instruction can be read from the memory on the first bus, and the frequency of occurrence of an undesired standby state is reduced.
[0092]
(2) The frequency of occurrence of an undesired standby state is further reduced by indicating whether or not to use the second bus when the data transfer device requests the bus use right.
[0093]
【The invention's effect】
The frequency of occurrence of an undesired standby state is reduced, and the processing performance of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a logical description of a bus arbiter as bus arbitration means in the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 3 is a timing chart illustrating an example of a bus operation in the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 4 is a diagram showing a register configuration of a DMAC in a semiconductor integrated circuit device according to a second embodiment of the present invention;
FIG. 5 is a diagram showing a logical description of a bus arbiter as bus arbitration means in the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 6 is a diagram showing a logical description of a bus use right request of a DMAC in the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 7 is a timing chart illustrating an example of a bus operation in the semiconductor integrated circuit device according to the second embodiment of the present invention;
[Explanation of symbols]
11 Central processing unit (CPU)
12 DMA controller (DMAC)
13 Read-only memory (ROM)
14. Random access memory (RAM)
15 Peripheral function blocks
16 I / O port (IOP)
17 Bus Controller (BSC)
18 Clock Oscillator (CPG)
19 First bus
20 Second bus
21 Third bus
22 Buffer circuit (BUF)
23 Bus Arbiter
24 Second bus controller
25 Third bus controller
41 Source Address Register (SAR)
42 Destination address register (DAR)
43 Transfer Counter (TCR)
44 DMA control register (DMCR)
dmareq DMAC bus use right request signal
dmack DMAC bus use right approval signal
dmap, dmap0, dmap DMAC second bus use signal
dmae, dmae0, dmae1 DMAC third bus use signal
cpuack CPU bus use right approval signal
ready Ready signal
treq0, treq1 transfer request signal
pwrbf second bus write buffer signal
ewrbf Third bus write buffer signal
ra, wa1, wa2 address
wd1, wd2, r, rd data
φI, φP, φE clock
IAB first bus address
IDB 1st bus data
PAB second bus address
PDB 2nd bus data
EXAB 3rd bus address
EXDB third bus data

Claims (5)

A first bus for transmitting signals between devices;
A central processing unit connected to the first bus;
A data transfer device connected to the first bus;
Bus use right arbitration means for arbitrating the bus use right of the first bus;
A second bus read or written via the first bus,
The semiconductor integrated circuit device according to claim 1, wherein the bus use right arbitrating means changes a bus use right arbitration method according to a state of the second bus. The semiconductor integrated circuit device according to claim 1,
The first bus and the second bus can perform a bus operation in parallel, and when the second bus is executing a bus operation, the central processing unit gives a bus access right to the central processing unit. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1, wherein:
A semiconductor integrated circuit device, wherein a memory for storing a program of the central processing unit is connected to the first bus. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3,
The semiconductor integrated circuit device according to claim 1, wherein the data transfer device notifies the bus use right arbitration unit whether or not to use the second bus when requesting a bus use right. 5. The semiconductor integrated circuit device according to claim 1, 2, 3, or 4,
2. The semiconductor integrated circuit device according to claim 1, wherein the second bus or a functional block connected to the second bus operates with a clock slower than the first bus.

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