JP2002073533A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable bus control corresponding to a bus width for every module regardless of a change in the address location of the module. SOLUTION: A first module (1) is provided with a data transfer control circuit (1A) and second modules (2, 3 and 4) are provided with bus width reporting circuits (2A, 3A and 4A). When bus width information required for data transfer is reported from the second module to the first module, on the basis of the reported bus width information, in the first module, bus control is performed for data transfer to be executed with the second module. Thus, bus control corresponding to the bus width for every module can be performed regardless of a change in the address location of the module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and relates to a technology effective when applied to, for example, a single-chip microcomputer (hereinafter simply referred to as "microcomputer").

[0002]

2. Description of the Related Art In a single-chip microcomputer as an example of a semiconductor integrated circuit, for example,
"LSI Handbook (Pages 540 and 541)" issued by Ohm Co., Ltd. on November 30, 2009
As described above, a ROM (read only memory) for holding a program, a RAM (random access memory) for holding data, and input / output of data centering on a central processing unit (abbreviated as “CPU”) Are formed on one semiconductor substrate such as a single crystal silicon substrate, for example.

The external bus access of such a microcomputer is disclosed, for example, in Japanese Patent Application Laid-Open No. 05-03075.
As described in Japanese Patent Application Laid-Open No. 19, there is known a technique in which an address range to be accessed is determined and an external bus width is switched for each address range.

[0004]

If the bus width of the internal bus is fixed to, for example, an 8-bit width in accordance with a module having a narrow bus width, the bus width is restricted even for a CPU or module having a wide bus width. The performance is impaired.

On the other hand, if a module having a wide bus width is used, for example, an A / D (analog / analog
Even in the case of a (digital) converter, it is necessary to increase the bus width, and the logical scale or the physical scale tends to be wasted compared to the bus width actually used.

[0006] As described in the above-mentioned Japanese Patent Application Laid-Open No. 05-0307519, in a system in which an address range to be accessed is determined and an external bus width is switched for each address range, a module in an address space managed by a CPU is controlled. It is necessary to have a logic for determining the bus width of the relevant bus cycle according to the address arrangement. If this is fixed in hardware, the address judgment is made every time the address arrangement is changed or a new module is added. It is necessary to change the configuration of the circuit. If the data bus width can be set by software using an internal I / O (input / output) register or the like, setting work by software is required.
Moreover, in such a case, if the bus width is to be mixed in a small range such as a unit of 10 bytes, the number of the internal I / O registers increases and the logical scale also increases.

An object of the present invention is to provide a technique for easily connecting a plurality of modules having different bus widths to a common bus regardless of a change in the address arrangement of the modules.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the second module is provided with information notifying means for notifying the first module of bus width information necessary for data transfer with the first module, and the bus width information notified from the second module is provided. Based on the above, the first module is provided with bus control means for performing bus control for data transfer performed with the second module.

In addition, information notifying means for notifying the first module of bus width information necessary for data transfer in response to a request from the first module is provided in the second module, and Requesting bus width information necessary for data transfer, and performing data transfer with the second module based on the bus width information notified from the second module in response to the request. Bus control means for performing bus control is provided in the first module.

According to the above means, when the bus width information required for data transfer is notified from the second module to the first module, the first module transmits the second bus width information based on the notified bus width information. It performs bus control for data transfer with the module. Since the bus control is performed irrespective of the contents of the address map of the module, even if the address arrangement of the module is changed, this does not affect the bus control. Therefore, a plurality of modules having different bus widths can be easily connected to a common bus.

At this time, the bus control means in the first module determines the bus width of data transfer performed with the module and the number of cycles of data transfer in accordance with the bus width information notified from the second module. It is good to adjust.

Further, the first module may be a bus master capable of acquiring the right to use the bus for data transfer.

Further, a plurality of bus masters each capable of acquiring the right to use the bus, a third module for arbitrating bus requests from the plurality of bus masters, and an access control from the bus master via the third module. When the data processing device is configured to include the fourth module, the fourth module has information for notifying the third module of bus width information necessary for data transfer in accordance with a request from the third module. A notifying means is provided, wherein the third module requests the fourth module for bus width information necessary for data transfer, and responds to the request with the bus width information notified from the fourth module. A bus control unit is provided for performing bus control for data transfer performed with the fourth module based on the bus control.

According to the above means, when the bus width information required for data transfer is notified from the fourth module to the third module, the third module, based on the notified bus width information, makes the fourth module. It performs bus control for data transfer with the module. Since the bus control is performed irrespective of the contents of the address map of the module, even if the address arrangement of the module is changed, this does not affect the bus control. Therefore, a plurality of modules having different bus widths can be easily connected to a common bus. Further, by controlling the plurality of bus masters in common by the third module, it is possible to reduce the logical scale and improve the development efficiency.

[0017]

FIG. 1 shows a configuration example of a single-chip microcomputer (hereinafter simply referred to as a "microcomputer") which is an example of a data processing apparatus according to the present invention.

A microcomputer 10 shown in FIG.
Although not particularly limited, it is possible to transfer data in a serial format between four modules, for example, a CPU 1 for performing predetermined arithmetic processing according to a predetermined program, a timer 2 for time measurement, and the outside of the chip. A serial communication interface (SCI) 3, an A / D converter 4 for converting an input analog signal into a digital signal, and a module for mutually connecting the modules so that various signals can be exchanged. The bus BUS is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The timer 2 includes a bus width notifying circuit 2A capable of outputting the bus width information of the own module to the CPU 1 when the module select signal SEL1 from the CPU 1 is asserted. When the module select signal SEL2 is asserted, the A / D converter 4 includes a bus width notification circuit 3A capable of outputting the bus width information of the own module to the CPU 1.
Includes a bus width notification circuit 4A capable of outputting the bus width information of the own module to the CPU 1 when the module select signal SEL4 from the CPU 1 is asserted.

The CPU 1 has a timer 2, an SCI 3, an A / D
For the converter 4, the transaction size information TS and the corresponding module select signals SEL2, SEL
3, SEL4, and in response, timer 2, SC
I3, includes a data transfer control circuit 11A for controlling the width of the data bus included in the bus BUS and the number of data transfer cycles in accordance with the bus width information BS output from the A / D converter 4. Here, “transaction” means a processing unit in the microcomputer 10, and “transaction size” means a size of the processing unit in the microcomputer 10.
Although not particularly limited, the transaction size in the microcomputer 10 is 32 bits (bi).
t), 16 bits, and 8 bits.

The CPU 1 is an example of a first module in the present invention, and the timer 2, SCI 3, A /
The D converter 4 is an example of the second module in the present invention.

FIG. 2 shows an example of coding transaction size information. Although not particularly limited, the transaction size is indicated by 2 bits, 32 bits are “11”, 16 bits are “10”, and 8 bits are “01”.
It is said. The 8-bit bus width module always uses the 7th to 0th bits of the internal bus without referring to the transaction size. The 16-bit bus width module uses the 15th to 0th bits of the internal bus with reference to the first bit of the transaction size (16 bits).
Bit) or whether the 7th to 0th bits are used (8 bits). The 32-bit width module refers to the 1st and 0th bits of the transaction size and uses the 31st to 0th bits of the internal bus (for 32 bits) or the 15th to 0th bits. Use (for 16 bit) or 7
Use bit 0 to bit 0 (8 bits)
Or choose.

FIG. 3 shows the operation timing of the main part of the microcomputer 10.

In this example, the CPU 1, the timer 2, the SC
It is assumed that a transaction for sequentially transferring 32-bit data to I3 and the A / D converter 4 is issued. In this case, a code “11” indicating a 32-bit transaction size is supplied by the CPU 1 to the clock signal C.
Issued in synchronization with LK.

When the CPU 1 first selects the timer 2 by asserting the module select signal SEL2 to the high level, the timer 2 informs the CPU 1 that the bus width of its own module is 16 bits by the bus width information BS. Inform. Thereby, the CPU 1 recognizes that the data transfer to the timer 2 needs to be performed by 16 bits. In this case, the data transfer is 2 for every 16 bits.
It is divided into times. Assuming that each of D0 to D3 is 8-bit data, D0 and D1 are transferred in the first transfer, and D2 and D3 are transferred in the second transfer. At this time, the 15th to 8th bits of the internal bus are used for the transfer of D0 and D2, and the 7th to 0th bits of the internal bus are used for the transfer of D1 and D3.

Next, when SCI3 is selected by the CPU1 asserting the module select signal SEL3 to a high level, the SCI3 informs the CPU1 that the bus width of its own module is 32 bits by the bus width information BS. Inform. As a result, the CPU 1
It recognizes that data transfer to SCI3 can be performed in 32-bit units. In this case, the module select signal SEL
The transaction is completed by performing 32-bit data transfer once while 3 is asserted high. In this case, the transfer of D0 uses the 31st to 24th bits of the internal bus, the transfer of D1 uses the 23rd to 16th bits of the internal bus, and the transfer of D2 uses the internal bus. Of the internal bus are used for the transfer of D3 from the 7th bit to the 0th bit.

Next, when the A / D converter 4 is selected by the CPU 1 asserting the module select signal SEL4 to a high level, the A / D converter 4 is selected.
Informs the CPU 1 that the bus width of its own module is 8 bits by the bus width information BS. Thereby, the CPU 1 recognizes that the data transfer to the A / D converter 4 needs to be performed by 8 bits. In this case, data transfer is performed four times. That is, the transaction is completed by performing the 8-bit data transfer four times in a row while the module select signal SEL4 is asserted at the high level.

Next, a case where a 16-bit transaction is issued will be described.

FIG. 4 shows that the timer 1 and the SCI
3. Operation timings when transactions for sequentially transferring 16-bit data to the A / D converter 4 are issued are shown. In this case, a code “10” indicating a transaction size of 16 bits is issued by the CPU 1 in synchronization with the clock signal CLK.

When the timer 2 is selected by asserting the module select signal SEL2 to a high level by the CPU 1, the timer 2 informs the CPU 1 of the bus width of the own module by the bus width information BS. . As a result, the CPU 1
It recognizes that the data transfer to can be performed by 16 bits.
In this case, the transaction is completed by performing the 16-bit data transfer once while the module select signal SEL2 is asserted to the high level. For transfer of D0, 15 to 8 on the internal bus BUS
The bit number is used, and the 7th to 0th bits on the internal bus BUS are used for the transfer of D1.

Next, when SCI3 is selected by the CPU1 asserting the module select signal SEL3 to the high level, the SCI3 informs the CPU1 that the bus width of its own module is 32 bits by the bus width information BS. Inform. As a result, the CPU 1
It recognizes that data transfer to SCI3 can be performed in 16-bit units. In this case, the module select signal SEL
The transaction is completed by performing the 16-bit data transfer once while 3 is asserted to the high level. The D0 transfer uses the 15th to 8th bits of the internal bus BUS, and the D1 transfer uses the 7th to 0th bits of the internal bus BUS.

Next, when the A / D converter 4 is selected by the CPU 1 asserting the module select signal SEL4 to a high level, the A / D converter 4 is selected.
Informs the CPU 1 that the bus width of its own module is 8 bits by the bus width information BS. Thereby, the CPU 1 recognizes that the data transfer to the A / D converter 4 needs to be performed by 8 bits. In this case, data transfer is performed twice. That is, the transaction is completed by performing the 8-bit data transfer twice consecutively while the module select signal SEL4 is asserted at the high level. For the transfer of D0, the 15th to 8th bits in the internal bus BUS are used.
The 7th to 0th bits in the internal bus BUS are used for the transfer of 1.

Next, a case where an 8-bit transaction is issued by the CPU 1 will be described.

FIG. 5 shows that the timer 1 and the SCI
3. Operation timings when transactions for sequentially transferring 8-bit data to the A / D converter 4 are issued are shown. In this case, a code “01” indicating the transaction size of 8 bits is issued by the CPU 1 in synchronization with the clock signal CLK.

When the timer 2 is selected by asserting the module select signal SEL2 to a high level by the CPU 1, the timer 2 informs the CPU 1 of the own module bus width by using the bus width information BS of 16 bits. . As a result, the CPU 1
It recognizes that the data transfer to can be performed by 8 bits. In this case, the transaction is completed by performing the 8-bit data transfer once while the module select signal SEL2 is asserted at the high level.
For the transfer of D0, the 7th to 0th bits on the internal bus BUS are used.

Next, when SCI3 is selected by the CPU1 asserting the module select signal SEL3 to the high level, the SCI3 informs the CPU1 that the bus width of its own module is 32 bits by the bus width information BS. Inform. As a result, the CPU 1
It recognizes that data transfer to SCI3 can be performed in 8-bit units. In this case, the module select signal SEL3
The transaction is completed by performing the 8-bit data transfer once during a period in which is asserted to the high level. The transfer of D0 requires 7 on the internal bus BUS.
The 0th bit is used.

Next, when the A / D converter 4 is selected by the CPU 1 asserting the module select signal SEL4 to a high level, the A / D converter 4 is selected.
Informs the CPU 1 that the bus width of its own module is 8 bits by the bus width information BS. Thereby, the CPU 1 recognizes that the data transfer to the A / D converter 4 needs to be performed by 8 bits. In this case, data transfer is performed twice. That is, the transaction is completed by performing the 8-bit data transfer once while the module select signal SEL4 is asserted at the high level. Internal bus B for transfer of D0
Bits 7-0 in the US are used.

According to the above example, the following functions and effects can be obtained.

Each module such as the timer 2, the SCSI 3, and the A / D converter 4 has a bus width notification circuit 2 A, 3 for notifying the CPU 1 of bus width information necessary for data transfer.
A and 4A are provided, and bus width information necessary for data transfer is notified to the CPU 1 in response to a request from the CPU 1, and the data bus width and the number of bus cycles are adjusted by the CPU 1 accordingly. Therefore, timer 2, S
Even though the data bus width of each module such as the CI 3 and the A / D converter 4 is different from each other, it is possible to connect them to a common internal bus without changing the circuit configuration of the module. Yes, in that case,
Data transfer can be performed with a bus width and the number of bus cycles according to each module.

FIG. 6 shows another example of the configuration of the microcomputer. 6, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals.

The microcomputer 10 shown in FIG.
Although it is not particularly limited, it is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The microcomputer 10 includes a central processing unit (CPU) 14, a direct memory access controller (DMAC) 16, and a read only memory (RO).
M) 12, random access memory (RAM) 11, clock oscillator 13, timer 2, serial communication interface (SCI) 3, A / D converter 4, input / output ports (IOP) A to F and IOP 1 to IOP 5,
It includes functional blocks or modules of the interrupt controller 19, the bus controller 15, and the clock oscillator 13, which are communicably connected by an internal bus. The bus controller 15 includes an external bus controller 152 and an internal bus controller 1.
53.

Terminals EXTAL and X of clock oscillator 13
The microcomputer 10 operates in synchronization with a reference clock (system clock) generated based on a crystal oscillator connected to TAL or an external clock input to an EXTAL terminal. One cycle of this reference clock is called a state.

Operation mode input terminals MD0, MD1, MD
2, the operation mode of the microcomputer 10 is designated. The operation mode includes designation of an address space of the CPU 1.

The DMAC 16 shares a bus with the CPU 14, and performs data transfer on behalf of the CPU 14. The data transfer by the DMAC 16 can be performed at high speed because the data transfer does not go through the CPU 14.

The internal bus of the microcomputer 10 is not particularly limited, but is not limited to an address bus and a data bus, but not shown, a bus right request signal, a bus acknowledge signal, a bus command, a transaction size, an external bus command, a ready Signals, external bus ready signals, read signals / write signals, bus size signals, transmission paths of various signal lines such as a system clock are included. Further, the internal address bus includes two buses as indicated by IAB and PAB. The internal data bus includes two buses as indicated by IDB and PDB. These internal buses are connected to the bus controller 15
Interfaced by

The internal address bus IAB and the internal data bus IDB correspond to the CPU 14, the DMAC 16, the ROM 1
2, the RAM 11, the bus controller 15, and the internal address bus IAB is connected to the input / output ports IOPA to IO
The internal data bus IDB is connected to an external data bus via input / output ports IOPD and IOPE.

The internal address bus PAB and the internal data bus PDB are connected to the bus controller 15, the timer 2, the SCI
3, the A / D converter 4, the interrupt controller 19, and the input / output ports IOPA to IOPF and IOP1 to IOP5.

Only the CPU 14 and the DMAC 16 can use the internal bus as an internal bus master.
The bus controller 15 has a function as a bus arbiter, and the bus contention between the CPU 14 and the DMAC 16 is determined in accordance with the respective bus right request signals.
Arbitrated by The bus right for the external bus is arbitrated by the bus controller 15.

ROM 12, RAM 11, timer 2,
SCI3, A / D converter 4, IOPA to IOPF and I
Each of the modules OP1 to IOP5 and the interrupt controller 19 is read or written by the CPU 14 or the DMAC 16 as an internal bus slave.

The data bus width of the internal bus is 32 bits, and the RAM 11 and the ROM 12 can be read or written in one state of 8 bits or 16 bits to 32 bits.

The timer 2, SCI 3, A / D converter 4, IOPA to IOPF and IOP1 to IOP5, and the clock oscillator 13 have built-in control registers, and these control registers are collectively referred to as internal I / O registers. Such an internal I / O register can be read or written in two states.

The outline of other functions in the microcomputer 10 is as follows.

The interrupt controller 19 has a timer 2,
SCI3, A / D converter 4, I / O ports IOPA-I
The OPF and the interrupt signals output from IOP1 to IOP5 are fetched, and based on the designation of a predetermined register or the like,
An interrupt request signal is output to the CPU 14 and DM
An activation request signal is output to AC16. Also, D
It takes in a clear signal output from the MAC 16 and outputs an interrupt clear signal. Note that these interrupt signals and the like are omitted in the drawing.

When a CPU interrupt request is generated, CP
U14 interrupts the currently executing process, branches to a predetermined processing routine through an exception processing state including an operation of saving the internal state to the stack, performs a desired processing, and then clears an interrupt factor. Or At the end of the predetermined processing routine, a normal return instruction is placed, and by executing this instruction, the previously interrupted processing is resumed.

Input / output ports IOPA to IOPF and IO
P1 to IOP5 are also used as external bus signals and input / output signals of input / output circuits. IOPA to IOPC are used for address bus output, IOPD and IOPE are used for data bus input / output, and IOPF is also used for bus control signal input / output. External addresses and external data are connected to internal address buses IAB and IDB via buffer circuits included in these input / output ports, respectively. The internal address bus PAB and the internal data bus PDB are used to read or write the register of the input / output port,
There is no direct relationship with the external bus. Although not shown in the drawing, the output bus control signals include an address strobe, a data strobe, a read strobe, a write strobe, and a bus acknowledge signal, and the input bus control signals include a wait signal, a bus request. There are signals. The extension of the external bus is selected depending on an operation mode or the like.

IOP1 is a timer input / output, IOP2
Is a pulse output, IOP3 is an SCI input / output, IOP4 is an analog input, and IOP5 is also used as a DMAC input / output. There are input / output signals for the DMAC 16, the timer 2, the SCI 3, the A / D converter 4, and the IOPs 1 to 5, internal interrupt request signals, and the like, but these are omitted in the drawing.

In addition, power supply terminals Vcc, Vss, analog power supply terminals AVcc, AVss, reset input RES,
Standby input STBY, interrupt input NMI, clock inputs EXTAL and XTAL, operation mode inputs MD0 and M
There are input terminals such as D1 and MD2. Based on input signals from the operation mode input terminals MD0, MD1, MD2,
An operation mode of the CPU (such as a maximum mode) and an operation mode of the microcomputer (such as an external bus expansion mode) are set.

When the reset signal RES is given to the microcomputer 10 having the above configuration, the main functions of the microcomputer 10 including the CPU 14 are reset. When this reset is released, CP
U14 reads a start address from a predetermined address, and executes reset exception processing to start reading an instruction from the start address. After that, the CPU 14
Reads data from the ROM 12 or the like sequentially and decodes the data to process data.
1. Data transfer with timer 2, SCI3, input / output port, etc. That is, the CPU 14 includes an input / output port,
Data input from A / D converter or SCI
3 and the like, while performing processing based on the instructions stored in the ROM 12 and the like, and outputting a signal to the outside via the input / output port based on the result, various external Control the equipment.

FIG. 7 shows a main part of the microcomputer 10 shown in FIG.

The CPU 14 and the DMAC 16, which is another internal bus master, exclusively use the internal data bus IDB,
And exclusively use the internal address bus IAB. Therefore, the internal bus controller 153 is provided with an arbitration circuit 153 for arbitrating the bus right. CPU 14 and DM
When the bus right request conflicts with the AC 16, the arbitration circuit 153 arbitrates the bus right, and the CPU 14
The right to use the bus is given to one of the MACs 16. Thus, the bus master that has acquired the bus right can access the module using the bus. The internal bus controller 153 checks the contents of the internal address bus IAB, and if it is an access to the RAM 11, controls the internal data bus IDB and the internal address bus IAB. Also, the internal bus controller 153 checks the contents of the internal address bus IAB, and if it is an access of the timer 2, the SCI 3, or the A / D converter 4, the internal data bus PDB and the internal address bus PAB
And activates the bus ready signal to cause the internal bus master to wait. Further, the internal bus controller 15
3 includes a data transfer control circuit 153B for performing bus control in data transfer. The data transfer control circuit 153B has the same function as the data transfer control circuit 1A shown in FIG. That is, timer 2, S
CI3, transaction size information TS for A / D converter 4, and corresponding module select signal SE
L2, SEL3, and SEL4 are supplied, and in response to the bus width information BS output from the timer 2, the SCI 3, and the A / D converter 4, the width of the data bus included in the bus BUS and the data transfer cycle are supplied. Control the number. In this case, the transaction size information TS and the module select signals SEL2, SEL3, SEL4, etc.
It is transmitted by being included in internal address bus PAB.

When a plurality of bus masters such as the CPU 14 and the DMAC 16 are provided, the internal bus controller 1 having a bus arbitration function is provided.
53, a data transfer control circuit 153B is provided, and the data transfer control circuit 153B
According to the data bus width of each module such as the A / D converter 4, data transfer can be performed at timings as shown in FIGS. 3 to 5, thereby obtaining the same operation and effect as in the above example. be able to. Since the data transfer control circuit 153B is provided in the internal bus controller 153 as described above, it is not necessary to separately provide a data transfer control circuit in the CPU 14 or the DMAC 16.

Here, the internal bus controller 153
Is an example of the third module in the present invention,
The timer 2, the SCI 3, and the A / D converter 4 are an example of a fourth module in the present invention.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, in the above example, the timer 2, the SCI
3, the data bus width and the number of data transfer cycles are controlled based on the data bus width information notified from each module such as the A / D converter 4. However, the timer 2, the SCI 3, and the A / D The address bus width information may be notified from each module such as the D converter 4 and the width of the address bus may be controlled based on the information.

The maximum bus width accessed by the CPU 14 and the maximum bus width accessed by the DMAC 16 may be different. For example, the maximum bus width accessed by the CPU 14 is 16 bits,
A case is considered in which the maximum bus width accessed by the AC 16 is 32 bits.

Further, in the above example, the timer 2, the SCI
3. Although the bus width notification circuit is built in the A / D converter 4, the present invention is not limited to this, and the bus width notification circuit can be built in another module.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer, which is the field of application, has been described. However, the present invention is not limited to this.
It can be widely applied to various data processing devices.

The present invention can be applied on the condition that at least a plurality of modules are included.

[0070]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when including the first module and the second module capable of exchanging data with the first module, the bus width information necessary for data transfer is transmitted from the second module to the first module. When notified,
In the first module, bus control for data transfer with the second module is performed based on the notified bus width information, and the bus control is independent of the contents of the address map of the module. Therefore, even if the address arrangement of the module is changed, this does not affect the bus control. For this reason, a plurality of modules having different bus widths can be easily connected to a common bus regardless of a change in the address arrangement of the modules.

A plurality of bus masters capable of acquiring the right to use the bus, a third module for arbitrating bus requests from the plurality of bus masters, and a third module capable of controlling access from the bus master via the third module. When the bus width information required for data transfer is
When notified from the module to the third module, the third module performs bus control for data transfer with the fourth module based on the notified bus width information. Is performed irrespective of the contents of the address map of the module. Therefore, even if the address arrangement of the module is changed, this does not affect the bus control. Therefore, a plurality of modules having different bus widths can be easily connected to a common bus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a microcomputer that is an example of a data processing device according to the present invention.

FIG. 2 is an explanatory diagram of a coding example of a transaction size handled by the microcomputer.

FIG. 3 is an operation timing chart of a main part in the microcomputer.

FIG. 4 is another operation timing chart of a main part in the microcomputer.

FIG. 5 is another operation timing chart of a main part in the microcomputer.

FIG. 6 is a block diagram showing another configuration example of the microcomputer.

FIG. 7 is a block diagram showing an example of a configuration of a main part in the microcomputer shown in FIG.

[Explanation of symbols]

 1, 14 CPU 1A, 153B Data transfer control circuit 2 Timer 2A, 3A, 4A Bus width notification circuit 3 SCI 4 A / D converter 10 Microcomputer BUS bus IAB, PAB Internal address bus IDB, PDB Internal address bus

Claims (5)

[Claims] 1. A data processing device in which a first module and a second module capable of exchanging data with the first module are connected via a bus, wherein the second module comprises: An information notifying unit for notifying the first module of bus width information necessary for data transfer, wherein the first module communicates with the second module based on the bus width information notified from the second module. A data processing device comprising bus control means for performing bus control for data transfer performed between the devices. 2. A data processing device comprising a first module and a plurality of second modules capable of exchanging data between the first module and a plurality of second modules, the two modules being connected via a bus. Includes information notifying means for notifying the first module of bus width information necessary for data transfer in accordance with a request from the first module, wherein the first module performs data transfer to the second module. A bus that requests necessary bus width information and performs bus control for data transfer with the second module based on the bus width information notified from the second module in response to the request. A data processing device comprising control means. 3. The bus control means in the first module adjusts the bus width of data transfer performed with the module and the number of data transfer cycles in accordance with the bus width information notified from the second module. Claim 1
Or the data processing device according to 2. 4. The data processing device according to claim 1, wherein said first module is a bus master capable of acquiring a right to use said bus for data transfer. 5. A plurality of bus masters each capable of acquiring a right to use the bus, and a third bus for arbitrating bus requests from the plurality of bus masters.
A data processing apparatus comprising: a module; and a fourth module that can be controlled to be accessed by the bus master via the third module, wherein the fourth module has a bus required for data transfer according to a request from the third module. An information notifying means for notifying the third module of the width information, wherein the third module requests the fourth module for bus width information necessary for data transfer, and responds to the request. A data processing apparatus, comprising: a bus control unit that controls a bus for data transfer performed with the fourth module based on the bus width information notified from the fourth module.