JP2015222487A - DMA controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency in a structure comprising two or more buses.SOLUTION: A DMA controller 50 for transferring data from a source address to a destination address comprises: master ports P1-P4 disposed corresponding to buses, and respectively connected to corresponding buses; an address table 514 for associating addresses of modules connected to the buses with the connected buses and storing them; an identification part 512 for identifying a transfer source bus to which the module of the source address belongs, and a transfer destination bus to which the module of the destination address belongs, by referring to the address table 514; and a transfer control part 502 for setting a path for transferring the data from the source address to the destination address, to the transfer source bus, the master port connected to the transfer source bus, the master port connected to the transfer destination bus, and the transfer destination bus.

Description

  The present invention relates to a DMA controller that transfers data by a DMA (Direct Memory Access) method.

  For example, when a system is constructed by a CPU (Central Processing Unit) as a bus master and a plurality of bus slaves that provide various functions, they are not connected by a single bus. The main reason is that the data transfer performance differs for each bus slave. For this reason, a bus slave with high transfer performance, a CPU and a DMA controller are connected to a high-speed bus, a bus slave with low transfer performance is connected to a low-speed bus, and the high-speed bus and low-speed bus are connected by a bus bridge. Is common.

In this configuration, when data is DMA-transferred, the DMA controller occupies the high-speed bus because DMA transfer is controlled via the high-speed bus even though the transfer is completed by the low-speed bus. For this reason, data transfer by the CPU cannot be executed, and the utilization efficiency of the high-speed bus is reduced.
Therefore, a technique is known in which when the DMA transfer is completed with a low-speed bus, the high-speed bus is disconnected and the processing in the DMA controller is transferred to the bus bridge (see Patent Document 1). In this technology, the data transfer that is completed by the low-speed bus is executed by the bus bridge. As a result, the DMA controller executes another transfer process, thereby preventing a reduction in the utilization efficiency of the high-speed bus.

Japanese Patent No. 3328246

  However, in the above technique, data transfer using both the high-speed bus and the low-speed bus via the bus bridge is limited by the transfer performance of the low-speed bus. In other words, the high-speed bus cannot transfer data at a speed higher than that of the low-speed bus, although it can transfer data at a higher speed. For this reason, the occupation time of the high-speed bus becomes long, and there is a problem that the efficiency when viewed in the whole system is lowered.

  On the other hand, in recent years, SoC (System on Chip) specialized for a specific application by integrating a plurality of functions (bus slave as a module) required for one semiconductor chip is known. The transfer performance of bus slaves required for SoC is very diverse, and it is required to improve the efficiency of data transfer using a plurality of types of buses. For this reason, a large number of three or more buses must be prepared as buses. However, in the above technique, only two types of buses are assumed in the first place.

  The present invention has been made in view of such circumstances, and one of its purposes is to provide a DMA controller that improves data transfer efficiency in a configuration having three or more buses having different transfer performances. It is to provide.

  In order to achieve the above object, a DMA controller according to an aspect of the present invention is a DMA controller that transfers data from a source address to a destination address, and is provided corresponding to at least three buses, A master port connected to the corresponding bus, an address table that stores the address of the module connected to the bus in association with the connected bus, a transfer source bus to which the module of the source address belongs, A specifying unit that specifies a transfer destination bus to which the module of the destination address belongs by referring to the address table, a path for transferring data from the source address to the destination address, the transfer source bus, the transfer Master port connected to former bus, front Connected master port to the destination bus, and characterized by comprising a transfer control unit for setting the transfer destination bus.

  According to the DMA controller according to the above aspect, data from the source address to the destination address is directly transferred from the transfer source bus to the transfer destination bus. Therefore, according to the above aspect, in a configuration having three or more buses, data can be transmitted in the shortest path without passing through a bus between the transfer source bus and the transfer destination bus or a bus bridge between the buses. Since the data is transferred, the data transfer speed can be improved.

In the one aspect, it is preferable that at least two or more master ports provided corresponding to the three or more buses are configured to transfer data to buses corresponding to the master ports in different transfer bands. Here, the transfer band refers to the amount of data that can actually be transferred in a unit time, and is mainly determined by the bus width, operating frequency, and latency (delay).
In the above aspect, the three or more buses may be connected in series via a bus bridge.
Here, for example, if there are four buses from the first bus to the fourth bus, the bus bridge is connected between the first bus and the second bus, and the second bus and the second bus. A bus bridge is provided between the three buses and a bus bridge is provided between the third bus and the fourth bus, respectively, so that data can be transferred between the buses.

  In the one aspect, it is preferable that the master port is a set of a read master port and a write master port. According to this configuration, read transfer via the read master port and write transfer via the write master port can be executed on the same bus, so that the efficiency of the entire system including the DMA controller can be improved.

In the above aspect, when the transfer source bus and the transfer destination bus are the same, the data read-transferred through the read master port of the transfer source bus is write-transferred through the write master port of the transfer destination bus. It is good also as a structure made.
When the three or more buses are connected in series via a bus bridge, and the transfer destination bus is a bus connected to the transfer source bus via the bus bridge, the transfer source bus Alternatively, data may be transferred via a master port corresponding to one of the transfer destination buses and the bus bridge.

In the above aspect, the transfer control unit has a plurality of transfer channels to which a function of data transfer is assigned, and the transfer control unit assigns one transfer channel to one transfer channel from one source address. When data transfer to the destination address is assigned, the read master port connected to the transfer source bus to which the module with the one source address belongs and the transfer destination bus to which the module with the one destination address belongs If the assigned write master port is not set as a data transfer path by another transfer channel, the assigned data transfer may be permitted to the one transfer channel.
According to this configuration, one transfer channel to which data transfer is assigned performs data transfer unless the read master port and the write master port are used for other transfer channels.

It is a figure which shows the structure of the system containing the DMA controller which concerns on embodiment. It is a block diagram which shows the structure of a DMA controller. It is a figure which shows an example of the address table in a DMA controller. It is a flowchart which shows operation | movement of a DMA controller. It is a figure which shows an example of the data transfer path | route in a system. It is a figure which shows an example of the transfer path | route set in the DMA controller. It is a figure which shows an example of the data transfer path | route in a system. It is a figure which shows an example of the transfer path | route set in the DMA controller. It is a figure which shows an example of the transfer path | route set in the DMA controller. It is a figure which shows an example of the transfer path | route set in the DMA controller. It is a figure which shows an example of the transfer path | route set in the DMA controller. It is a figure which shows the example of the data transfer path | route in the DMA controller of a comparative example.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a system 1 including a DMA controller 50 according to the embodiment.
As shown in this figure, the system 1 includes a bus (A) 110, a bus (B) 120, a bus (C) 130 and a bus (D) 140, and a DMA controller 50 connected to each of these buses. The bus bridges 12, 23, and 34 for connecting the buses to each other, and one or a plurality of modules are connected to each bus as follows.

  That is, a CPU 112, a moving picture decoder 114, a rendering engine 116, and an SRAM (Static Random Access Memory) 118 are connected to the bus (A) 110, and a DRAM (Dynamic Random Access Memory) 122, and Even when the power is cut off, a nonvolatile memory 124 that holds stored data is connected. A sound circuit (sound source) 132 is connected to the bus (C) 130, and an SPI (Serial Peripheral Interface) 142, an I2C (Inter-Integrated Circuit) 144, a GPIO (General Purpose Input) is connected to the bus (D) 140. / Output) 146 and ROM (Read Only Memory) 148 are connected.

  Although details of the DMA controller 50 will be described later, each of the master ports P1 to P4 corresponds to each of the buses, and each of the master ports P1 to P4 includes a read master port denoted as “R” and “W”. Each has a pair with a light master port written as. Of the master ports P1 to P4, the master port P1 corresponds to the bus (A) 110. Similarly, the master ports P2, P3, and P4 include the bus (B) 120, the bus (C) 130, and the bus (D). 140.

On the other hand, each of the bus (A) 110, the bus (B) 120, the bus (C) 130, and the bus (D) 140 is a read bus that transfers data read from a module at a specified address (source address). And two independent unidirectional buses each having a write bus for transferring data to be written to a designated address (destination address).
Note that the operating frequencies (transfer rates) in each bus are different from each other. In the example in the figure, the bus transfer speed is ascending order.
Bus (B) 120> Bus (A) 110> Bus (C) 130> Bus (D) 140
It has become.

  Each of the bus (A) 110, the bus (B) 120, the bus (C) 130, and the bus (D) 140 is provided with two points Ap for accessing the DMA controller 50. One of the two points Ap is connected to the read master port of the corresponding master port, and the other is connected to the write master port.

  The bus bridge 12 converts the bus access between the bus (A) 110 and the bus (B) 120 in both directions. Similarly, the bus bridge 23 provides bidirectional bus access between the bus (B) 120 and the bus (C) 130, and the bus bridge 34 provides bidirectional bus access between the bus (C) 130 and the bus (D) 140. Convert. In this way, the bus (A) 110, the bus (B) 120, the bus (C) 130, and the bus (D) 140 are connected in series via the bus bridge.

FIG. 2 is a block diagram showing a configuration of the DMA controller 50.
As shown in the figure, in addition to the master ports P1 to P4 described above, the DMA controller 50 includes a transfer control unit 502, a selection unit 504, a specifying unit 512, an address table 514, and DMA channels (transfer channels) Ch0 to Ch15. including.

When the transfer control unit 502 receives a DMA transfer command from the CPU 112, the transfer control unit 502 executes processing described later to control each part of the DMA controller 50 or set each part.
Each of the DMA channels Ch0 to Ch15 buffers the data read from the source address in a FIFO (Fast In Fast Out) memory (not shown) and transfers it to the destination address according to the control by the transfer control unit 502. To do. At this time, the path from the read master port to the input end of the DMA channel and the path from the output end of the DMA channel to the write master port are set by the selection unit 504 according to the control of the transfer control unit 502, respectively.

  The selection unit 504 connects the input / output terminals of each of the DMA channels Ch0 to Ch15 and the read master port and the write master port of the master ports P1 to P4 to set a path in the DMA controller 50. The configuration for storing information necessary for the transfer control unit 502 to set a route is the address table 514. The configuration for identifying the necessary information from the address table 514 and notifying the transfer control unit 502 is the identifying unit. 512.

FIG. 3 is a diagram illustrating an example of the contents of the address table 514. As shown in this figure, in the address table 514, the address range of the connected module is associated with each of the bus (A) 110, the bus (B) 120, the bus (C) 130, and the bus (D) 140. Is remembered. For this reason, the identifying unit 512 refers to the address table 514 to identify which bus the module of the designated address is connected to.
Note that the CPU 112 is a module for instructing DMA transfer, and the CPU 112 itself is not a target of DMA transfer, and thus is not described in the address table 514.

  Next, the operation of the DMA controller 50 will be described with reference to the drawings.

FIG. 4 is a flowchart showing the control contents of the transfer control unit 502 in the DMA controller 50.
First, when receiving a DMA transfer instruction, the transfer control unit 502 determines whether there is an unallocated channel (empty channel) among the DMA channels Ch0 to Ch15, that is, whether there is a DMA channel not involved in the DMA transfer. It discriminate | determines (step Sa11). If the transfer control unit 502 determines that there is no free channel (if the determination result in step Sa11 is “No”), the transfer control unit 502 returns the processing procedure to step Sa11. For this reason, the transfer control unit 502 waits (queues) the DMA transfer instruction in step Sa11 until an empty channel is generated.
Since the DMA channel that has completed the DMA transfer is deallocated as described later, even if there is no empty channel when the DMA transfer command is received and the determination result is initially “No”, in step Sa11 If you are waiting, you will eventually turn to “Yes”.

  If the transfer control unit 502 determines that there is an empty channel (if the determination result of step Sa11 is “Yes”), the transfer control unit 502 assigns one of the empty channels as a channel for executing the DMA transfer instruction (step Sa12). ).

  Next, the transfer control unit 502 notifies the specifying unit 512 of the source address and the destination address related to the DMA transfer instruction, and instructs the specification of the transfer source bus and the transfer destination bus (step Sa13). . With this instruction, the specifying unit 512 refers to the address table 514, specifies the bus corresponding to the source address as the transfer source bus, specifies the bus corresponding to the destination address as the transfer destination bus, and transfers the transfer control unit 502. Return to

The transfer control unit 502 determines whether the assigned DMA channel is capable of DMA transfer using the transfer source bus and the transfer destination bus specified by the specifying unit 512 (step Sa14).
Specifically, if the transfer control unit 502 is used for DMA transfer by a DMA channel other than the DMA channel assigned by at least one of the read master port of the transfer source bus and the write master port of the transfer destination bus, It is determined that DMA transfer by the assigned DMA channel is not possible (the determination result of step Sa14 is “No”), and the processing procedure is returned to step Sa14. Even if it is determined that the DMA transfer is impossible, the read master port and the write master port are not used when the DMA transfer by another DMA channel is completed. For this reason, even if the determination result in step Sa14 is initially “No”, if the process waits in step Sa14, it will eventually turn to “Yes”.

If the transfer control unit 502 determines that the DMA transfer by the assigned DMA channel is possible (if the determination result of step Sa14 is “Yes”), the transfer control unit 502 causes the selection unit 504 to set the following route: (Step Sa15).
That is, the transfer control unit 502 includes a path connecting the input end of the assigned DMA channel and the read master port of the transfer source bus, and a path connecting the output end of the DMA channel and the write master port of the transfer destination bus. Are set in the selection unit 504. The selection unit 504 sets a route according to this control.

  When the transfer control unit 502 causes the selection unit 504 to set a route, the transfer control unit 502 instructs the DMA transfer to the assigned DMA channel (step Sa16). As a result, the DMA channel starts DMA transfer of data related to the DMA transfer command.

The transfer control unit 502 determines whether or not the DMA transfer by the assigned DMA channel has been completed (step Sa17).
If the transfer control unit 502 determines that the DMA transfer by the assigned DMA channel is in progress (if the determination result of step Sa17 is “No”), the transfer control unit 502 returns the processing procedure to step Sa17. That is, the transfer control unit 502 stands by in step Sa17 until the DMA transfer is completed.
On the other hand, if it is determined that the DMA transfer by the allocated DMA channel has been completed (if the determination result of step Sa17 is “Yes”), the transfer control unit 502 cancels the allocation of the DMA channel (step Sa18). Thus, when the next DMA transfer command is received, the DMA channel can be allocated and the next DMA transfer can be executed.

  After step Sa18, the transfer control unit 502 ends the process when the DMA transfer command is received. The transfer control unit 502 executes the processing shown in FIG. 4 every time it receives a DMA transfer command.

Next, a specific example of DMA transfer will be described. FIG. 5 is a diagram showing an example of a data path by DMA transfer, and is set assuming the following conditions. Specifically, in this example, it is assumed that DMA transfer is assigned to the DMA channel Ch0 (step Sa12) because the DMA channel Ch0 is not assigned in the DMA transfer instruction (step Sa11). .
In the DMA transfer instruction, it is assumed that the module (transfer source) indicated by the source address is the ROM 148, and the module (transfer destination) indicated by the destination address is the SRAM 118. In this case, the specifying unit 512 refers to the address table 514 to specify that the transfer source bus corresponding to the source address is the bus (D) 140, and the transfer destination bus corresponding to the destination address is the bus (A ) 110 (step Sa13).

  Here, if both the read master port of the master port P4 and the write master port of the master port P1 are not used in other DMA channels (if the determination result in step Sa14 is “Yes”), FIG. 6, the input end of the DMA channel Ch0 is connected to the read master port of the master port P4, the output end of the DMA channel Ch0 is connected to the write master port of the master port P1, and the transfer in the DMA controller 50 is performed. A route is set (step Sa15).

When a transfer instruction is given to the DMA channel Ch0 in the state where the transfer path is set in this way, the DMA channel Ch0 sends the data read from the ROM 148 to the ROM 148 → bus (as shown in FIGS. 5 and 6). D) Read transfer is performed by a route of 140 → read master port of the master port P4 → DMA channel Ch0 (FIFO memory), and temporarily accumulates in the FIFO memory. For this reason, in the DMA transfer, the reading from the ROM 148 is determined by the reading speed of the ROM 148 or the transfer speed of the bus (D) 140 and is not affected by the transfer speed of other buses.
On the other hand, after accumulation, the DMA channel Ch0 transfers the data read from the FIFO memory through a path of DMA channel Ch0 (FIFO memory) → write master port of the master port P1 → bus (A) 110 → SRAM 118. Therefore, in the DMA transfer, the writing to the SRAM 118 is determined by the writing speed of the SRAM 118 or the transfer speed of the bus (A) 110, and is not affected by the transfer speed of other buses.

  When the DMA transfer through such a path is completed (when the determination result at step Sa17 is “Yes”), the assignment of the DMA channel Ch0 is released (step Sa18). Thereby, when another DMA transfer instruction is issued, the DMA channel Ch0 can be allocated.

  Next, the superiority of the DMA controller 50 according to this embodiment will be described in comparison with a conventional DMA controller.

  FIG. 12 is a diagram illustrating a configuration of a system including a DMA controller according to a comparative example. As shown in the figure, the DMA controller 52 according to the comparative example is configured to be connected to only one bus, that is, the bus (C) 130 in this example. In such a configuration, when the DMA controller 52 is used as a reference, the read latency (delay) increases as the transfer source bus slave is farther away, so the bus occupation time for reading becomes longer. Similarly, if the module of the transfer destination (write destination) is far away, the write latency increases accordingly, and the bus occupation time for writing becomes longer. As the bus occupation time increases, the access latency of the other bus master (CPU 112) also increases, and the efficiency of the entire system decreases.

  The read transfer performance includes the read performance of the transfer source bus slave, the transfer performance of the bus to which the bus slave is connected, the bus to which the DMA controller 52 is connected, and the bus through the middle. It will be limited to the lowest bus. Similarly, the write transfer performance includes the write performance of the transfer destination bus slave, the bus to which the bus slave is connected, the bus to which the DMA controller 52 is connected, and the bus through the middle. The speed is limited to the bus with the lowest performance.

For example, in this comparative example, when the DMA controller 52 performs DMA transfer from the ROM 148 to the SRAM 118, a path of ROM 148 (read port) → bus (D) 140 → bus bridge 34 → bus (C) 130 (→ DMA controller 52). Read data with. When the read performance of the ROM 148 is sufficiently fast, the read transfer performance on this path is limited by the transfer performance of the lower bus (D) 140 even if the transfer performance of the bus (C) 130 is high.
Similarly, the DMA controller 52 performs data transfer via the path (DMA controller 52 →) bus (C) 130 → bus bridge 23 → bus (B) 120 → bus bridge 12 → bus (A) 110 → SRAM 118 (write port). Write. When the write performance of the SRAM 118 is sufficiently fast, the transfer performance of the write on this path is the transfer of the lower bus (C) 130 even if the transfer performance of the bus (A) 110 and the bus (B) 120 is high. Limited by performance.

On the other hand, in the DMA controller 50 according to the present embodiment, only the transfer source bus is used as the data read path and only the transfer destination bus is used as the data write path. However, the write transfer performance is not limited by the transfer performance of other buses.
This will be explained with reference to the DMA transfer of the path shown in FIG. 5. Only the transfer source bus (D) 140 is used as the data read path. Therefore, the read transfer performance is not limited by the transfer performance of other buses, so that the transfer performance (read performance) of the bus slave that is the transfer source can be maximized.
Similarly, only the transfer destination bus (A) 110 is used as a data write path. For this reason, the write transfer performance is not limited by the transfer performance of other buses, so that the transfer performance (write performance) of the bus slave as the transfer destination can be maximized.
As described above, according to the DMA controller 50 according to the present embodiment, in a configuration having four buses, data is DMA-transferred from the transfer source bus to the transfer destination bus through the shortest path, thereby improving the transfer rate of the data. be able to.

  In addition, the DMA controller 50 according to the present embodiment has DMA channels Ch0 to Ch15, and can perform DMA transfer on each channel assigned to DMA transfer (if the determination result in step Sa14 is “Yes”). ), DMA transfer is executed in parallel.

For example, in a state where the DMA channel Ch0 performs DMA transfer from the ROM 148 to the SRAM 118 (see FIG. 5), when a DMA transfer instruction from the memory 124 to the SPI 142 is assigned to the DMA channel Ch1, the bus of the transfer source bus ( B) Since the read master port of the master port P2 connected to 120 and the write master port of the master port P4 connected to the bus (D) 140 of the transfer destination bus are not used by the DMA channel Ch0, A transfer instruction is issued to the DMA channel Ch1.
Further, when a DMA transfer command from the sound circuit 132 to the DRAM 122 is assigned to the DMA channel Ch15 in a state where the DMA channels Ch0 and Ch1 are performing DMA transfer, the DMA channel Ch15 is connected to the bus (C) 130 of the transfer source bus. Since neither the read master port of the master port P3 nor the write master port of the master port P2 connected to the bus (B) 120 of the transfer destination bus is used by the DMA channels Ch0 and Ch1, the DMA channel A transfer instruction is given to Ch15.

FIG. 7 is a diagram showing a data transfer path when DMA channels Ch0, Ch1, and Ch15 are DMA-transferred in this way, and FIG. 8 shows a transfer path set in the DMA controller 50. FIG.
As shown in this figure, in this embodiment, since three DMA transfers are executed simultaneously in parallel, the efficiency as viewed in the entire system can be further improved.
Further, as shown in FIGS. 7 and 8, neither the read master port of the master port P1 nor the write master port of the master port P3 is used. For this reason, DMA transfer using the transfer source bus as the bus (A) 110 and the transfer destination bus as the bus (C) 130 is enabled by other DMA channels.

Of course, in the DMA controller 50, the transfer source bus and the transfer destination bus may be the same.
FIG. 9 is a diagram illustrating an example of a data transfer path when the DMA controller 50 has the same bus (D) 140 as the transfer source bus and the transfer destination bus. In the example of this figure, when any DMA channel performs DMA transfer from the ROM 148 to the I2C 144, data is read out through the path of ROM 148 (read port) → bus (D) 140 (→ DMA controller 50), while (DMA Data is written through the path of the controller 50->) bus (D) 140-> bus (D) 140-> I2C 114 (write port).

In addition, in the DMA controller 50, when two DMA buses connected via one of the bus bridges perform DMA transfer from a module of one bus to a module of the other bus, the bus bridge may be used. .
FIG. 10 shows DMA transfer from the sound circuit 132 belonging to the bus (C) 130 to the memory 122 belonging to the bus (B) 120 in the bus (B) 120 and the bus (C) 130 connected via the bus bridge 23. It is a figure which shows the transfer path | route of the data in the case of doing. In the example of this figure, one of the DMA channels reads data through a path of sound circuit 132 (read port) → bus (C) 130 → bus bridge 23 → bus (B) 120 (→ DMA controller 50), Data is written through a path of (DMA controller 50 →) bus (B) 130 → memory 122 (write port).

In this case, instead of the master port P2 of the DMA controller 50, the master port P3 may be used as shown in FIG. Specifically, as shown in the figure, one of the DMA channels reads data through the path of the sound circuit 132 (read port) → bus (C) 130 (→ DMA controller 50), while the (DMA controller 50 →) Data is written through the path of bus (C) 130 → bus bridge 23 → bus (B) 120 → memory 122 (write port).
Thus, in this description, the transfer of data through the shortest path can include a transfer via a bus bridge across adjacent buses.

  The present invention is not limited to the above-described embodiments, and various applications and modifications as described below are possible, for example. In addition, one or more arbitrarily selected aspects of application / deformation described below can be appropriately combined.

In the above-described embodiment, the bus width is not mentioned, but the bus widths of the bus (A) 110, the bus (B) 120, the bus (C) 130, and the bus (D) 140 are different from each other. Also good. Note that the DMA controller 50 (or the bus bridges 12, 23, and 34) executes the bus width conversion when the bus widths are different.
In the embodiment, the number of buses (and the number of master ports) connected to the DMA controller 50 is “4”, but may be “3” or more. It is sufficient that at least two buses have different transfer bands in three or more buses.

50 ... DMA controller, 110 ... bus (A), 112 ... CPU, 120 ... bus (B), 122 ... DRAM, 124 ... memory, 130 ... bus (C), 132 ... sound circuit, 140 ... bus (D), 142 ... SPI, 148 ... ROM, 502 ... transfer control unit, 504 ... selection unit, 512 ... identification unit, 514 ... address table.

Claims (7)

A DMA controller for transferring data from a source address to a destination address,
A master port provided corresponding to at least three or more buses, each connected to a corresponding bus;
An address table for storing addresses of modules connected to the bus in association with the connected bus;
A specifying unit that specifies a transfer source bus to which the module of the source address belongs and a transfer destination bus to which the module of the destination address belongs by referring to the address table;
A path for transferring data from the source address to the destination address is transferred to the transfer source bus, a master port connected to the transfer source bus, a master port connected to the transfer destination bus, and the transfer destination bus. A transfer control unit to be set;
A DMA controller comprising: 2. The master port provided corresponding to the three or more buses, at least two or more of them transfer data to the buses corresponding to each of them in different transfer bands. DMA controller. The DMA controller according to claim 1, wherein the three or more buses are connected in series via a bus bridge. The master port is
A set of read master port and write master port,
The DMA controller according to claim 1 or 2, characterized in that When the transfer source bus and the transfer destination bus are the same,
Data read-transferred through the read master port of the transfer source bus is write-transferred through the write master port of the transfer destination bus.
The DMA controller according to claim 4. The three or more buses are connected in series via a bus bridge,
When the transfer destination bus is a bus connected to the transfer source bus via the bus bridge, a master port corresponding to either the transfer source bus or the transfer destination bus and the bus bridge Data is transferred,
The DMA controller according to claim 4. A plurality of transfer channels to which data transfer functions are assigned by the transfer control unit;
The transfer control unit
When data transfer from one source address to one destination address is assigned to one transfer channel among the plurality of transfer channels,
Data by another transfer channel is transmitted between the read master port connected to the transfer source bus to which the module with the one source address belongs and the write master port connected to the transfer destination bus to which the module with the one destination address belongs. If it is not set as the transfer route,
Allow the assigned data transfer to the one transfer channel,
The DMA controller according to claim 4, 5 or 6.

Images