JP4789269B2 - Vector processing apparatus and vector processing method - Google Patents

Description

  The present invention relates to vector operation processing.

  In general, a vector processing device includes a plurality of vector operation registers that hold vector data loaded from a main memory, intermediate results during vector operations, and a vector operation unit that performs operations on vector data held in the vector operation registers. Prepare.

  The time from the access to the memory until the read data returns is called the memory access TAT. In recent vector computers, the memory access TAT tends to be relatively long with respect to the instruction processing time as the operation clock increases.

  Patent Document 1 describes a vector processing device including a load buffer that temporarily stores vector data between a main memory and a vector operation register in order to speed up loading from the main storage device to the vector operation register. Has been. The load buffer temporarily stores data until the vector data is transferred to the vector operation register after both the condition that all the elements of the vector data are complete and the condition that the transfer destination vector operation register resource is available. Has the ability to buffer.

Patent Document 2 describes a technique aimed at providing a vector processing device capable of preventing an increase in the amount of the vector data buffer and improving the utilization efficiency. This vector processing device divides a vector data buffer for each of a plurality of array systems by means of array system number holding means for holding the number of array systems of array data instructed by an instruction, and a value held by the array system number holding means And division control means for controlling the input / output of the array data.
JP 2005-25693 A JP-A-6-274526

  In recent vector computers, as the operation clock speeds up, the time from accessing the memory until the read data returns (memory access TAT) tends to be relatively longer than the instruction processing time. is there.

  The load buffer serves to conceal the memory access TAT by temporarily buffering the load data returned from the memory by the vector load instruction issued prior to the arithmetic instruction in order to effectively use the arithmetic unit. Bear. In order to conceal the relatively long memory access TAT, a larger capacity load buffer is required. In order to effectively use a limited chip area, it is required to efficiently use a load buffer and suppress an increase in load buffer capacity.

  The vector processing apparatus having the load buffer confirms that all elements specified by the vector load instruction are stored in the load buffer, and starts transfer from the load buffer to the vector operation register. In such processing, when loading is performed at an address where memory interleaving does not work, or when a vector load instruction having a large number of elements is used, it takes time until all the elements are stored in the load buffer. As a result, there is a problem that transfer from the load buffer to the vector operation register is delayed and execution of subsequent instructions using the load data is also delayed.

  An object of the present invention is to provide a system capable of improving the performance of the entire system by improving the use efficiency of a load buffer unique to a vector computing unit.

  A vector processing apparatus according to the present invention includes a memory access control unit that reads vector data from a main memory based on a received instruction, a load buffer that stores vector data read by the memory access control unit, and a vector operation register. A vector processing unit that vector-processes vector data transferred from a vector to a vector operation register, and a plurality of elements constituting the vector data are divided into a plurality of element groups, and all the elements of the plurality of element groups are memory access control units. And a vector instruction issuing unit that controls the element group read from the main memory to start transfer from the load buffer to the vector processing unit.

  A vector processing method according to the present invention includes a step of reading vector data from a main memory based on a received instruction, a step of storing vector data read by a memory access control unit in a load buffer, and a transfer from the load buffer to a vector operation register The vector processing of the vector data and a plurality of elements constituting the vector data are divided into a plurality of element groups, and all elements of the plurality of element groups are read from the main memory by the memory access control unit And a step of controlling the element group to start transfer from the load buffer to the vector processing unit.

  According to the present invention, subsequent vector operation instructions using the data of the vector load instruction can be executed quickly, so that the use efficiency of the vector operation unit is improved and the total system performance can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a schematic configuration diagram as an embodiment of the present invention. The vector processing apparatus according to the present embodiment includes an instruction decoding unit 1, a vector load request processing unit 2, a load data alignment determining unit 3, a vector instruction issuing unit 4, a vector instruction processing unit 5, a memory access control unit 6, and a main memory 7. Is provided.

  The instruction decoding unit 1 decodes the input instruction sequence. If the decoded instruction is a vector instruction including a vector load instruction, the instruction decoding unit 1 sends the vector instruction 12 and accompanying information to the vector instruction issuing unit 4. If the decoded instruction is a vector load instruction, the instruction decoding unit 1 sends the vector load instruction 11 and accompanying information to the vector load request processing unit 2. When receiving the busy signal 10 from the vector load request processing unit 2, the instruction decoding unit 1 has a function of temporarily stopping transmission of the vector load instruction.

  When the vector load request processing unit 2 receives the vector load instruction 11 and the accompanying information from the instruction decoding unit 1, the vector load request processing unit 2 performs a process of securing a load buffer for storing vector data loaded by the instruction. This process is performed as follows.

  Based on the number of elements constituting the vector data loaded by the received instruction, a subload buffer necessary for storing the vector data (example: 64-bit prepared by dividing a 256-bit load buffer into four parts) The number of units (subload buffers) is calculated. Among the plurality of load buffers, the load buffer having the calculated number of sub-load buffer vacancies is designated as the reserved load buffer that is the destination requesting the load. Further, the number of subload buffers necessary for storing vector data is designated as the reserved subload buffers from the free subload buffers of the reserved load buffers. Load buffer allocation number notifications 13 and 23 including an allocated load buffer number indicating an allocated load buffer and an allocated sub load buffer number indicating an allocated sub load buffer are sent to the load data determination unit 3 and the vector instruction issue unit 4 Sent out.

  The vector load request processing unit 2 generates a tag and address 18 and sends them to the memory access control unit 6. The address indicates a location on the main memory 7 where a plurality of elements constituting vector data to be loaded are stored. The tag includes a reserved load buffer number indicating a destination on the load buffer in which vector data to be loaded is stored and a reserved subload buffer number. When the necessary number of load buffers cannot be secured, the vector load request processing unit 2 transmits a busy signal 10 to the instruction decoding unit 1.

  The load data alignment determination unit 3 stores in advance the number of elements of vector data to be loaded for each subload buffer, and decrements the number of elements when the vector element is sent from the main memory 7 to the subload buffer. By monitoring the number of elements, alignment determination processing for recognizing that data has been transmitted to all register areas in units of subload buffers is performed.

  More specifically, the load data alignment determination unit 3 sets a value corresponding to the number of reply elements in the alignment determination counter corresponding to the reserved subload buffer number designated by the received reservation number notification 13. When the memory access control unit 6 reads the vector data element from the main memory 7 and sends it to the load buffer, the memory access control unit 6 sends the destination to the load data alignment determination unit 3 with the destination as a tag 19. The load data alignment determination unit 3 decodes the tag 19 and subtracts the value totaled for each subload buffer number from the value set in the alignment determination counter. When the result of subtraction becomes 0, it is determined that all elements scheduled for reply are prepared, and an alignment notification 15 is sent to the vector instruction issuing unit 4.

  The vector instruction issue unit 4 performs a vector instruction issue process and a load buffer release process as follows. The vector instruction issuing unit 4 receives a vector instruction 12 including a vector operation instruction and a vector load instruction from the instruction decoding unit 1. When a vector operation instruction is received, the busy state of various resources such as a vector operation register and the consistency between instructions are confirmed as necessary, and a vector operation start instruction 17 is sent at an appropriate timing to the vector instruction processing unit 5. To send. When a vector load instruction is received, a load buffer allocation number notification 23 corresponding to the vector load instruction is received, the corresponding load buffer alignment notification 15 and the busy status of the transfer destination vector operation register area and the consistency between instructions are checked. After confirmation, a load buffer transfer start instruction 16 is sent to the vector instruction processing unit 5 at an appropriate timing. At this time, the load buffer number that has started the transfer is sent to the vector load request processing unit 2 as a load buffer release notification 14.

  The vector instruction processing unit 5 includes a load buffer 5-1 and a vector operation register 5-2, and has a function of performing vector operation processing on data stored in the vector operation register 5-2. The vector instruction processing unit 5 performs vector instruction processing as follows. When the load buffer transfer start instruction 16 is received, the load data is read from the designated area of the load buffer 5-1, and stored in the designated vector operation register area. When the vector calculation start instruction 17 is received, a process of reading data from the designated vector calculation register area and performing a predetermined vector calculation is stored in the designated vector calculation register area.

  The memory access control unit 6 receives the tag and address 18. The address of the tag and address 18 indicates a data read address 21 which is information indicating the address on the main memory 7 of each element of the vector data to be read. A data read address 21 is sent to the main memory 7 based on the received tag and address 18. The memory access control unit 6 receives read data 22 from the main memory 7. The tag and data 20 including the received read data 22 and the destination of the read data 22 indicated by the tag and the tag of the address 18 are sent to the vector instruction processing unit 5. Further, the tag 19 corresponding to the read data 22 at the tag and address 18 is sent to the load data alignment determination unit 3. The memory access control unit 6 has an interleaving function, and has a function capable of accessing the divided areas on the main memory 7 in parallel.

  The main memory 7 stores programs and vector data. When the main memory 7 receives the data read address 21 from the memory access control unit 6, the main memory 7 reads the data from the memory element at the address and sends it to the memory access control unit 6 as read data 22. The main memory 7 has an access port in each of the divided memory areas so that an interleaved configuration can be adopted.

  FIG. 2 shows details of the load data alignment determination unit 3. The number-of-elements setting unit 301 specifies the use location of the load buffer and the sub load buffer based on the reserved load buffer number and the reserved sub load buffer number included in the received reservation number notification 13. The number-of-elements setting unit 301 distributes a plurality of elements constituting vector data loaded by the received vector load instruction 11 to a plurality of reserved subload buffers, and stores them in each reserved subload buffer. The subload buffer storage scheduled element number 351 that is the number of elements to be stored is calculated and sent to the element number subtraction counter unit 302.

  In the present embodiment, the maximum number of elements of vector data is 256, and the number of elements of a subload buffer, which is a division unit for dividing and loading vector data, is 64. When the number of elements of the vector data to be loaded is 1 to 64, one division unit is used. When the number of elements is 65 to 128, two division units are used. When the number of elements is 129 to 192, 3 is used. When the number of elements is 193 to 256, four division units are used.

  The data read from the main memory 7 is transferred to one load buffer 5-1 in units of sub load buffers, which are sub areas obtained by dividing the area of the load buffer 5-1 by a predetermined division unit. The A plurality of sub load buffers corresponding to one load buffer 5-1 are specified by sub load buffer numbers. The element number setting unit 301 generates the subload buffer storage scheduled element number 351 by dividing the number of elements of the vector data to be loaded and assigning it to the subload buffer specified by the reservation number notification 13. This allocation is performed so that 64 elements are packed from the reserved subload buffer having a lower subload buffer number. In the case where the number of elements is 64 and the fraction is not divisible, the fraction is assigned to the reserved subload buffer number having the largest number.

  The element number subtraction counter unit 302 includes a number of alignment determination counters equal to the number of subload buffers and valid flags corresponding to the alignment determination counters. The element number subtraction counter unit 302 sets “0” to each valid flag of the unreserved subload buffer, and sets “1” to the valid flag corresponding to each secured subload buffer. The element number subtraction counter unit 302 sets the subload buffer storage scheduled element number 351 in each alignment determination counter whose valid flag is “1”.

  The load buffer number assigning unit 303 receives a plurality of tags 19. Each of the plurality of tags 19 includes a reserved load buffer number and a reserved sub that identify a load buffer 5-1 in which an element read from the main memory 7 among the elements constituting the vector data to be loaded is stored. Contains the load buffer number. The load buffer number assigning unit 303 has a function of decoding each of the plurality of tags 19 and assigning them to each sub load buffer number and sending them to the element number counter 304.

  The element counter 304 has a counter corresponding to each of the plurality of sub load buffers provided in the plurality of load buffers 5-1. Each time the load buffer number distribution unit 303 receives the tag 19, each counter counts up the number of times 352 that the corresponding sub load buffer became the distribution destination in the load buffer number distribution unit 303, and the element number subtraction counter To the unit 302. If the number of tags 19 that can be received simultaneously by the load buffer number assigning unit 303 is N (that is, if tags corresponding to N elements constituting the vector data can be received simultaneously), all the tags 19 are the same. If it is addressed to the subload buffer number, the counted value is N (the maximum value is N).

  The alignment determination unit 305 has a function of determining that a predetermined number of load data (same as the number 351 of scheduled subload buffer storage elements) is stored in each subload buffer. This determination is made on condition that the value of each alignment determination counter of the element number subtraction counter unit 302 is “0” and the corresponding valid flag is “1”. When this condition is satisfied, the alignment determining unit 305 notifies the vector instruction issuing unit 4 of an alignment notification 15 indicating that all the predetermined number of elements have been loaded into the subload buffer.

  FIG. 3 shows the vector instruction issuing unit 4. The vector instruction issue unit 4 includes two vector operation instruction issue wait buffers 410 and 430 and two vector load instruction issue wait buffers 420 and 440. The instruction buffer unit 401 receives the vector instruction 12 including the vector load instruction from the instruction decode unit 1, receives the vector instruction in the vector operation instruction issue waiting buffers 410 and 430, and receives the vector load instruction in the vector load instruction issue wait buffers 420 and 440. Control to store.

  When the vector operation instruction issuance waiting buffers 410 and 430 or the vector load instruction issuance waiting buffers 420 and 440 are waiting for issuance and cannot be used for storing instructions, the vector instruction buffer unit 401 receives the vector instructions in the order received (First In Buffering (at First Out). At this time, if there is at least one “1” in the unissued element identification flag 412 or the unissued element identification flag 422, it is determined that there is an unprocessed element number band, and the vector operation instruction issue waiting buffers 410, 430 or It is determined that the vector load instruction issuance waiting buffers 420 and 440 are in use waiting for issuance.

  The vector computing unit busy management unit 402 has a function of managing a busy flag indicating that a vector computing unit (not shown) is being used. The vector operation unit busy information indicating that the vector operation unit is being used is sent to the vector operation instruction issue check unit 415 and used for the vector operation instruction issue check. By the vector operation instruction issue check, control is performed so that the vector operation by another element number band or another instruction does not start while using the vector operation unit.

  The load buffer transfer path busy management unit 403 is using a load buffer transfer path which is a path used to transfer load data from the load buffer 5-1 in the vector processing unit 5 to the vector operation register 5-2. It has a function to manage a busy flag indicating that there is a certain event. The busy information indicating the busy state of the load buffer transfer path is used for an issue check when starting the load buffer transfer. By this issuance check, control is performed so that load buffer transfer due to another element number band of the same instruction or another vector load instruction does not start during load buffer transfer.

  The vector operation instruction issue waiting buffers 410 and 430 are a vector operation instruction information buffer 411, an unissued element identification flag 412, an inter-instruction consistency maintaining flag 413, an inter-instruction consistency maintaining flag check unit 414, and a vector arithmetic instruction issuance, respectively. A check unit 415 is included.

  The vector load instruction issue waiting buffers 420 and 440 include a vector load instruction information buffer 421, an unissued element identification flag 422, an inter-instruction consistency maintaining flag 423, a load buffer number 424, a load buffer use location instruction flag 425, and an inter-instruction A consistency maintenance flag check unit 426, a specific load buffer transfer condition confirmation unit 427, and a vector load instruction issue check unit 428 are included.

  The vector operation instruction information buffer 411 stores the operation type and vector operation register information that is read and written by the vector operation instruction.

  The unissued element identification flag 412 is set in correspondence with four element number bands formed by dividing vector data composed of 256 element bands into 64 elements as division units. Control is performed so that the flag value corresponding to the element number band for which the calculation start instruction has not yet been issued becomes “1”.

  The inter-instruction consistency maintaining flag 413 corresponds to four element number bands formed with 64 elements as a division unit, and is set corresponding to instruction issue waiting buffers 420, 430, and 440 other than 410. When it is necessary to keep the instruction execution order for data consistency with the preceding instruction (there is a vector operation register conflict relationship), the corresponding flag value is controlled to be valid.

  The inter-instruction consistency maintaining flag check unit 414 performs inter-instruction consistency processing as follows. When the flag information of the inter-instruction consistency maintaining flag 413 is invalid, an instruction issue permission signal corresponding to the corresponding division unit is sent to the vector operation instruction issue check unit 415.

  If the flag information of the inter-instruction consistency maintaining flag 413 is valid, the vector load instruction transfer destination vector operation register area stored in the vector load instruction issuance waiting buffer 420 and waiting for execution, and the following vector Since the vector operation register area read or written by the operation instruction coincides with the vector operation register area, it is indicated that the order of instruction issuance must be maintained from the necessity of maintaining data consistency. Therefore, unless the preceding vector load instruction is issued, the succeeding vector operation instruction stored in the vector operation instruction issuance waiting buffer 410 is not issued. By such processing, when the vector operation register used by the vector load instruction in progress competes with the preceding vector processing, execution of the subsequent vector operation instruction can be suspended.

  In this embodiment, four element number bands are formed by dividing 256 elements constituting vector data using 64 elements as a division unit. For example, when it is necessary to maintain the data consistency between the vector load instruction and the subsequent vector operation instruction, when the preceding vector load instruction for the first 64 elements is issued, the inter-instruction consistency corresponding to the first 64 elements is maintained. The flag 413 becomes invalid, and an instruction issue permission signal corresponding to the first 64 elements of the vector operation instruction is sent to the vector operation instruction issue check unit 415.

  The vector operation instruction issue check unit 415 includes a busy signal from the vector operation unit busy management unit 402, an instruction issue permission signal from the inter-instruction consistency maintaining flag check unit 414, and an unissued element from the unissued element identification flag 412. The identification flag signal and instruction information from the vector operation instruction information buffer 411 are received.

  The vector operation instruction issue check unit 415 checks a condition for issuing a vector operation instruction. This condition includes a condition that the vector computing unit is not busy, and a 4-bit unissued element identification flag 412 corresponding to the four element number bands obtained by dividing 64 elements as a division unit, and a 4-bit instruction corresponding thereto. This is a condition that satisfies both of the conditions that there is a digit in which a 4-bit signal obtained by ANDing the signal of the consistency maintaining flag check unit 414 for each digit has a valid “1”. When this condition is satisfied, the vector operation start instruction 17 for one element number band that satisfies the condition is selected from the four element number bands obtained by dividing the 64 elements as a division unit. 5 is sent out.

  There are cases where the issuing conditions for a plurality of element number bands are established for the four element number bands. In that case, a vector operation instruction execution start instruction is issued for one element number band from among a plurality. Also, an instruction to start execution of a vector operation instruction is issued, and at the same time, the vector operation unit busy management unit 402 is instructed to turn on the vector operation unit busy flag for 2 clocks (= 64 elements / [processing speed 32 elements per clock]). Put out.

  The vector load instruction information buffer 421 stores vector operation register information of a vector load instruction transfer destination.

  The unissued element identification flag 422 is set corresponding to four element number bands formed with 64 elements as division units. The flag value for each element for which the load buffer transfer start instruction has not yet been issued is controlled to be “1”.

  The inter-instruction consistency maintaining flag 423 corresponds to four element number bands formed with 64 elements as division units, and corresponds to instruction issue waiting buffers 410, 430, and 440 other than the vector load instruction issue waiting buffer 420. Installed. When there is a vector operation register conflict relationship with the preceding instruction and there is a need to maintain data consistency, the corresponding flag value is controlled to be “1” (valid).

  The load buffer number 424 stores the load buffer number of the vector load instruction transfer source.

  The load buffer usage location instruction flag 425 stores a sub load buffer usage location indication flag. A flag corresponding to a plurality of sub load buffer numbers in the load buffer number of the vector load instruction transfer source is set to be valid.

  When the flag information of the inter-instruction consistency maintaining flag 423 is invalid, the inter-instruction consistency maintaining flag check unit 426 sends an instruction issuance permission signal corresponding to the corresponding division unit to the vector load instruction issuance checking unit 428. Has function. If the flag information of the inter-instruction consistency maintaining flag 423 is valid, the vector operation register area used in advance by the vector operation instruction stored in the vector operation instruction issue waiting buffer 410 and waiting for execution, and the subsequent vector It is shown that the vector operation register area of the load instruction transfer destination coincides and the order of instruction issue must be observed. In this case, control is performed so that the subsequent vector load instruction stored in the vector load instruction issuance buffer 420 is not issued unless the preceding vector operation instruction is issued.

  In the present embodiment, the elements of a plurality (256 elements) constituting the vector data are divided into a plurality of element groups (four element number bands formed by dividing 64 elements as a division unit). For example, if it is necessary to maintain data consistency between a vector operation instruction and a subsequent vector load instruction, when the preceding vector operation instruction for the first 64 elements is issued, the first 64 of the inter-instruction consistency maintenance flag 423 is issued. The flag corresponding to the element becomes invalid, and a vector load instruction issue permission (load buffer transfer start permission) signal corresponding to the first 64 elements is sent to the vector load instruction issue check unit 428. As a result of this processing, even when all the elements constituting the vector data are not prepared, all elements of the plurality of element groups are transferred from the element group read from the main memory 7 to the vector operation register 5-2 first. It becomes possible to do.

  The specific load buffer transfer condition confirmation unit 427 includes an alignment notification 15 sent from the load data alignment determination unit 3, a load buffer number 424 stored in the vector load instruction issuance waiting buffer 420, and a load buffer use location instruction flag. The information of the sub load buffer use location instruction flag stored in 425 is compared with the alignment notification signal for each sub load buffer. If there is a matching subload buffer as a result of the comparison, the vector load instruction issuance permission (load buffer transfer start permission) of the element number band corresponding to the subload buffer is sent to the vector load instruction issuance check unit 428.

  In this embodiment, the correspondence between the load buffer use location instruction flag 425, the four element number band 422 formed by dividing the 64 elements into division units, and the inter-instruction consistency maintaining flag 423 Are in order of increasing load buffer usage location instruction flag 425.

  For example, consider a case where a 256 element vector load instruction is buffered at 420 and the load buffer usage location instruction flag 425 stores the pattern “11101000”. In this case, control is performed so that the load data element is stored in the load buffer 5-1 so that the following correspondence is established. Regarding the elements 0 to 63, the first flag of the unissued element identification flag 422 corresponds to the first bit of the load buffer usage location instruction flag 425. Regarding the elements 64 to 127, the second flag of the unissued element identification flag 422 corresponds to the second bit of the load buffer usage location instruction flag 425. The elements 128 to 191 correspond to the third flag of the unissued element identification flag 422 and the third bit of the load buffer usage location instruction flag 425. The elements 192 to 255 correspond to the fourth flag of the unissued element identification flag 422 and the fifth bit flag of the load buffer usage location instruction flag 425.

  The vector load instruction issue check unit 428 includes a load buffer transfer pass busy signal from the load buffer transfer path busy management unit 403, an instruction issue permission signal from the inter-instruction consistency maintaining flag check unit 426, and a specific load buffer transfer condition confirmation unit 427. From the vector load instruction information buffer 421, the unissued element identification flag signal from the unissued element identification flag 422, and the instruction information from the vector load instruction information buffer 421.

The vector load instruction issuance check unit 428 starts vector operation for one element number band from four element number bands formed by dividing 64 elements as a division unit when the following three conditions are satisfied: An instruction 17 is sent to the vector instruction processing unit 5.
(1) The load buffer transfer path is not busy,
(2) When attention is paid to a certain element number band, a 4-bit signal obtained by performing a logical product for each digit of a 4-bit unissued element identification flag 422 and a corresponding 4-bit inter-instruction consistency maintenance flag check unit 426 The digit is “1”.
(3) The load buffer transfer condition confirmation unit 427 confirms that the load data of any of the four element number bands is complete.
When this condition is satisfied, a vector operation start instruction 17 for one element number band is sent to the vector instruction processing unit 5 out of four element number bands formed using 64 elements as a division unit.

  There are cases where the issuing conditions for a plurality of element number bands are established for the four element number bands. In this case, a vector load instruction execution start instruction (load buffer transfer start instruction 16) for one element number band from among a plurality of elements is sent to the vector instruction issuing unit 5 and simultaneously loaded to the load buffer in-use flag reset signal generating unit 204. A buffer release notification 14 is sent out. At the same time when the load buffer transfer start instruction is issued, the load buffer transfer path busy management unit 403 is instructed to turn on the busy flag for 2 clocks (= 64 elements / [processing speed 32 elements per clock]).

  FIG. 4 shows the vector load request processing unit 2. The address conversion unit 201 decodes the vector load instruction 11 received from the instruction decoding unit 1. The address conversion unit 201 generates addresses for the number of elements of the vector data based on the load start address, the inter-element address distance, and the number of elements included in the vector load instruction 11. This address indicates a position on the main memory 7 where a plurality of elements constituting vector data to be used are stored. The address conversion unit 201 sends the generated address as a part of the tag and the address 18 to the memory access control unit 6 and performs a load instruction for the number of elements based on one vector load instruction.

  The use load buffer determination unit 202 determines a place on the load buffer 5-1 to load vector data as follows. First, the vector load instruction 11 received from the instruction decoding unit 1 is decoded. The vector load instruction 11 includes element number information indicating the number of elements of vector data to be loaded. Based on the number-of-elements information, the necessary number of subload buffers necessary for storing all the elements of the vector data is calculated. A load buffer 5-1 having empty subload buffers corresponding to the number of necessary subload buffers is selected. In the selected load buffer 5-1, an unused sub load buffer is secured by the number of necessary sub load buffers. The reserved sub load buffer is specified by a reserved load buffer number that specifies the selected load buffer 5-1, and a reserved sub load buffer number that specifies the reserved sub load buffer. Through the above processing, the load buffer 5-1 and the plurality of sub load buffers used by a certain vector load instruction are determined and notified by the allocation number notifications 13 and 23.

  The used load buffer determining unit 202 sends a load buffer in-use flag set signal to the load buffer in-use flag 203 at the same time as the reservation number notifications 13 and 23, and a location on the newly reserved load buffer 5-1 "1" is set in a flag corresponding to the reserved load buffer number indicating the reserved sub-buffer number. The use load buffer determination unit 202 further transmits to the tag generation unit 205 the reserved load buffer number, the reserved sub load buffer number, and the number of elements of vector data to be loaded.

  When the required number of sub load buffers (load buffer division units) cannot be secured for all the load buffer numbers, the used load buffer determination unit 202 sends the busy signal 10 to the instruction decode unit 1 to perform subsequent vector loading. Suppress sending instructions.

  In the present embodiment, the maximum number of elements is 256, and the number of elements in the unit for dividing the load buffer is 64. When the number of elements is 1 to 64, one division unit is used. When the number of elements is 65 to 128, two division units are used. When the number of elements is 129 to 192, three division units are used. When the number of elements is 193 to 256, 4 division units are used.

  The load buffer in-use flag 203 has a flag for every load buffer division unit. That is, it has flags corresponding to all subload buffer numbers. These flags are set and reset based on a set signal from the used load buffer determining unit 202 and a reset signal from the load buffer in-use flag reset signal generating unit 204.

  The load buffer busy flag reset signal generation unit 204 receives from the vector instruction issue unit 4 a load buffer release notification 14 that is sent when a load buffer transfer start instruction is issued. The load buffer release notification 14 includes a sub load buffer number that identifies a sub load buffer that has become empty. The load buffer busy flag reset signal generation unit 204 sends a reset signal to the load buffer busy flag 203 so that the flag corresponding to the sub load buffer number is reset.

  The tag generation unit 205 uses the load buffer number secured by the use load buffer determination unit 202, a plurality of subload buffer numbers, and information on the number of elements of vector data to be loaded to store each load destination load buffer of the vector data elements. The address is generated as a tag, and the tag and address 18 are sent to the memory access control unit 6 so as to correspond one-to-one to the load address that is an address on the main memory 7 generated individually by the address conversion unit 201.

  The tag information includes information on a reserved load buffer number, a plurality of reserved sub load buffer numbers, and a storage load buffer address of each element of load data. By determining that the storage destination load buffer addresses are allocated in order from the smallest of the plurality of reserved sub load buffer numbers, if the storage destination load buffer address is sent to the memory access control unit 6 as a tag, the necessary information can be obtained. As a result, the number of interfaces can be reduced, resulting in a desirable configuration.

The following vector processing apparatus is configured by the configuration of the present embodiment described above.
First, the use load buffer determination unit 202, the element number setting unit 301, the element number subtraction counter unit 302, the alignment determination unit 305, the vector operation instruction issue wait buffer 410, and the vector operation instruction issue wait buffer 430 are used to generate the next vector. A processing device is realized.

  The vector processing apparatus includes a load buffer 5-1 for temporarily storing vector data read from the main memory 7 between the main memory 7 and the vector calculation register 5-2. When the vector load instruction read from the main memory 7 is decoded, a use area of the load buffer 5-1 is secured and reading of vector data from the main memory 7 to the load buffer 5-1 is started. After starting, on condition that the element of vector data is stored in the load buffer 5-1, and that the vector operation register area used in the vector load instruction does not conflict with the vector operation register area used in the preceding vector instruction, Transfer of vector data from the load buffer 5-1 to the vector operation register 5-2 is started. In such a vector processing apparatus, after dividing the maximum number of vector elements into a predetermined size and confirming that the data elements loaded in the divided units are stored, the vector operation is performed from the load buffer 5-1. Control is performed to start transfer of vector data to the register 5-2.

  Second, in addition to the above configuration, the vector operation instruction issue waiting buffers 410 and 430 and the vector load instruction issue wait buffers 420 and 440 operate in cooperation to realize a vector processing device having the following functions. .

  In the vector processing device, in order to avoid losing data consistency in the instruction decoding order, a check is performed in units divided into the above specific sizes, and if there is no problem in data consistency, regardless of the instruction decoding order Control is performed to issue an instruction.

  Third, in addition to the above configuration, the use load buffer determination unit 202, the element number setting unit 301, and the element number subtraction counter unit 302 operate in cooperation, thereby realizing a vector processing device having the following functions. The

  In the vector processing apparatus, the load buffers in the divided units are grouped into one or a plurality of groups, and the necessary number of load buffer dividing units are secured according to the number of vector load elements. Control is performed so that the load buffer division unit is transmitted to the vector instruction issuing unit.

  Fourth, in addition to the above configuration, the used load buffer determining unit 202, the load buffer in-use flag 203, the load buffer in-use flag reset signal generating unit 204, and the vector operation instruction issue waiting buffers 410 and 430 operate in cooperation. Thus, a vector processing device having the following functions is realized.

  In the vector processing device, the load buffer corresponding to the unit divided in accordance with the start of transfer of vector data from the load buffer 5-1 to the vector operation register 5-2 in the unit divided into the specific size. Release and control to use in subsequent vector load instructions.

[Description of operation]
Next, the operation of the present embodiment will be described using the time chart of FIG. 5 and the instruction sequence example for explanation of FIG.

  FIG. 7 shows an example of an instruction sequence for explanation, and it is assumed that decoding is performed in the order of numbers 1-7. ADD-A is defined as an instruction for performing an ADD operation using data loaded to the operation register 5-2 by the LD-A. ADD-B is defined as an instruction for performing an ADD operation using data loaded to the operation register 5-2 by LD-B. Since the vector operation register areas to be used are different except for the first, second, third and fourth instructions, there is no issue order dependency between instructions from the viewpoint of data consistency. All vector data are defined to have 256 elements.

  The ADD operation is normally performed using two operand data, but in this embodiment, it is assumed that the data paired with the load data is stored in a separate vector operation register in advance. Further, there is only one write path from the load buffer 5-1 to the vector operation register 5-2.

  FIG. 5 shows a time chart of a case where the instruction sequence shown in FIG. 7 is executed. Hereinafter, the operation will be described with reference to the clock number 1-33 described in the upper part of the figure. The timing at which the vector load instruction LD-A is decoded by the instruction decoding unit 1 and output to the vector load request processing unit 2 and the vector instruction issuing unit 4 as the vector load instruction 11 and the vector instruction 12 is set as a clock 1.

  When the instruction sequence shown in FIG. 7 is sequentially decoded, the tag and address 18 are stored in the memory access control unit 6 after securing the subload buffer for storing vector data read by each instruction sequence. Sent out.

  The vector instruction processing unit 5 includes two load buffers 5-1 specified by # 0 and # 1. When the vector load instruction LD-A in the first row of the instruction sequence is processed by the use load buffer determination unit 202, the sub load buffers 0, 1, 2, and 3 in the load buffer # 0 (FIGS. 2, 4, and 4) In FIG. 6, four of LD-Buf # 0-0, # 0-1, # 0-2, # 0-3 and # 0 indicating the load buffer number are added to the branch number). Secured. A value of “11110000” is output as the usage location information of the reservation number notifications 13 and 23.

  Similarly, when the LD-B in the second row of the instruction sequence is processed by the use load buffer determination unit 202, the sub load buffers 4, 5, 6, and 7 of the load buffer # 0 are secured and the use location information includes “ A value of 00001111 "is output. When the LD-C in the fifth row of the instruction sequence is processed by the use load buffer determination unit 202, the sub load buffers 0, 1, 2, and 3 of the load buffer # 1 are secured, and the LD-B uses the load buffer determination unit. When processed in 202, the sub load buffers 4, 5, 6, and 7 of the load buffer # 1 are secured. Since all the load buffers # 0 and # 1 are in use at this time, the subsequent vector load instruction LD-E enters a state of waiting for processing, and a busy signal 10 is output to the instruction decoding unit 1.

  The element number setting unit 301 receives the reservation number notification 13 from the use load buffer determining unit 202, and LD-Buf # 0-0, LD-Buf # 0-1, LD-Buf # 0- of the element number subtraction counter unit 302. 2, the value 64 is set in each of the alignment determination counters of LD-Buf # 0-3, and “1” is set in the corresponding valid flag.

  The vector instruction buffer unit 401 sequentially receives an instruction sequence as shown in FIG. First, the vector load instruction LD-A is stored in the vector load instruction issuance waiting buffer 420, and then the vector operation instruction ADD-A is stored in the vector operation instruction issuance waiting buffer 410. Subsequently, LD-B is stored in the vector load instruction issuance waiting buffer 440, and ADD-B is stored in the vector operation instruction issuance waiting buffer 430. LD-C and LD-D are buffered in the vector instruction buffer 401 until the vector load instruction issue wait buffer 420 or the vector load instruction issue wait buffer 440 becomes empty.

  When the ADD-A is stored in the vector operation instruction issuance waiting buffer 410 so that the ADD-A is executed over the LD-A and the data consistency is not impaired, the vector load instruction issuance waiting buffer is preceded. “1111” is set in the inter-instruction consistency maintaining flag 413 for the LD-A stored in 420. For this reason, even if the vector operation register area used in the ADD-A instruction is not busy, all of the inter-instruction consistency maintaining flags 413 are “1”, so that the four element number bands formed with 64 elements as a division unit. No issue permission signal is valid "1". As a result, the ADD-A instruction enters a standby state in the vector operation instruction issuance waiting buffer 410.

  Since LD-A is the first instruction, there is no need to maintain data consistency with the preceding instruction, so “0000” is set in the inter-instruction consistency maintaining flag 423. Therefore, as soon as it is confirmed that the data of the sub load buffer LD-Buf # 0-0, LD-Buf # 0-1, LD-Buf # 0-2, or LD-Buf # 0-3 is prepared, the operation register The data in the load buffer 5-1 can be started to be transferred to 5-2. This state is a state of the clock 14 which is omitted from the time chart as a wait state for load data alignment. FIG. 6A shows the load buffer usage state at this time.

  When all the 64 elements assigned to the youngest reserved subload buffer LD-Buf # 0-0 of the vector load instruction LD-A are received from the memory access control unit 6 at the clock 15, the number of elements The value of the alignment determination counter of LD-Buf # 0-0 in the subtraction counter unit 302 is “0”. The alignment determining unit 305 determines that all the load elements of the sub load buffer LD-Buf # 0-0 are aligned.

  At the clock 16, the specific load buffer transfer condition confirmation unit 427 compares the load buffer number 424 of the LD-A and the information of the load buffer usage location 425 with the alignment notification 15 received from the alignment determination unit 305. From this comparison, it is recognized that the alignment of LD-Buf # 0-0 reserved for LD-A is completed, and further, since it is the element number band of the smallest reserved subload buffer number, the element It is also identified that the alignment of the numbers 00 to 63 has been completed, and this is transmitted to the vector load instruction issue check unit 428.

  The vector load instruction issuance check unit 428 confirms that the transfer destination vector operation register area of the LD-A is not busy, and the vector operation register area specified by the instruction for the sub load buffer LD-Buf # 0-0 A load buffer transfer start instruction 16 is issued. At the same time, the load buffer release notification 14 of LD-Buf # 0-0 is sent to the load buffer in-use flag reset signal generation unit 204, and the flags corresponding to the element numbers 00 to 63 of the unissued element identification flag 422 are reset. Further, an instruction is issued to reset the flag corresponding to the LD-A element number 00 to 63 of the inter-instruction consistency maintaining flag 413 of the vector load instruction issuance waiting buffer 420 to “0”. As a result, the value of the unissued element identification flag 422 becomes “0111”, and the value of the inter-instruction consistency maintenance flag 413 becomes “0111”. Since the LD-A transfer destination has only one write path to the vector operation register 5-2, the load buffer transfer path busy management unit turns on the busy flag for two clocks until the transfer is completed. An instruction is issued to 403.

  Further, in the present embodiment, it is identified that all elements of the sub load buffer LD-Buf # 0-1 are prepared at the clock 16.

  In response to the transfer instruction to the vector operation register 5-2 for the sub load buffer LD-Buf # 0-0 at the clock 17, the vector instruction processing unit 5 receives the vector operation register 5- from the sub load buffer LD-Buf # 0-0. The load data transfer to 2 is started. Since 32 elements of load data can be transferred in one clock, the load buffer transfer path is used for two clocks. Correspondingly, the load buffer transfer path busy management unit 403 is instructed to turn on the busy flag for two clocks.

  At this timing, the specific load buffer transfer condition confirmation unit 427 receives the alignment determination signal of the sub load buffer LD-Buf # 0-1 and compares it with the load buffer number 424 and the load buffer use location instruction flag 425, and the element number 64 ˜127 is transmitted to the vector load instruction issue check unit 428 that the load data can be transferred. Since the busy flag in the vector computing unit busy management unit 402 is lit, no transfer start instruction is issued to the subload buffer LD-Buf # 0-1.

  On the other hand, the value of the inter-instruction consistency maintaining flag 413 for LD-A is “0111”. Therefore, the inter-instruction consistency maintaining flag check unit 414 determines that the ADD operation of the element numbers 00 to 63 can be executed, and an instruction issue permission signal “1000” is sent to the vector operation instruction issue check unit 415. The vector operation instruction issuance check unit 415 includes information indicating the value “1111” of the unissued element identification flag 412, information indicating the instruction issuance permission signal “1000” from the inter-instruction consistency maintaining flag check unit 414, and vector calculator busy Therefore, it is determined that the ADD calculation start instruction for the element number band of the element numbers 00 to 63 can be issued, and the ADD calculation start instruction for the element numbers 00 to 63 is issued as the vector calculation start instruction 17. At the same time, an instruction to turn on the busy flag in the ADD-A instruction execution result storage destination vector operation register area in the vector operation unit busy management unit 402 is given for 2 clocks, and it corresponds to the element numbers 00 to 63 of the unissued element identification flag 412. Reset the flag you want. As a result, the value of the unissued element identification flag 412 is “0111”.

  At clock 18, the busy flag of the load buffer transfer path busy management unit 403 is turned off. Therefore, the issue condition is checked by the vector load instruction issue check unit 428, and the load buffer transfer start instruction 16 of the sub load buffer LD-Buf # 0-1 in which the load data of the element numbers 64 to 127 is stored is vectorized. It is sent to the instruction processing unit 5.

  At this timing, the load buffer release notification 14 of LD-Buf # 0-1 is sent to the load buffer busy flag reset signal generation unit 204, and the flags corresponding to the element numbers 64-127 of the unissued element identification flag 422 are reset. Further, a reset instruction is issued to the flags corresponding to the element numbers 64 to 127 of the inter-instruction consistency maintaining flag 413 for the LD-A stored in the vector load instruction issuance waiting buffer 420. As a result, the value of the unissued element identification flag 422 is “0011”, and the value of the inter-instruction consistency maintaining flag 413 is “0011”. Also, since there is only one write path to the LD-A transfer destination vector operation register 5-2, the load buffer transfer path busy so that the busy flag is lit for two clocks using the load buffer transfer path. An instruction is issued to the management unit 403.

  At the clock 19, upon receiving a transfer instruction to the vector operation register 5-2 for the sub load buffer LD-Buf # 0-1, the vector instruction processing unit 5 receives the vector operation register 5-5 from the sub load buffer LD-Buf # 0-1. The load data transfer to 2 is started. FIG. 5 is a time chart in which the ADD calculation is completed in two clocks. This is because 32 elements of ADD calculation can be performed in one clock.

  At this timing, the specific load buffer transfer condition confirmation unit 427 receives the alignment determination signal of the sub load buffer LD-Buf # 0-2, compares it with the load buffer number 424 and the load buffer usage location instruction flag 425, and compares the element numbers 128 to It informs 428 that 191 load data can be transferred. However, since the busy flag of the load buffer transfer path busy management unit 403 is lit, a transfer start instruction for the sub load buffer LD-Buf # 0-2 is not issued.

  On the other hand, the value of the inter-instruction consistency maintaining flag 413 for LD-A is “0011”. For this reason, the inter-instruction consistency maintaining flag check unit 414 determines that the ADD operation of the element numbers 64 to 127 can be executed, and sends an instruction issue permission signal to the vector operation instruction issue check unit 415.

  The vector operation instruction issuance check unit 415 indicates that the value of the second bit of the unissued element identification flag 412 is “1” when the element numbers 64 to 127 are focused, and the 2 bits of the inter-instruction consistency maintenance flag 413. It is checked that the value of the eye is “1” and that the vector calculator is not busy, and an ADD calculation start instruction for element numbers 64 to 127 is output to the vector instruction processing unit 5 as a vector calculation start instruction 17. At the same time, an instruction to turn on the busy flag for two clocks is issued to the vector computing unit busy management unit 402, and the flags corresponding to the element numbers 64 to 127 of the unissued element identification flag 412 are reset. As a result, the value of the unissued element identification flag 412 is “0011”.

  As described above, by realizing the function of maintaining data consistency between instructions in units of dividing the load data of 256 elements into 64 elements, subsequent ADD operations can be performed efficiently.

  At clock 20, a transfer start instruction and a load buffer release instruction are issued to sub load buffer LD-Buf # 0-2 in which element numbers 128 to 191 are stored. At the same time, the value of the inter-instruction consistency maintaining flag 413 corresponding to the element numbers 128 to 191 is reset to “0”. The vector load instruction LD-E is a vector load instruction having 256 elements, and it is necessary to secure four load buffer division units. At this point, since only three sub load buffers are available in the load buffer # 0, the busy signal to the instruction decoding unit 1 remains valid.

  Since the value of the inter-instruction consistency maintaining flag 413 corresponding to the element numbers 128 to 191 becomes “0” in the clock 21, the vector operation start instruction for the element number band corresponding to the element numbers 128 to 191 of the ADD-A instruction is issued. Is issued.

  At clock 22, a transfer start instruction and a load buffer release instruction are issued to sub load buffer LD-Buf # 0-4 in which element numbers 00 to 63 of the LD-B instruction are stored. The load buffer busy flag reset signal generation unit 204 receives the load buffer release notification 14 from the vector load instruction issue check unit 428 and resets the load buffer busy flag corresponding to the instructed sub load buffer number.

  At clock 23, an instruction to execute an ADD operation of element numbers 00 to 63 of the ADD-B instruction is issued. The load buffer usage state at this time is shown in FIG. At this time, since there are four vacant spaces in the load buffer # 0, the use load buffer determination unit 202 can secure a sub load buffer for the vector load instruction LD-E, and the vector load processing of the LD-E can be performed. . “1” is set to the load buffer in-use flag corresponding to the four secured sub load buffers. When the vector load instruction LD-E is processed by the used load buffer determination unit 202, four of the sub load buffers 0, 1, 2, and 4 in the load buffer # 0 are secured, and the load buffer securing number notification 13; A value of “11101000” is output in the 23 usage location information.

  Thereafter, all the elements for each division unit of the remaining vector load instructions LD-A-3, LD-B-1, LD-B-2, LD-B-3 and LD-C, LD-D, LD-E Is loaded and a data transfer instruction is issued to the vector calculation register 5-2, and calculation is started for each division unit of the calculation instructions ADD-A-2, ADD-A-3, and ADD-B while maintaining data consistency. Although all the instructions are issued and the execution of the instruction sequence of the present embodiment is completed, the description of the operation becomes redundant, and is omitted.

[Modification]
Hereinafter, modifications of the embodiment of the present invention will be described. Although the basic configuration is as described above, a configuration in which the maximum number of vector elements is not 256 is also possible. The maximum number of vector elements is not particularly limited as long as it is a value that is four times or more the number of processing elements per clock, and can be determined by trade-off between HW (Hardware) amount and performance. For example, if the number of processing elements per clock is four, the above configuration functions effectively and the performance is improved if the maximum number of vector elements is set to 16 times four.

  In the present embodiment, 64 elements obtained by dividing the maximum number of vector elements by 4 are used as one division unit as a load buffer division unit. For this division unit, a value obtained by dividing the maximum number of vector elements by an integer of 2 or more can be set as one division unit.

  Furthermore, in this embodiment, the load buffer prepared for 1024 elements is divided into two stages. That is, first, a load buffer number is assigned in a unit divided by a value twice the maximum vector length (= 512 elements), and then 64 elements (= 256) obtained by dividing one load buffer number by the maximum vector element number by 4. / 4) Divided into 8 units. For this, it is possible to divide the load buffer prepared for 1024 elements into sub load buffer units in one step, for example, to divide the load buffer into 16 pieces every 64 element division units. In this case, instead of the field of the load buffer number in the tag information in the present embodiment disappearing, the 8-bit sub load buffer usage location field is expanded to 16 bits corresponding to the number of divisions.

  In the present embodiment, the load buffer capacity is 1024 elements, but a larger capacity is also possible. The larger the load buffer capacity, the greater the total performance because vector load instructions can be issued prior to the operation instructions. The load buffer capacity can be determined to an optimum amount by trade-off between the HW amount and the performance.

  In the present embodiment, the load buffer number is assigned in units obtained by dividing the load buffer by twice the maximum vector length (= 512 elements), but the load buffer is more than twice the maximum vector length. A load buffer number may be assigned to a unit divided by a value. For example, the number of elements may be divided into halfway numbers such as 896 = 256 * 3 + 128. However, if the division unit of the number of elements is an integral multiple of the maximum vector length, the use efficiency is increased.

  In this embodiment, two vector load instruction issue wait buffers 420 and 430 and two vector operation instruction issue wait buffers 410 and 470 are prepared, but by increasing the inter-instruction consistency maintenance flag as well. It is also possible to increase the buffer for waiting for issuing each instruction.

  In this embodiment, only one data transfer path from the load buffer to the vector operation register is used. However, it is also possible to improve performance by providing a plurality of data transfer paths.

  In the present embodiment, the breakdown of the interface signals between the functional blocks is also illustrated, but a signal different from the breakdown of the illustrated signals may be used as long as necessary information can be transmitted.

  Hereinafter, effects achieved by the vector processing apparatus and the vector loading method according to the present embodiment will be described.

The first effect is that the subsequent vector operation instruction using the data of the vector load instruction can be executed quickly, so that the use efficiency of the vector operation unit is improved and the total system performance is improved.
The reason is that the vector load instruction and subsequent vector operation instructions can be managed for each divided element while maintaining data consistency, and even if not all elements are aligned, the elements are aligned in divided elements. For example, transfer from the load buffer to the vector operation register and control to start a vector operation instruction using the data.

The second effect is that since the load buffer usage efficiency is improved, the vector load instruction processing can be started quickly, thereby reducing the probability of waiting for load data from the memory and improving the total system performance. It is.
The reason is that even if all the elements of the vector load instruction are not aligned, if the elements are aligned in divided elements, transfer from the load buffer to the vector operation register is started and at the same time the load buffer is released in divided elements. By controlling to start the processing of the subsequent vector load instruction if it is released more than the number of division units used in the subsequent vector load instruction even if not all the load buffer transfer start instructions of the vector load instruction are issued .

Configuration diagram Alignment judgment block block diagram Vector instruction issuing department Vector load request processing section Invention configuration time chart Load buffer usage status transition Instruction sequence for explanation

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Instruction decode part 2 Vector load request process part 3 Load data alignment determination part 4 Vector instruction issue part 5 Vector instruction process part 6 Memory access control part 7 Main memory 10 Busy signal 11 Vector load instruction 12 Vector instruction 13 Secure number notification 14 Load Buffer release notification 15 Alignment notification 16 Load buffer transfer start instruction 17 Vector operation start instruction 18 Tag and address 19 Tag 20 Tag and data 21 Data read address 22 Read data 201 Address conversion unit 202 Load buffer determination unit 203 Load buffer busy flag 204 Load buffer busy flag reset signal generation unit 205 Tag generation unit 301 Element number setting unit 302 Element number subtraction counter unit 303 Load buffer number distribution unit 304 Element number counter 05 Alignment determination unit 351 Number of elements scheduled to be stored in sub load buffer 401 Vector instruction buffer unit 402 Vector arithmetic unit busy management unit 403 Load buffer transfer path busy management unit 410, 430 Vector operation instruction issue wait buffer 411 Vector operation instruction information buffer 412 Unissued element Identification flag 413 Inter-instruction consistency maintenance flag 414 Inter-instruction consistency maintenance flag check unit 415 Vector operation instruction issuance check unit 420, 440 Vector load instruction issuance buffer 421 Vector load instruction information buffer 422 Unissued element identification flag 423 Inter-instruction consistency Maintainability flag 424 Load buffer number 425 Load buffer usage location instruction flag 426 Inter-instruction consistency maintenance flag check unit 427 Specific load buffer transfer condition confirmation unit 428 De instruction issue checking unit

Claims (4)

A memory access control unit that reads vector data from the main memory based on the received command;
A load buffer for storing the vector data read by the memory access control unit;
A vector processing unit comprising a vector operation register, and vector processing the vector data transferred from the load buffer to the vector operation register;
The load buffer necessary for storing all the elements of the vector data processed in the received instruction is secured in units of sub load buffers obtained by dividing the load buffer into predetermined elements. A vector load request processing unit for generating a reservation notification indicating the sub load buffer;
A plurality of elements constituting the vector data are divided into a plurality of element groups each having the subload buffer as a unit, and all elements of the plurality of element groups are read from the main memory by the memory access control unit. A load data alignment determination unit that issues an alignment notification for the element group
A vector instruction for controlling to start transfer from the subload buffer corresponding to the alignment notification to the vector processing unit when the alignment notification corresponding to the subload buffer indicated in the reservation notification is issued A vector processing device comprising an issuing unit. When the vector instruction issuance unit divides the vector data into the plurality of element groups and performs the transfer, the vector processing result executed in accordance with the received instruction is used by the vector load instruction in progress. 2. The vector processing device according to claim 1, wherein the vector operation register is controlled to start transfer from the load buffer to the vector processing unit on condition that the vector operation register does not compete with a preceding vector instruction. The vector processing device according to claim 2, wherein when the transfer is started, the vector instruction issuing unit performs control to release the load buffer in which the transfer has been started so that it can be used in a subsequent vector load instruction.   Reading vector data from main memory based on received instructions;
  Storing the vector data read in the reading step in a load buffer;
  Vector processing the vector data transferred from the load buffer to a vector operation register;
  The load buffer necessary for storing all the elements of the vector data processed in the received instruction is secured in units of sub load buffers obtained by dividing the load buffer by a predetermined number of elements. Generating an allocation notification indicating a subload buffer;
  A plurality of elements constituting the vector data are divided into a plurality of element groups each having the subload buffer as a unit, and all elements of the plurality of element groups are read from the main memory by the memory access control unit. Issuing an alignment notification for the set of elements;
  Controlling to start transfer from the subload buffer corresponding to the alignment notification to the vector processing unit when the alignment notification corresponding to the subload buffer indicated in the reservation notification is issued;
  A vector processing method comprising:

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