JP3726092B2 - Vector processing apparatus and vector loading method - Google Patents

Description

The present invention relates to a vector processing device, and more particularly to a vector load instruction processing method for loading vector data from a main storage device into a vector register.

In general, a vector processing device includes a plurality of vector registers that hold vector data loaded from a main storage device, intermediate results during vector operations, and the like, and a vector operation unit that performs operations on vector data held in the vector registers, A large amount of data can be calculated at high speed. In addition, since the access speed of the main storage device is slower than the vector operation speed, the vector data is temporarily transferred between the main storage device and the vector register in order to speed up the loading of the vector data into the vector register. It has a load buffer to store, and starts reading vector data from the main memory to the load buffer when the vector load instruction is decoded. Transfer from the load buffer to the vector register is in the order of instruction issue, that is, in the issue stage of the vector load instruction. The technique to implement is proposed (for example, refer patent document 1).
Japanese Patent Laid-Open No. 2-101576

However, in the configuration in which the transfer from the load buffer to the vector register is activated at the issue stage of the vector load instruction, as long as the vector instruction preceding the vector load instruction remains at the issue stage for reasons such as resource busy, Transfer to the vector register cannot be started, and the speed of vector load processing cannot be increased. In addition, in the configuration in which the transfer from the load buffer to the vector register is started at the issue stage of the vector load instruction, the processing of a plurality of vector load instructions is in the instruction issue order, and the subsequent vector load instruction is performed earlier than the preceding vector load instruction. Instruction overtaking control such as processing cannot be performed.

Therefore, the object of the present invention is to execute the transfer from the load buffer to the vector register not in the order of instruction issuance, but in the order in which all the elements are aligned in the load buffer and the condition that the transfer destination vector register is not busy is satisfied. It is to provide a vector processing device.

The vector processing device of the present invention includes a load buffer for temporarily storing vector data read from the main storage device between a main storage device and a vector register, and a vector read from the main storage device. Detects that the vector register used by the vector load instruction in progress no longer conflicts with the preceding vector instruction between the instruction decode stage and the instruction issue stage of the vector controller that sequentially processes instructions in multiple stages. Resource checking means for starting vector data read from the main memory to the load buffer when decoding a vector load instruction read from the main memory, and all elements of the vector data are loaded into the load buffer As soon as it is stored in the vector register, the vector register used by the vector load instruction precedes That it does not conflict with the vector registers used in the vector instruction is detected by the resource check means the condition that initiates the transfer of vector data from the load buffer to the vector register. More specifically, a main storage device and a processor connected to the main storage device are provided. When the vector instruction read from the main storage device is a vector load instruction, the processor A memory access processing unit for starting reading of vector data, a vector control unit for sequentially processing vector instructions read from the main storage device in a plurality of stages, a plurality of vector registers, one or more vector calculators, and a plurality of loads A vector processing unit including a buffer, and the vector register used by the vector load instruction in progress no longer conflicts with the preceding vector instruction between the instruction decoding stage and the instruction issuing stage of the vector control unit. Resource checking means for detecting and notifying the vector processing unit, The unit stores the vector data read from the main storage device in the load buffer allocated by the memory access processing unit, and when all the elements of the vector data are stored in the load buffer, the vector load instruction A vector that starts transfer of vector data from the load buffer to the vector register on the condition that the vector control unit notifies that the vector register to be used does not conflict with the vector register used in the preceding vector instruction A load management unit is provided.

In the vector loading method of the present invention, a) a load buffer for temporarily storing vector data read from the main memory by the vector load instruction when the vector load instruction read from the main memory is decoded. Initiating reading of vector data from the main memory to the load buffer; b) detecting a first condition that all elements of the vector data are stored in the load buffer; c) the vector Detecting a second condition between the instruction decode stage and the instruction issue stage that the vector register used in the load instruction does not conflict with the vector register used in the preceding vector instruction; d) the first and second stages; As soon as the condition is met, the vector data from the load buffer to the vector register Initiating transfer of data, configured to include a.

According to the present invention, transfer from the load buffer to the vector register can be executed not in the order of instruction issuance, but in the order in which all the elements are aligned in the load buffer and the transfer destination vector register is not busy. For this reason, even if the vector instruction preceding the vector load instruction stays in the issue stage for reasons such as resource busy, transfer from the load buffer to the vector register can be started as soon as the transfer condition is satisfied. Processing speed can be increased. In addition, the processing of multiple vector load instructions can be performed in the order in which the transfer conditions are satisfied, not in the order of instruction issuance, and it is possible to control overtaking of instructions such that subsequent vector load instructions are processed earlier than the preceding vector load instructions. Become.

Referring to FIG. 1, the vector processing device according to the embodiment of the present invention includes a processor 1 and a main storage device 7. The processor 1 and the main storage device 7 read from the processor 1 the signal line 101 for reading out the instructions stored in the main storage device 7 from the processor 1, the vector data stored in the main storage device 7, etc. The vector data and the like generated by the processor 1 are connected to each other by a signal line 102 for writing to the main storage device 7. The signal line 102 is multiplexed so that reading of vector data from the main storage device 7 related to a plurality of vector load instructions can be performed in parallel.

The processor 1 includes an instruction control unit 2, a memory access processing unit 3, a processor network unit 4, a vector control unit 5, and a vector processing unit 6.

The instruction control unit 2 is connected to the main storage device 7 through a signal line 101, is connected to the memory access processing unit 3 through a signal line 103, is connected to the vector control unit 5 through a signal line 104, and is connected to the main storage device through the signal line 101. 7 includes an instruction decoding unit 21 that decodes an instruction read from 7 and a scalar processing unit 22 that executes a process related to the scalar instruction when the decoded instruction is a scalar instruction. Further, the instruction decoding unit 21 outputs the vector instruction to the vector control unit 5 through the signal line 104 when the decoded instruction is a vector instruction, and further, the signal line 103 when the vector instruction is a vector load instruction. The vector load instruction is output to the memory access processing unit 3 through The vector load instruction includes information (for example, the interval between the start address and the vector data) specifying the address of the main memory 7 of the vector data to be loaded, the number of elements of the vector data, and the number of the vector register for loading the vector data ing.

The memory access processing unit 3 controls access to the main storage device 7 and is connected to the instruction control unit 2 through the signal line 103, connected to the processor network unit 4 through the signal line 105, and connected to the vector control unit 5 and the signal. They are connected by a line 106 and are connected to the vector processing unit 6 by a signal line 107. The memory access processing unit 3 decodes a memory access command sent from the command control unit 2 through the signal line 103 and manages the state of the processor network unit 4 and controls a memory access request through the signal line 105 Is sent to the processor network unit 4 to control the data transfer between the signal line 102 to the main storage device 7 and the signal line 108 to the vector processing unit 6. In particular, regarding the vector load instruction, the memory access processing unit 3 performs vacancy management of a plurality of load buffers provided in the vector processing unit 6, and receives a vector load instruction from the instruction control unit 2 through the signal line 103. A free load buffer is allocated for the vector load instruction and managed as a busy state, and a memory access request is attached to the processor through the signal line 105 with a buffer number uniquely identifying the allocated load buffer. It is issued to the network unit 4 and at the same time, the vector control unit 5 is notified via the signal line 106 of which buffer number is assigned to which vector load instruction. When receiving a buffer release notification designating a buffer number from the vector processing unit 6 through the signal line 107, the memory access processing unit 3 again manages the load buffer of that buffer number as an empty state.

The processor network unit 4 is connected to the main storage device 7 through the signal line 102, connected to the memory access processing unit 3 through the signal line 105, connected to the vector processing unit 6 through the signal line 108, and supplied from the memory access processing unit 3. In response to a memory access request, vector data is exchanged between the main storage device 7 and the vector processing unit 6. Regarding the memory access request related to the vector load instruction, the processor network unit 4 associates each element constituting the vector data read from the main storage device 7 with the buffer number associated with the memory access request, and performs vector processing through the signal line 108. Send to unit 6. The signal line 108 is multiplexed so that vector data related to a plurality of memory access requests can be supplied to the vector processing unit 6 in parallel.

The vector processing unit 6 is connected to the memory access processing unit 3 through a signal line 107, connected to the processor network unit 4 through a signal line 108, connected to the vector control unit 5 through signal lines 109 and 110, and Has the ability to perform vector operations. The vector processing unit 6 includes at least one vector pipeline calculator 61. The vector pipeline arithmetic unit 61 includes a plurality of vector registers 62 that store vector data, one or more vector arithmetic units 63 that perform vector operations on the vector data stored in the vector register 62, and the main storage device 7. A crossbar switch circuit that distributes the vector data output from the plurality of load buffers 64, the vector load management unit 65, the vector calculator 63, and the load buffer 64 to the vector register 62 for temporarily storing the vector data read from 66. It should be noted that the configuration related to the store, such as a store buffer for storing the vector data obtained by vector calculation in the main storage device 7, is not shown because it is not directly related to the present invention.

The vector load management unit 65 is connected to the memory access processing unit 3 through the signal line 107, is connected to the processor network unit 4 through the signal line 108, is connected to the vector control unit 5 through the signal lines 109 to 111, and passes through the signal line 108. The elements of the transmitted vector data are temporarily stored in the load buffer 64 having the buffer number associated therewith, and then the vector data stored in the load buffer 64 is transferred to the vector register 62. FIG. 2 shows a configuration example of the vector load management unit 65.

Referring to FIG. 2, an example of the vector load management unit 65 includes a register group 651, a register setting unit 652, a write unit 653, and a read unit 654.

The register group 651 includes a set of registers 651-0 to 651-n corresponding to the load buffer 64 on a one-to-one basis. Each register 651-i (i = 0 to n) includes a load buffer number field 6511, a vector. It has a register (VAR) number field 6512, a resource check flag field 6513, a write element number field 6514, and a read element number field 6515. In the load buffer number field 6511, the buffer number of the load buffer 64 is fixedly set. In the vector register number field 6512, the number of the vector register 62 that stores vector data to be loaded by the vector load instruction is set. A resource check flag field 6513 is set with a resource check flag indicating whether or not the vector register 62 used in the vector load instruction conflicts with the preceding vector instruction. In the write element number field 6514 and the read element number field 6515, the number of elements of vector data to be loaded by the vector load instruction is set as an initial value. The number of write elements set in the write element number field 6514 is subtracted in accordance with the writing of the vector data element to the load buffer 64, and becomes zero when the writing of all the elements to the load buffer 64 is completed. The number of read elements set in the number of read elements field 6515 is subtracted in response to reading from the load buffer 64 to the vector register 62, and becomes 0 when reading of all elements from the load buffer 64 is completed.

The register setting unit 652 is connected to the vector control unit 5 through the signal line 109, and performs initial setting of the register group 651 and the like. When the vector setting instruction information including the load buffer number, the vector register number, and the number of elements is transmitted from the vector control unit 5 through the signal line 109, the register setting unit 652 has the load buffer number in the load buffer number field 6511. The vector register number in the vector load instruction information is set in the vector register number field 6512 of the register 651-i, the number of elements in the vector load instruction information is set in the write element number field 6514 and the read element number field 6515, and the resource check is performed. In the flag field 6513, a flag value 1 indicating that there is a resource conflict is set. Further, when a resource check OK signal designating a load buffer number is transmitted from the vector control unit 5 through the signal line 109, the register setting unit 652 has a register 651-i having the load buffer number in the load buffer number field 6511. The flag in the resource check flag field 6513 is rewritten to a value 0 indicating no resource conflict.

The write unit 653 is connected to the processor network unit 4 through the signal line 108 and writes vector data to the load buffer 64. When the write unit 653 receives an element of vector data from the processor network unit 4 through the signal line 108, the write unit 653 writes the element into the load buffer 64 having the load buffer number associated with the received element, and the load buffer number is set to the load buffer number. The value of the write element number field 6514 of the register 651-i in the field 6511 is subtracted by the number of written elements.

The read unit 654 is connected to the vector control unit 5 through signal lines 109 and 110 and transfers vector data from the load buffer 64 to the vector register 62. For the register 651-i in which the write element number field 6514 is initialized to the total number of elements by the register setting unit 652, the read unit 654 stores the load buffer 64 having the buffer number set in the load buffer number field 6511 of the register. It monitors whether the condition for transferring data to the vector register 62 of the number set in the vector register number field 6512 of that register is satisfied. (1) All elements of vector data have been stored in the load buffer 64 (the value of the write element number field 6514 is 0). (2) The preceding vector instruction does not conflict with the vector register (resource check flag field 6513). If the two requirements are satisfied, it is determined that transfer is possible.

When the read unit 654 determines that transfer is possible for a certain register 651-i, the buffer number and vector set in the load buffer number field 6511 of the register 651-i to the vector control unit 5 through the signal line 110. After sending a transfer start notification specifying the vector register number set in the register number field 6512, the data stored in the load buffer 64 having the buffer number set in the load buffer number field 6511 is read sequentially, Data is written to the vector register 62 of the number set in the vector register number field 6512 through the crossbar switch circuit 66. At this time, every time one element of the vector data is read from the load buffer 64, the value of the read element number field 6515 is decremented by one. When the value of the read element number field 6515 becomes 0, the transfer is completed, and the read unit 654 reads the buffer number set in the load buffer number field 6511 of the register 651-i and the vector register set in the vector register number field 6512. A transfer end notification designating a number is sent to the vector control unit 5 through the signal line 110, and at the same time, a buffer release notification designating the buffer number set in the load buffer number field 6511 of the register 651-i is stored in the memory through the signal line 107. The data is sent to the access processing unit 3, and the fields 6512 to 6515 of the register 651-i are initialized to NULL, for example.

Referring again to FIG. 1, the vector control unit 5 is connected to the instruction control unit 2 through the signal line 104, connected to the memory access processing unit 3 through the signal line 106, and connected to the vector processing unit 6 through the signal lines 109 to 111. And issue control of vector instructions. The vector control unit 5 divides a vector instruction execution cycle into a plurality of stages such as instruction decoding, operand calculation and extraction, and instruction issuance, and processing of each stage is performed by independent hardware. Thus, a plurality of vector instructions are processed in parallel. For this reason, the vector control unit 5 includes an intermediate between the instruction decode unit 51 that decodes the vector instruction input from the instruction control unit 2 through the signal line 104 and the instruction issue stage register 52 that is the final stage. There are provided several instruction registers 53, 54, and 55 that hold decode information and the like of instructions existing in each stage, and decoders 56 and 57 that execute processing in an intermediate stage. The number of stages differs depending on the processor architecture. The instruction issuing unit 58 checks whether or not the instruction stored in the register 52 at the instruction issuing stage can be issued. If the instruction is not issued, the instruction issuing unit 58 waits until the instruction can be issued. An instruction issuance is notified to the unit 6, and accompanying information necessary for processing is simultaneously notified. Whether or not the instruction stored in the register 52 can be issued is determined by checking whether or not the resource is busy for each resource such as the vector register 62 and the vector calculator 63 in the vector pipeline calculator 61 of the vector processing unit 6. Of the busy flags of the busy flag group 59 to be held, the determination is performed based on whether the busy flag of the resource used by the instruction stored in the register 52 at the instruction issue stage is not busy.

In the present embodiment, for the vector load instruction, all elements of the vector data read from the main storage device 7 are stored in the load buffer 64, and the vector instruction preceded by the resource used by the vector load instruction If there is no conflict with the resources used in step 1, the transfer from the load buffer 64 to the vector register 62 is started immediately without waiting for the vector load instruction to arrive at the register 52 in the instruction issue stage. The write / load counter unit 5A, the read counter unit 5B, and the load instruction information management unit 5C of the vector control unit 5 are provided for such control.

The write / load counter unit 5A manages a vector register 62 used for writing or loading with a vector instruction being processed in the vector control unit 5 and the number of instructions used. A configuration example is shown in the block of the write / load counter unit 5A in FIG. The write / load counter unit 5A in this example includes a counter 5AC including a vector register 62 existing in the vector processing unit 6 and count units 5A-0 to 5A-m corresponding one-to-one. The initial values of all the counting units 5A-0 to 5A-m of the counter 5AC are zero. When the instruction decoded by the instruction decoding unit 51 is an instruction for writing to the vector register 62 or an instruction for loading data into the vector register 62, the counter 5AC displays the vector register used by the instruction output from the decoding unit 51. Based on the information 62, the value of the count unit 5A-j (j is 0 to m) corresponding to the vector register 62 is incremented by one. In addition, when processing of the instruction in the register 52 at the instruction issuing stage is completed, the instruction issuing unit 58 determines that the instruction is an instruction to write to the vector register 62 or an instruction to load data to the vector register 62. At the timing when the busy flag of the used vector register 62 is reset, the number of the vector register 62 is notified to the write / load counter unit 5A, and the counter 5AC counts the counting unit 5A corresponding to the notified vector register 62. Decrease the value of -j by -1.

The read counter unit 5B manages the vector register 62 to be read by the vector command being processed in the vector control unit 5 and the number of used instructions. A configuration example is shown in the block of the read counter section 5B in FIG. The read counter unit 5B in this example includes a counter 5BC including a vector register 62 existing in the vector processing unit 6 and a count unit 5B-0 to 5B-m corresponding one-to-one. The initial values of all the counting units 5B-0 to 5B-m of the counter 5BC are zero. When the instruction decoded by the instruction decoding unit 51 is an instruction for reading the vector register 62, the counter 5BC determines the vector register based on the information of the vector register 62 used by the instruction output from the decoding unit 51. The value of the count unit 5B-j corresponding to 62 is incremented by one. Further, when processing of the instruction in the register 52 at the instruction issuing stage is completed, the instruction issuing unit 58 resets the busy flag of the vector register 62 used in the instruction when the instruction is an instruction that reads the vector register 62. At the timing, the number of the vector register 62 is notified to the read counter unit 5B, and the counter 5BC decrements the value of the count unit 5B-j corresponding to the notified vector register 62 by -1.

The load instruction information management unit 5C is a part that manages a vector load instruction in progress in the vector control unit 5 and notifies the vector load management unit 65 of the vector processing unit 6 of necessary information. A configuration example is shown in the block of the load instruction information management unit 5C in FIG. The load instruction information management unit 5C in this example includes a register group 5C1, a resource information registration unit 5C2, and a resource information check unit 5C3.

The register group 5C1 is composed of a set of registers 5C1-0 to 5C1-n corresponding one-to-one with the load buffer 64 existing in the vector processing unit 6, and each register 5C1-i (i = 0 to n) It has a load buffer number field 5C11, a vector register number field 5C12, an element number field 5C13, a write / load counter value field 5C14, and a read counter value field 5C15. In the load buffer number field 5C11, the buffer number of the load buffer 64 is fixedly set. In the vector register number field 5C12, the number of the vector register 62 that stores vector data to be loaded by the vector load instruction is set. In the element number field 5C13, the number of elements of vector data loaded by the vector load instruction is set. In the write / load counter value field 5C14, the number of vector instructions that use the vector register 62 of the number set in the vector register number field 5C12 for writing and loading is set. In the read counter value field 5C15, the number of vector instructions that use the vector register 62 of the number set in the vector register number field 5C12 for reading is set.

The resource information registration unit 5C2 receives the output of the instruction register 53, the output of the write / load counter unit 5A, and the output of the read counter unit 5B. In the instruction register 53, when the vector instruction decoded by the instruction decoding unit 51 is a vector load instruction, the instruction notified from the memory access processing unit 3 through the signal line 106 in addition to the decoding information of the instruction decoding unit 51 The number of the load buffer 64 assigned to the vector load instruction is held. When the resource information registration unit 5C2 inputs the load buffer number from the instruction register 53, the instruction register 53 is stored in the vector register number field 5C12 and the element number field 5C13 of the register 5C1-i having the load buffer number in the load buffer number field 5C11. Sets the vector register number and the number of elements output from. Of the count units 5A-0 to 5A-m of the counter 5AC of the write / load counter unit 5A, the contents of the count unit corresponding to the vector register number set in the vector register number field 5C12 are written in the write / load counter value field 5C14. Among the count units 5B-0 to 5B-m of the counter 5BC of the read counter unit 5B, the content of the count unit corresponding to the vector register number set in the vector register number field 5C12 is set in the read counter value field 5C15 To do. Then, the vector load management section 65 receives the vector load instruction information including the load buffer number in the load buffer number field 5C11, the vector register number set in the vector register number field 5C12, and the number of elements set in the element number field 5C13 through the signal line 109. Output to.

The resource information check unit 5C3 updates the write / load counter value field 5C14 and the read counter value field 5C15 of the register group 5C1 in response to the notification from the instruction issuing unit 58, so that the conflict between the preceding vector instruction and the vector register does not occur. At the same time, a resource check OK signal designating a load buffer number is transmitted to the vector load management unit 65 through the signal line 109. Specifically, when the instruction issuing unit 58 finishes processing the instruction in the register 52 at the instruction issuing stage, the instruction is an instruction to write to the vector register 62 or an instruction to load data to the vector register 62. At the timing when the busy flag of the vector register 62 used in the instruction is reset, the number of the vector register 62 is notified to the load instruction information management unit 5C, and the resource information check unit 5C3 notifies the notified vector register The value of the write / load counter value field 5C14 of the register having the number in the vector register number field 5C12 is decremented by one. In addition, when the instruction issuing unit 58 finishes processing the instruction in the register 52 at the instruction issuing stage, if the instruction is an instruction that reads the vector register 62, the instruction issuing unit 58 resets the busy flag of the vector register 62 used in the instruction. At the timing, the number of the vector register 62 is notified to the load instruction information management unit 5C, and the resource information check unit 5C3 reads the register counter having the notified vector register number in the vector register number field 5C12. Subtract 1 from the value in the value field 5C15. Then, when the value of the write / load counter value field 5C14 is 1 and the value of the read counter value field 5C15 is 0, the resource information check unit 5C3 is set in the load buffer number field 5C11 of the register. A resource check OK signal designating the specified load buffer number is transmitted to the vector load management unit 65 through the signal line 109.

Referring to FIG. 1 again, when the load buffer number management unit 5D receives a transfer start notification from the vector load management unit 65 through the signal line 110, the load buffer number management unit 5D holds the number of the load buffer 64 included in the notification. The load buffer number management unit 5D is referred to by the instruction issuing unit 58 when processing the vector load instruction stored in the instruction register 52 in the instruction issuing stage. The load buffer number stored in the load buffer number management unit 5D is deleted by the instruction issuing unit 58 when a vector load instruction using the load buffer of the load buffer number is stored in the instruction register 52 in the instruction issuing stage. Is done.

As described above, the busy flag group 59 holds whether or not the resource is busy for each resource such as the vector computing unit 63 and the vector register 62. Basically, the instruction issuing unit 58 is in the instruction issuing stage. When the instruction stored in the instruction register 52 is issued, the resource used by the instruction is updated to the busy state, and the busy state is released when the execution of the instruction is completed. However, in this embodiment, since the operation of transferring the contents of the load buffer 64 to the vector register 62 is started at the judgment of the vector load managing unit 65, the transfer sent from the vector load managing unit 65 through the signal line 110 is started. The busy flag group 59 is also updated by the start notification and the transfer end notification. Specifically, when a transfer start notification is received from the vector load management unit 65 through the signal line 110, the vector register specified by the number of the vector register 62 included in the notification is updated to the busy state, and the vector is transmitted through the signal line 110. When the transfer end notification is received from the load management unit 65, the busy state of the vector register specified by the number of the vector register 62 included in the notification is canceled.

Next, the operation of the vector processing apparatus according to the present embodiment will be described with a focus on vector load instruction processing.

When the instruction read from the main storage device 7 through the signal line 101 is a vector load instruction, the instruction decoding unit 21 of the instruction control unit 2 sends the vector load instruction to the memory access processing unit 3 through the signal line 103 at the same time. The signal is sent to the vector control unit 5 through the signal line 104. For convenience of the following description, the vector load instruction is a vector load instruction having as parameters the start address X of the main storage device 7, the interval D of vector data to be accessed, the number of elements 100, and the vector register number 1 for loading vector data. VLD1.

The memory access processing unit 3 secures one empty load buffer from among the plurality of load buffers 64, designates the number of the secured load buffer, and transmits the vector load instruction transmitted from the instruction control unit 2 A memory access request for the VLD 1 is issued to the processor network unit 4 through the signal line 105, and at the same time, the number of the reserved load buffer is notified to the vector control unit 5 through the signal line 106. It is assumed that the number of the load buffer secured now is 0.

The instruction decode unit 51 of the vector control unit 5 decodes the vector load instruction VLD 1, decodes information such as the vector register number 1 and the number of elements 100, and the load buffer number 0 notified from the memory access processing unit 3 through the signal line 106. Information is stored in the instruction register 53. Since it is a vector load instruction, the instruction decode unit 51 increments the value of the count unit 5A-1 corresponding to the vector register number 1 in the counter 5AC of the write / load counter unit 5A. Next, the contents of the instruction register 53 are stored in the instruction register 54 and simultaneously output to the load instruction information management unit 5C. Since the load buffer number 0 is output from the instruction register 53, the resource information registration unit 5C2 of the load instruction information management unit 5C has the load buffer number field 0C in the load buffer number field 5C11 and the vector register number field 5C12 of the register 5C1-0. The vector register number 1 and the element number 100 output from the instruction register 53 are set in the element number field 5C13, and the count unit 5A-1 corresponding to the vector register number 1 in the counter 5AC of the write / load instruction counter unit 5A is set. The value is set in the write / load counter value field 5C14, and the value of the count unit 5B-1 corresponding to the vector register number 1 in the counter 5BC of the read instruction counter unit 5B is set in the read counter value field 5C15. Then, the resource information registration unit 5C2 notifies the vector load management unit 65 through the signal line 109 of vector load instruction information including information of the load buffer number 0, the vector register number 1, and the number of elements 100. The register setting unit 652 of the vector load management unit 65 sets the vector register number 1 in the vector register number field 6512 in the register 651-0 in which the load buffer number 0 is set in the load buffer number field 6511, and the write element number field. The element number 100 is set in 6514 and the read element number field 6515, and the flag in the resource check flag field 6513 is set to a value of 1.

Here, the value of the write / load counter value field 5C14 and the value of the read counter value field 5C15 of the register 5C1-0 of the load instruction information management unit 5C precedes the vector load instruction VLD1. It is determined by the type and number of vector instructions in progress, and can be roughly divided into the following cases.

(1) Case 1: When the vector register used by the vector load instruction VLD1 does not conflict with the vector register used by the preceding instruction. At this time, the value of the write / load counter value field 5C14 is 1, and the value of the read counter value field 5C15 is 0.
(2) Case 2: When the vector register used by the vector load instruction VLD1 conflicts with the vector register used by the preceding instruction. At this time, assuming that the number of vector instructions in progress using the vector register used by the vector load instruction VLD1 for writing is a, the value of the write / load counter value field 5C14 is a + 1, and the vector load instruction VLD1 uses it. Assuming that the number of vector instructions in progress using the vector register to be read is b, the value of the read counter value field 5C15 is b. Since the memory access processing unit 3 does not assign the same load buffer 64 to a plurality of vector load instructions at the same time, even if a vector load instruction preceding the vector load instruction VLD1 is in progress, the write / load counter value There is no effect on the value of field 5C14.

In case 1, the resource information check unit 5C3 of the load instruction information management unit 5C has a value of 1 in the write / load counter value field 5C14 of the register 5C1-0 registered by the resource information registration unit 5C2 and a read counter value. Since the value of the field 5C15 is 0, it is determined that the resource of the vector load instruction VLD1 does not compete with other vector instructions in progress, and the resource check OK signal designating the load buffer number 0 is sent through the signal line 109 to the vector load management unit. 65 is notified. On the other hand, in case 2, the resource information check unit 5C3 sets the value of the write / load counter value field 5C14 of the register 5C1-0 registered by the resource information registration unit 5C2 to 1 and the value of the read counter value field 5C15. Is monitored to become 0. Each time the vector control unit 5 finishes executing the in-progress vector instruction preceding the vector load instruction VLD1, the resource information check unit 5C3 responds to the notification from the instruction issue unit 58 in the write / load counter value field 5C14. The value and the value of the read counter value field 5C15 are subtracted. When the value of the write / load counter value field 5C14 of the register 5C1-0 becomes 1 and the value of the read counter value field 5C15 becomes 0, the resource information check unit 5C3 sets the resource of the vector load instruction VLD1. It is determined that there is no conflict with other vector instructions being applied, and a resource check OK signal designating the load buffer number 0 is notified to the vector load management unit 65 through the signal line 109.

The register setting unit 652 of the vector load management unit 65 changes the flag value of the resource check flag field 6513 of the register 651-0 having the notified load buffer number 0 in the load buffer number field 6511 from 1 to 0.

In response to the memory access request issued from the memory access processing unit 3, the processor network unit 4 sequentially selects the element of the start address X of the main storage device 7, the element of the address of the start address + the distance D,. Read out, load the load buffer number 0 and send it to the vector load management unit 65 via the signal line 108. The write unit 653 of the vector load management unit 65 stores each received element in the load buffer 64 with the load buffer number 0, and the write element of the register 651-0 in which the load buffer number 0 is set in the load buffer number field 6511 The value in the number field 6514 is sequentially subtracted. When all 100 elements of data are stored in the load buffer 64 with the load buffer number 0, the value of the write element number field 6514 becomes 0.

The read unit 654 recognizes that all the elements are stored in the load buffer 64 when the value of the write element number field 6514 of the register 651-0 becomes 0, and the flag value of the resource check flag field 6513 is 0. Or 1 is determined. If it is 1, wait until it becomes 0, if it is 0 or 0, immediately if the path to the crossbar switch circuit 66 is free, if it is not free, as soon as it is free, load buffer number 0 and vector A transfer start notification designating the register number 1 is sent to the vector control unit 5 through the signal line 110. The load buffer number management unit 5D of the vector control unit 5 holds the load buffer number 0, and the busy flag group 59 manages the vector register of the vector register number 1 as a busy state. The read unit 654 starts a process of transferring the contents of the load buffer 64 with the load buffer number 0 to the vector register 62 with the vector register number 1 through the crossbar switch circuit 66 at the same time that the transfer start notification is given.

Each time one element is transferred, the read unit 654 decrements the value of the read element number field 6515 of the register 651-0 by 1, and ends the transfer when the value of the read element number field 6515 becomes 0. Then, a transfer end notification designating the load buffer number 0 and the vector register number 1 is sent to the vector control unit 5 through the signal line 110, and simultaneously, a buffer release notification designating the load buffer number 0 is sent through the signal line 107 to the memory access processing unit. 3 to send. The busy flag group 59 of the vector control unit 5 cancels the busy state of the vector register of vector register number 1. Further, the memory access processing unit 3 manages the notified load buffer with the load buffer number 0 as an empty state.

In the vector control unit 5, the vector load instruction VLD1 is stored in the instruction register 54, then processed in each subsequent stage, and finally stored in the instruction register 52 in the instruction issue stage. The instruction issuing unit 58 manages the load buffer number 0 (this is sequentially carried from the instruction register 53 and held in the instruction register 52) used by the vector load instruction VLD1 stored in the instruction register 52. The load buffer number stored in the unit 5D is compared, and if the load buffer number 0 is not stored in the load buffer number management unit 5D, the load buffer number 0 is waited to be stored, and is stored or stored while waiting. Then, the processing of the instruction is terminated without issuing the vector load instruction VLD1, and the load buffer number 0 is deleted from the load buffer number management unit 5D. The reason why the instruction issuing unit 58 does not issue the instruction of the vector load instruction VLD1 in this way is that the resource used by the vector load instruction VLD1 does not compete with the resource of the preceding instruction, and all elements of the vector data are stored in the load buffer. When stored, the vector load management unit 65 starts the transfer to the vector register, so that the instruction issuing unit 58 does not need to execute the instruction issuing process of the vector load instruction VLD1.

As described above, according to the present embodiment, the transfer from the load buffer 64 with the buffer number 0 to the vector register 62 with the register number 1 is performed without waiting for the vector load instruction VLD1 to arrive at the instruction register 52 in the instruction issue stage. Therefore, it is possible to speed up the processing of the subsequent vector instruction using the vector register 62 of the register number 1, and to speed up the release of the load buffer 64 of the buffer number 0, thereby improving the processing efficiency.

In the above description, attention is paid to one vector load instruction VLD1, but the same operation is performed even when a plurality of vector load instructions are consecutive. In this case, in this embodiment, the transfer to the vector register is started not in the order in which the vector load instructions arrive at the instruction issue stage but in the order in which all elements are aligned in the load buffer and there is no resource contention. It is also possible to transfer the vector data of the subsequent vector load instruction to the vector register before the vector load instruction to be performed. For example, the preceding vector load instruction VLD1 waits for the end of the preceding vector instruction in progress using the vector register used in its own instruction, or all elements are stored in the load buffer because of the large number of elements. All the elements of the subsequent vector load instruction VLD2 are stored in the load buffer and the vector register used by the vector load instruction VLD2 does not conflict with the resources of the preceding vector instruction in progress. Then, the read unit 654 of the vector load management unit 65 starts the transfer from the load buffer to the vector register for the vector load instruction VLD2 prior to the vector load instruction VLD1.

It is a block diagram of an embodiment of the invention. It is a block diagram which shows the structural example of a vector load management part. It is a block diagram which shows the example of a structure of a write / load counter part, a read counter part, and a load command information management part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Instruction control part 3 ... Memory access processing part 4 ... Processor network part 5 ... Vector control part 6 ... Vector processing part 7 ... Main memory

Claims (3)

A load buffer for temporarily storing vector data read from the main storage device is provided between the main storage device and the vector register, and vector instructions read from the main storage device are sequentially processed in a plurality of stages. Resource check means for detecting that the vector register used by the vector load instruction in progress does not conflict with the preceding vector instruction between the instruction decoding stage and the instruction issuing stage of the vector control unit, When the vector load instruction read from the main storage device is decoded, reading of the vector data from the main storage device to the load buffer is activated, and the vector load is started as soon as all elements of the vector data are stored in the load buffer. The vector register used in the instruction must be used in the preceding vector instruction. That it does not conflict with torr register has been detected in the resource check means on condition, the vector processor to start the transfer of vector data from the load buffer to the vector register. A main storage device and a processor connected to the main storage device, wherein the processor activates reading of vector data from the main storage device when the vector instruction read from the main storage device is a vector load instruction A memory access processing unit, a vector control unit for sequentially processing vector instructions read from the main storage device at a plurality of stages, a vector processing comprising a plurality of vector registers, one or more vector computing units, and a plurality of load buffers And detecting that the vector register used by the vector load instruction in progress no longer conflicts with the preceding vector instruction between the instruction decoding stage and the instruction issuing stage of the vector control section. Resource checking means for notifying the processing unit, wherein the vector processing unit includes the main memory. The vector data read from the device is stored in the load buffer allocated by the memory access processing unit, and as soon as all elements of the vector data are stored in the load buffer, the vector register used in the vector load instruction is preceded. A vector load management unit for starting transfer of vector data from the load buffer to the vector register on the condition that the vector control unit is informed that there is no conflict with the vector register used in the vector instruction to be executed A vector processing device. a) When a vector load instruction read from the main storage device is decoded, a load buffer for temporarily storing vector data read from the main storage device by the vector load instruction is allocated, and the load buffer is transferred from the main storage device to the load buffer. Starting the reading of the vector data to b) detecting the first condition that all elements of the vector data are stored in the load buffer; c) preceding the vector register used in the vector load instruction Detecting a second condition between the instruction decoding stage and the instruction issuing stage that does not conflict with the vector register used in the vector instruction to be used; d) as soon as the first and second conditions are satisfied, from the load buffer Initiating transfer of vector data to the vector register. Vector load wherein the.

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