JP4631442B2 - Processor - Google Patents

Description

  The present invention relates to a processor, and more particularly to a processor capable of executing a plurality of tasks or threads in parallel.

  Generally, a processor has a hardware configuration dedicated to each process in order to execute pipeline processing. A configuration in which a plurality of such processors are provided and all the processors are controlled in an integrated manner is called a multi-thread processor. Many multi-thread processors share a part of the hardware configuration among a plurality of processors, thereby efficiently using hardware resources and suppressing an increase in circuit scale.

According to the multi-thread processor, a plurality of instructions can be executed in parallel, and the processing speed of the processor can be significantly increased as compared with a single-thread processor.
As prior art relating to a multi-thread processor, for example, inventions described in Patent Documents 1 to 3 are listed. The microcomputer according to the invention of Patent Document 1 is configured such that a microcomputer composed of a plurality of CPUs (Central Processing Units) reads instructions from a memory.

  The invention described in Patent Document 1 divides the memory space of the memory into program areas for each CPU, and stores the offset addresses of the divided program areas in a register. When the CPU accesses the memory, the program area to be accessed is selected by adding the offset address corresponding to the CPU and the instruction fetch address. According to such a patent document 1, it is possible to develop software without the programmer being aware of the memory bank, and the memory space can be effectively used.

  In the invention described in Patent Document 2, a CPU, an instruction memory from which an instruction is read by the CPU, a data memory from which data is read, an instruction memory, and a shared memory bank that can be mapped by the data memory are provided. According to Patent Document 2, it is possible to provide an integrated circuit that can cope with a case where the amount of memory required for an instruction memory or a data memory cannot be accurately estimated during software development.

Furthermore, the invention described in Patent Document 3 includes a plurality of processors and a shared memory accessed by the plurality of processors. Each processor is provided with a local memory having a continuous address with the shared memory, and subpages in the shared memory are stored in the local memory. According to such an invention of Patent Document 3, it is possible to reduce the load on the snoop process between the processors.
JP-A-9-325910 JP 2004-171232 A Japanese Patent Laid-Open No. 11-120078

  By the way, in a multi-thread processor, an instruction is read from a memory by each of a plurality of processors. For this reason, in a multi-thread processor, it is necessary to read out an instruction sequence at a higher speed and process it at an appropriate timing as compared with a single-thread processor. If the processor cannot read the instruction at an appropriate timing, the program being executed by all the processors of the multi-thread processor may stop due to waiting for the instruction to be read from the memory. Note that the fact that a program stops due to such a factor is generally called a memory stall.

  However, none of the above-described Patent Documents 1 to 3 is intended to supply instructions to the multithread processor at an appropriate timing. For this reason, with the configurations of Patent Documents 1 to 3, it is difficult to realize a read speed sufficient for operation when considering operating the processor at a high speed of about 200 MHz, for example. For this reason, in a processor to which the conventional technology is applied, it is not possible to suppress the occurrence of memory stalls when operating at high speed, and the processing capability of the processor is limited by the limitation of the operation speed.

Furthermore, in each of Patent Documents 1 to 3, the memory is divided into banks, and the instruction sequence is read in parallel, thereby speeding up the reading of the instructions and preventing memory stalls.
The configuration in which the memory is divided into banks is advantageous in increasing the operation speed of the multi-thread processor. However, the banked memory generally stores different types of data in each bank. For this reason, unless an appropriate memory space is set in a bank for any of a plurality of types of data, requests from a plurality of processors are concentrated in one bank, causing a reduction in processing performance. Furthermore, there is a possibility that an empty area where data is not stored is generated among a plurality of banks, and the use efficiency of the memory may be lowered.

In addition, according to the prior art, there is one that adopts a multi-port to speed up instruction reading. However, since a multi-port configuration is relatively expensive, it is desirable to employ a lower cost single port. FIG. 11 shows an example of the configuration of a processor connected to a banked memory in a multiport connection.
The present invention has been made in view of the above points, and provides a processor capable of reading a sequence of instructions at an appropriate timing even when operating at a relatively high speed and obtaining high processing capability. With the goal. In addition, since the instruction sequence can be read at an appropriate timing, the present invention avoids memory banking to improve memory utilization efficiency, and adopts a single port to reduce the circuit scale and reduce the cost. An object of the present invention is to provide a processor capable of realizing the above.

  In order to solve the above-described problems, a processor according to the present invention is a processor that fetches an instruction from a memory in which an instruction is stored. The processor fetches an instruction, and the instruction requested by the fetch means Memory control means for transferring to the fetch means that requested the instruction, wherein the fetch means is an instruction storage means for storing the transferred instructions, and an instruction that is actually executed among the instructions stored in the instruction storage means. Based on the state of a certain actual instruction, the urgency level setting means indicating the degree of urgency of instruction acquisition in the fetch means, and the urgency level set by the urgency level setting means are output to the memory control means, Fetch request means for requesting transfer, and the memory control means is based on the urgency level input by the fetch request means. Fetch priority setting means for determining the priority of instruction transfer; and memory access control means for reading an instruction relating to a fetch request from the memory according to the priority set by the fetch priority setting means. To do.

  According to such an invention, instructions transferred to the fetch means are accumulated, and the degree of urgency of instruction acquisition in the fetch means based on the state of the actual instructions that are actually executed among the accumulated instructions Can be set. Then, the set urgency level is output to the memory control means to request the command transfer. Further, the memory control means can determine the priority order of instruction transfer based on the outputted urgency level, and can read out the instruction relating to the fetch request from the memory according to the set priority order.

For this reason, the present invention provides a processor capable of reading a sequence of instructions at an appropriate timing without increasing the access speed to the memory even when operating at a relatively high speed, and preventing a memory stall. can do.
Further, according to the present invention, it is possible to read an instruction sequence at an appropriate timing without performing instruction fetching in parallel, and it is possible to prevent a memory stall. For this reason, it is possible to provide a processor capable of improving the memory utilization efficiency by avoiding the banking of instructions and also adopting a single port to reduce the circuit scale and reduce the cost.

  The processor according to the present invention is a processor for executing a plurality of instructions in parallel, a plurality of fetch means for fetching instructions, and a memory for transferring the instruction requested by the fetch means to the fetch means that requested the instruction. Control means, wherein the fetch means is based on an instruction storage means for storing transferred instructions and a state of an actual instruction that is an instruction actually executed among the instructions stored in the instruction storage means. Urgent level setting means for indicating the degree of urgency of instruction acquisition in the fetch means; fetch request means for outputting the urgency level set by the urgency level setting means to the memory control means and requesting transfer of instructions; And the memory control means determines the priority of instruction transfer based on the urgency level output by the fetch request means. The previous order setting means, characterized in that it comprises, a memory access control means for reading such instruction fetch request from the memory according to the priority set by the fetch priority setting means.

  According to such an invention, each of the plurality of fetch means accumulates the transferred instruction, and the instruction acquisition in the fetch means is based on the state of the actual instruction that is the actually executed instruction among the accumulated instructions. The degree of urgency can be set. Then, the set urgency level is output to the memory control means to request the command transfer. Further, the memory control means can determine the priority order of instruction transfer based on the outputted urgency level, and can read out the instruction relating to the fetch request from the memory according to the set priority order.

For this reason, the present invention provides a processor capable of reading a sequence of instructions at an appropriate timing without increasing the access speed to the memory even when operating at a relatively high speed, and preventing a memory stall. can do.
Further, according to the present invention, even when instructions are fetched in parallel, an instruction sequence can be read at an appropriate timing, and a memory stall can be prevented. For this reason, even in a so-called multi-thread processor that executes instructions in parallel, it avoids banking of instructions to increase the memory utilization efficiency, and also uses a single port to reduce the circuit scale and reduce costs. A realizable processor can be provided.

Further, the present invention is characterized in that the urgency level setting means sets the urgency level according to the number of instructions actually executed.
According to such an invention, it is possible to preferentially execute fetching by fetch means that is highly likely to cause a memory stall due to a lack of instructions to be processed. For this reason, memory stall can be effectively prevented.

In the processor according to the present invention, when the fetch storage unit stores a plurality of execution scheduled instructions having different data lengths, the urgency setting unit determines the number of stored instructions based on the data length of the execution scheduled instruction. It is characterized by that.
According to such an invention, even when an instruction with a variable data length is handled, the number of instructions stored in the fetch storage means can be accurately determined. For this reason, an instruction sequence can be read at a more appropriate timing.

The processor according to the present invention further includes a branch instruction detection unit that detects that a branch instruction has been fetched by the fetch unit, and the urgency level setting unit includes the branch instruction detection unit. The urgent level is set by detecting the fetch of the branch instruction by the corresponding fetch means.
According to such an invention, it is possible to preferentially execute the fetch of the fetch unit in which the instruction stored in the fetch storage unit is cleared by executing the branch instruction. For this reason, memory stall can be effectively prevented.

  In the processor according to the present invention, the second fetching unit may receive the second instruction after the first fetching unit requests the first instruction among the plurality of fetching units and before the transfer of the first instruction is completed. When the transfer of the second instruction is completed before the transfer of the first instruction, the priority setting means updates the instruction transfer priority setting of the first instruction to a higher order. It is characterized by that.

According to such an invention, when a fetch overtaking occurs, it is possible to prevent a previously requested fetch with a low urgency from being waited for a long time and being substantially unable to be executed.
The processor according to the present invention is characterized in that the memory control means and the memory are connected in a single port, and one of the fetch means is fetched one by one.

  According to such an invention, it is possible to provide a processor that employs a single port to reduce the circuit scale and realize cost reduction.

Embodiments 1 and 2 of a processor according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram for explaining a processor common to the first and second embodiments of the present invention. The processor according to the first embodiment is a processor that includes a plurality of processors A, B, C, and D, and is configured by sharing some hardware resources among the processors. In the processor according to the first embodiment, the processors A to D can execute instructions in parallel.

  The processor according to the first embodiment includes a memory 101 in which instructions are stored, and reads (fetches) instructions from the memory 101. Therefore, the processor controls the processor main body 1 including a plurality of fetch units 107a, 107b, 107c, and 107d for fetching instructions and the memory control for transferring the instructions requested by the fetch units 107a to 107d to the fetch unit that requested the instructions. Part 103.

The memory 101 according to the first embodiment has a non-bank configuration in which a storage area for storing instructions is not banked. Such a memory 101 can store many instructions linearly in a storage area, and can efficiently use the storage area.
In the first embodiment, the memory control unit 103 is connected to the memory 101 with a single port and reads instruction data one by one from the memory. In the first embodiment, the scale and cost of the circuit for connection with the memory 101 can be suppressed.

  The processors A to D included in the processor main body 1 each include a fetch unit, a decode unit that interprets an instruction fetched by the fetch unit, an ALU (Arithmetic and Logical Unit) that executes an operation related to the decoded instruction, and It has. In the first embodiment, each of the processors A to D includes any one of the fetch units 107 a to 107 d and shares the decode unit 113 and the ALU 115.

  Each of the fetch units 107a to 107d fetches an instruction to be executed from the memory 101 according to a program or the like. A fetch buffer that accumulates fetched instructions and a fetch buffer management unit that manages the accumulation state of instructions in the fetch buffer are provided. Of the fetched instructions, once they are stored in the fetch buffer, they may be cleared by the occurrence of a branch or the like, and may not actually be executed. An instruction to be executed is sometimes referred to as an actual instruction in this specification to distinguish it from an instruction that is not executed.

  Furthermore, the processors A to D include program control units 105a, 105b, 105c, and 105d corresponding to the fetch units 107a to 107d, respectively. Each of the program control units 105a to 105d includes a program counter 209, and performs a program address calculation. Further, a branch determination unit 210 is provided to decode the branch instruction, determine the branch when the branch condition status is ready, pass the branch address to the program counter, and output the branch destination address as the instruction address. Based on the accumulation state of the actual instruction in the fetch buffer managed by the fetch buffer management unit, the degree of urgency (urgency) of instruction data transfer of the corresponding fetch unit is set.

  In the first embodiment, the program control units 105a to 105d generate a signal indicating the set urgency level (emergency level signal), and output this signal to the memory control unit 103 together with a signal for requesting command data transfer. To do. Since the instruction data transfer is requested by outputting the urgent signal and the signal for requesting the instruction data transfer, the program control units 105a to 105d function as the fetch request unit of the first embodiment.

  In the above configuration, one program control unit, one fetch buffer, and one fetch buffer management unit are provided for each of the processors A to D. In the present specification, hereinafter, the program control unit is referred to as program control units 105a, 105b, 105c, and 105d, and the correspondence with the processors A to D is indicated by characters a, b, c, and d in the code. Further, the fetch buffers are denoted as fetch buffers 109a, 109b, 109c, and 109d, and the correspondence relationships with the processors A to D are similarly shown. Further, the fetch buffer management units are denoted as fetch buffer management units 111a, 111b, 111c, and 111d, and the corresponding relationships with the processors A to D are similarly shown.

On the other hand, the memory control unit 103 sets the priority order of the instruction data transfer based on the urgency level indicated by the urgency level signal, and executes the requested fetch by reading the command from the memory 101 according to the set priority level. .
Furthermore, the processor of the illustrated first embodiment includes register units 117 a to 117 d for storing the result of the operation of the ALU 115. Each of the register units 117a to 117d is provided corresponding to each of the processors A to D, and stores the calculation result of the corresponding processor.

Next, the configuration and operation of the processor body 1 and the memory control unit 103 described above will be described in more detail.
(1) Processor Main Body FIG. 2 is a diagram showing the configuration of the processor main body 1 in more detail, and in particular, the fetch unit 107a and program control unit 105a of the processor A, and the decoding unit 113 and ALU 115 shared with other processors. It shows. The plurality of processors A to D included in the processor main body 1 each have a similar configuration in which one program control unit and one fetch unit are provided, and the decoding unit 113 and the ALU 115 are shared. . For this reason, in the present specification, for the sake of simplicity, the configuration and operation of the processor A will be described below, and the description of the other processors will be partially omitted as being the same.

Hereinafter, each configuration of the fetch unit 107a, the program control unit 105a, the decoding unit 113 and the ALU 115 shared with other processors will be described, and the operation of each configuration will be described with reference to FIG.
I Fetch unit 107a
The data (instruction data) of the instruction scheduled to be executed fetched by the fetch unit 107a is accumulated in the fetch buffer 109a. The fetch buffer 109a has three buffers 200, 201, and 202, and can store a plurality of instruction data at the same time. The fetch buffer management unit 111a determines the accumulation state of instruction data to be executed in the three buffers 200, 201, and 202, and detects information including the number of instruction data accumulated in the fetch buffer 109a. Can do.

  The fetch buffer management unit 111a detects the accumulation state of the instruction data in the fetch buffer 109a, generates an urgency signal, and outputs it to the program control unit 105a. In the first embodiment, the fetch buffer management unit 111a constantly monitors the state of the fetch buffer 109a, and outputs a signal E (Empty) and a signal EL (Empty_Level) to the program control unit 105a as state signals. The signal E is a signal indicating that there is no instruction data stored in the fetch buffer 109. The signal EL is a signal indicating the number of instruction data currently stored in the fetch buffer 109a. Specific examples of the signal E and the signal EL will be described later.

  The instruction data fetched by the fetch unit 107a is first stored in the buffer 202 of the fetch buffer 109a. The fetch buffer management unit 111a sequentially sends the instruction data stored in the buffer 202 to the buffer 200, and stores the instruction data fetched later in a buffer in which a space is generated. Then, the instruction data stored in the buffer 200 is output to the decoding unit 113 at the next operation and used for execution of the operation in the ALU 115.

II decode unit 113 and ALU 115
The decoding unit 113 decodes the instruction data stored in the buffer 200. Then, the instruction data is interpreted and sent to the ALU 115 together with the interpretation result. The ALU 115 performs an operation on the instruction data received from the decoding unit 113 and stores the result in the register unit 117a.

  The register unit 117 a includes a register file 206 and a branch condition status register 205. The register file 206 is a register file in which calculation results, data loaded for calculation, and the like are stored. The branch condition status register 205 is a register for storing the state of the operation result of the operation executed by the ALU 115. The size comparison, the coincidence comparison, the sign of the addition / subtraction result, etc. are stored in the status register.

In addition, when the branch instruction is decoded, the register unit 117a outputs the branch address I and the branch address J to the program control unit 105a. Further, a branch condition status signal indicating the status of the branch condition is output from the branch condition status register 205 to the program control unit 105a.
III program control unit 105a
The program control unit 105 a includes an instruction data read control unit 207, a program counter 209, and a branch determination unit 210. The instruction data read control unit 207 generally controls fetch in the processor A. The program counter 209 is a counter indicating the progress of the program being executed by the processor A, and functions as a fetch unit together with the fetch unit 107a. The branch determination unit 210 is configured to receive the branch address I from the register unit 117 a and the branch address J and the branch condition status signal from the ALU 115, and detect that the branch instruction is decoded by the corresponding decoding unit 113.

  The instruction data read control unit 207 outputs a signal Sreq (RD_REQ) that is an instruction data transfer request signal to the memory control unit 103. The memory control unit 103 that has received the signal Sreq reads instruction data from the memory 101 in response to a request for instruction data transfer, and executes fetching. If the instruction is successfully read, the memory control unit 103 returns a signal Sready (RD_READY) in response to the signal Sreq. The program counter 209 outputs an instruction address signal indicating the address in the memory 101 of the instruction data requested by the signal Sreq.

  Further, the command data read control unit 207 of the first embodiment includes an urgency determination table 208. The instruction data read control unit 207 acquires instruction data with the highest degree of urgency when it is determined to execute a branch using a branch control signal from the branch determination unit. On the other hand, when the branch is not established, the signal E and the signal EL are compared with the urgency determination table 208 to determine the urgency of the instruction data transfer of the fetch unit 107a. Then, a signal P (PRIORITY) indicating the determined urgency level is generated. Then, the signal P is output to the memory control unit 103 together with the signal Sreq and the instruction address signal.

  FIG. 3 is a diagram showing an example of the urgency determination table 208. The urgency determination table 208 in FIG. 3 shows an example in which the buffers 200 to 202 all have a 32-bit capacity and the instruction data is fixed-length data of one instruction 16 bits. In such an example, each of the buffers 200 to 202 can store two instructions, and the fetch buffer 109a can store a maximum of six instruction data.

The urgency determination table 208 shown in FIG. 3 shows the state of the fetch buffer 109a and the urgency of the instruction data corresponding to each state. As the state of the fetch buffer 109a, the fact that the fetch unit 107a has taken a branch by a branch instruction and the number of instruction data stored in the fetch buffer 109a (the number of remaining instructions) are set.
In the first embodiment, as shown in the urgency determination table 208, the degree of urgency indicated by the urgency is set according to the number of instruction data to be executed that are stored in the fetch unit 107a. In the first embodiment, a higher urgency level is set when the number of instruction data stored in the fetch buffer 109a is smaller.

In the first embodiment, the urgency level is set based on the fact that the decoding unit 113 detects that the branch instruction has been decoded. In the first embodiment, even in the case of a branch instruction, a branch caused by an interrupt is distinguished from a branch caused by a branch instruction, and when a branch instruction caused by an interrupt is decoded, an urgency level signal having a higher urgency level is generated.
The processor A described above operates as follows. That is, the fetch buffer management unit 111a generates a signal EL indicating the number of instruction data to be executed stored in the fetch buffer 109a, and constantly outputs it to the program control unit 105a. When there is no instruction data stored in the fetch buffer 109a, a signal E is output to notify the instruction data read control unit 207 of the instruction data storage state in the fetch buffer 109a.

  On the other hand, the decoding unit 113 can interpret the instruction data and detect from the result that the branch instruction has been decoded. In this case, the decoding unit 113 outputs a branch decode signal and notifies the branch determination unit 210 that the branch instruction has been decoded. Further, the register unit 117a and the ALU 115 output the branch address I, the branch address J, and the branch condition status signal to the branch determination unit 210.

  The branch determination unit 210 receives a branch decode signal, a branch address I and a branch address J, and a branch condition status signal. Then, a branch address which is a branch destination address is calculated from the branch address I and the branch address J. Further, the branch determination unit 210 generates a branch control signal based on the branch condition status signal. The branch control signal is input to the program counter 209 and to the instruction data read control unit 207.

  The command data read control unit 207 receives the signal E and the signal EL, and compares them with the urgency determination table 208. When the signal E is input, the instruction data read control unit 207 determines that there is no instruction data stored in the fetch buffer 109a, and generates a signal P indicating the urgency level 2. In addition, when the signal EL is input, the instruction data read control unit 207 receives the signal P indicating one of the urgency levels 3 to 8 depending on the number of instruction data stored in the fetch buffer 109a indicated by the signal EL. Is generated.

  In addition, the instruction data read control unit 207 receives a branch control signal from the branch determination unit 210 and collates it with the urgency determination table 208. When the branch determination unit 210 detects that the fetch unit 107a corresponding to the own device has decoded the branch instruction, the urgency level is higher than when the remaining number of instructions in the fetch buffer 109a is 1 or more. The signal is generated.

  The reason for generating an urgency level signal having a higher urgency level than when the remaining number of instructions is 1 or more when a branch instruction is executed is that the instruction data stored in the fetch buffer 109a when a processing branch occurs This is because all are cleared. That is, when a branch instruction is decoded and this instruction is executed, the fetch buffer 109a is emptied. For this reason, in this embodiment, when instruction data is not fetched, a memory stall may occur immediately, so that the signal P with a relatively high urgency level is generated.

Furthermore, in this embodiment, the instruction data read control unit 207 determines whether the branch instruction is interrupted by the branch instruction interrupt indicated by the branch control signal, and whether the instruction branch is determined, and the emergency level 0 or the emergency level 1 is determined based on the determination result. A signal P is generated. The generated signal P is output to the memory control unit 103 together with the signal Sreq and the instruction address signal.
As described above, in the first embodiment, the operation of the processor according to the first embodiment has been described assuming that the instruction data is fixed-length data. However, the first embodiment is not limited to a configuration that handles fixed-length instruction data, and can also handle variable-length instruction data. When handling variable-length instruction data, the program control unit 105a detects the data length of the instruction data when, for example, an address signal is output or a signal Sready is input.

Then, the instruction data read control unit 207 compares the detected data length with the accumulation amount of the instruction data included in the signal EL in the fetch buffer 109a, and changes the variable length actually accumulated in the fetch buffer 109a. Get the number of instruction data.
(2) Memory Control Unit FIG. 4 is a diagram showing the configuration of the memory control unit 103 in more detail, and shows the memory control unit 103 and the memory 101. A processor interface unit 401 that exchanges data with the processors A to D of the processor body 1 is provided. A signal Sreq and a signal P are input to the processor interface unit 401 from each of the program control units 105 a to 105 d included in the processors A to D of the processor body 1. The processor interface unit 401 receives an address of instruction data requested by the signal Sreq from each of the program control units 105a to 105d as an address signal.

  The memory control unit 103 receives, via the processor interface unit 401, the address of the memory 101 to be accessed at the time of fetch and the urgency signal of instruction data transfer for each of the processors A to D by the signal Sreq, the signal P, and the instruction address. . Then, the instruction data is sent to each of the processors A to D together with the signal Sready indicating that the requested data transfer has been executed.

  The memory control unit 103 includes a request list table 404 and an address decoding unit that function as a priority setting unit that sets the priority of requested data transfer based on the urgency indicated by the signal P input by the program control unit 105a. 402 is provided. In addition, a memory access control unit 405 that reads an instruction from the memory 101 in accordance with the set priority order is provided.

  FIG. 5 is a diagram illustrating an example of the request list table 404. The illustrated request list table 404 shows a list of access requests to the memory 101 in which priorities are set according to the urgency level. The processor ID shown in the figure is an ID for identifying each of the processors A to D, and is shown as A, B, C, and D in FIG. The urgency is the urgency of data transfer to the processor represented by the signal P. The current priority is the priority between competing fetches set according to the urgency of each processor. In the request list table 404, the instruction data transfer requests are arranged in descending order of priority and assigned a small access list number. The access list number is a list pointer.

  The configuration described above operates as follows. That is, the signal Sreq is output to each of the request list table 404, the priority order control unit 403, and the address decoding unit 402. The signal Sreq includes a processor ID for specifying the output processor, and the processor ID is set in the request list table 404. In the request list table 404, it is detected that an instruction data transfer request has been made by the input of the signal Sreq, and the processor that has requested the instruction data transfer is specified.

  The processor that has output the signal Sreq outputs the signal P and the instruction address at the same time. The signal P is input to the priority control unit 403. The priority control unit 403 determines the urgency of data transfer of the signal Sreq based on the signal P. The determined urgency level is output to the request list table 404 and set in response to a request for command data transfer. On the other hand, the instruction address is input to the address decoding unit 402. The address decoding unit 402 outputs the input instruction address to the request list table 404, and the request list table 404 sets the instruction address corresponding to the instruction data transfer request.

The command data transfer request is set in the request list table 404 with an access list number assigned in order of highest urgency. The processor ID is set in the request list table 404 in response to the request.
By the operation described above, the ID for identifying the processor that has requested the instruction data transfer and the urgency level of the instruction data transfer are set in the request list table 404 in the order according to the urgency level. The priority order control unit 403 assigns priorities to command data transfer requests set in the request list table 404 according to the urgency level.

  The fetch units 107a to 107d sequentially request instruction data transfer even after the request list table 404 is set once. If the urgency level of the command data transfer request made later has a higher urgency level than the command data transfer request for which the priority is set first, the priority control unit 403 outputs priority update information to the request list table 404 Then, the priority order once set is updated. For this reason, the priority set in the request list table 404 varies depending on the urgency of the command data transfer request made thereafter.

  That is, the priority order control unit 403 sets the urgency level of the requested command data transfer in the request list table. If the command data transfer by the command data transfer request for which the urgency level is set first is executed and a signal P indicating a higher urgency level is input later, this information is updated as a priority. The information is output to the request list table 404 as information. In the request list table 404, based on the priority update information, a higher priority is set for a command data transfer request with a higher urgency than a command data transfer request with a lower urgency requested earlier.

  On the other hand, the priority of the instruction data transfer request with the lower urgency level is lowered by the instruction data transfer request with the higher urgency level made later. In such a case, the priority order control unit 403 updates the request list table 404 and newly sets a priority order in the request list table 404 for an unexecuted instruction data transfer request. The information on the newly set priority is notified from the request list table 404 to the priority control unit 403 as the current priority. The current priority is used for priority control in the subsequent priority control unit 403.

  FIG. 6 is a flowchart for explaining processing for changing the priority order setting by the memory control unit 103. Prior to starting the priority setting process, the priority control unit 403 first initializes the request list table 404 (S601). Then, the memory control unit 103 determines whether there is an instruction data transfer request based on the signal Sreq (S602). When there is an instruction data transfer request (S602: Yes), information such as an address to be accessed is further input (S603). If it is determined in step S602 that there is no instruction data transfer request (S602: No), the process waits until an instruction data transfer request occurs.

  Next, the memory control unit 103 defines the access list number k in the request list table 404 as N−1 (S604). N is the total number of instruction data transfer requests set in the request list table 404 shown in FIG. The access list number shown in FIG. For this reason, the maximum value of the access list number k is obtained by N-1.

  Next, the memory control unit 103 determines whether or not the urgency level of the command data transfer requested in step S602 is higher than the urgency level of the access list number k (S605). As a result of the comparison, if the urgency level of the command data transfer requested this time is not higher than the urgency level of the access list number k (S605: No), the priority order of the command data transfer requested this time is set in the request list table 404. The order immediately after the priority set in the access list number k is set (S609).

According to the processing of steps S605 and S609, when the urgency level of the requested command data transfer is equal to the urgency level of the access list number k, the command data requested later among the command data transfer requests having the same urgency level The transfer can be set immediately after the previously requested command data transfer.
If the memory control unit 103 determines in step S605 that the urgency level of the command data transfer requested this time is higher than the urgency level of the access list number k (S605: Yes), the priority level of the access list number k The request list table 404 is updated so as to lower (S606). Then, 1 is subtracted from the access list number k to make k (S607), and it is determined whether or not k has become 0 as a result of subtracting 1 from the access list number k (S608).

As a result of the determination in step S608, the memory control unit 103 determines again whether or not the urgency level of the command data transfer requested when the access list number k is not 0 is higher than the urgency level of the access list number k (S608). : No). If the access list number k becomes 0 (S608: Yes), it is determined whether or not there is a next instruction data transfer request.
Next, the operation of the processor of Embodiment 1 performed based on the priority set as described above will be described.

7 and 8 are timing charts for explaining the processor operation. FIG. 7 is a timing chart showing the operation when the priority order of the instruction data transfer request is set according to the urgency level. FIG. 8 is a timing chart showing the operation of the conventional multi-thread processor listed for comparison with the first embodiment.
7 and 8, for each of the processors A to D, the signal Sreq, the signal P, the signal Sready timing, and the instruction data read timing are shown, and the processor clock cycle (CLK) is shown at the top. . In FIGS. 8 to 10, A, B, C, and D denote processors that generate signals.

  The processor A_REQ is a signal Sreq generated by the processor A. The processor A_PRIORITY indicates a signal P generated by the processor A, and the processor A_READY is a signal Sready generated by the processor A. Further, the processor A_DATA indicates the timing at which the instruction data is read by the instruction data transfer request. The above notation represents a signal generated by a processor other than processor A by replacing processor A with processor B, processor C, and processor D.

  According to FIG. 7, first, processor A makes an urgent 1 instruction data transfer request to memory control unit 103 in the first cycle, and starts reading instruction data in response to the request in the second cycle of the next cycle. Is done. Then, it can be seen that the signal Sready is generated at the timing of completion of the instruction data reading, and that the instruction data transfer is executed to the processor body 1 side.

  Also, as shown in FIG. 7, in the first embodiment, the processor C issues an instruction data transfer request with an urgency level 2 in the third cycle, and the instruction data read by the instruction data transfer request of the processor C is completed. Processor A makes an urgent 0 command data transfer request. At this time, the memory control unit 103 reads the instruction data in response to the instruction data transfer request from the processor A before reading the instruction data in response to the instruction data transfer request from the processor C.

  On the other hand, in the conventional fetch operation shown in FIG. 8, the instruction data transfer requests made by the processors A to D are executed in order. Compared to such a conventional operation, in the operation of the processor of the first embodiment shown in FIG. 7, the instruction data transfer of the processor with less instruction data remaining in the fetch buffer can be preferentially executed. For this reason, even if the access speed to the conventional processor and the memory is the same, the entire processor can be operated smoothly, and problems such as memory stalls can be prevented.

  Furthermore, in the processor according to the first embodiment that can operate smoothly, the fetch units 107a to 107d can transfer the instruction data to the instruction at an appropriate timing even if the memory 101 has a non-bank configuration. For this reason, it is possible to increase the use efficiency of the memory 101 rather than assigning data linearly to the memory and dividing the data into banks. In addition, since the processor according to the first embodiment can operate smoothly, even if it is connected to the memory 101 with a single port, it is possible to sufficiently prevent problems such as memory stalls. For this reason, it is advantageous to further reduce the circuit scale required for connection between the memory and the processor and to reduce the cost.

  In the first embodiment described above, the processor of the present invention is configured as a multi-thread processor or the like that can execute instructions in parallel. However, the processor according to the first embodiment is not limited to a configuration capable of executing instructions in parallel, and may be configured as a single processor.

(Embodiment 2)
By the way, in the first embodiment, there is a possibility that an instruction data transfer request having a relatively low urgency level may not be executed for a long time when a command data transfer request having a higher urgency level is subsequently issued. That is, when the priority order of the instruction data transfer request is set only according to the urgency level as in the first embodiment, the instruction of the processor C having the urgency level 2 requested in the third cycle as shown in FIG. The data transfer is not executed until the 10th cycle due to an instruction data transfer request by the processor A and the processor B made later. According to such an operation, there is a possibility that an instruction data transfer request with a relatively low degree of urgency may be substantially not executed due to being kept waiting for a long time.

  In the second embodiment, after a certain fetch unit (first fetch unit) requests an instruction data transfer (first fetch) in order to eliminate the possibility of the first embodiment while maintaining the effect of preventing memory stalls. In addition, before the completion of the first instruction data transfer, another fetch unit (second fetch unit) requests the instruction data transfer (second fetch) from the memory 101, and the second instruction data transfer is When executed prior to one instruction data transfer, the priority control unit 403 updates the priority setting of the first instruction data transfer to a higher order.

  That is, for example, after processor A makes a urgency 3 command data transfer request to memory control unit 103 and before the request is accepted, processor C requests urgency 1 command data transfer. And In such a case, in the second embodiment, as in the first embodiment, the instruction data transfer request of the processor C having a higher degree of urgency is given priority, and the processor C transfers the instruction data before the processor A.

Then, the urgency level of the instruction data transfer request of the processor A is increased by one and set to the urgency level 2. In the second embodiment, the operation of executing the requested instruction data transfer after the previously requested instruction data transfer is also referred to as the overtaking of the instruction data transfer request.
Next, for example, it is assumed that the processor D requests a command data transfer with an urgency level of 1. At this time, the priority control unit 403 compares the urgency level 2 of the instruction data transfer request of the processor A with the urgency level 1 of the instruction data transfer request of the processor D. Then, a higher priority order than the processor A is set for the instruction data transfer request of the processor D having a higher degree of urgency. Further, the urgency level of the instruction data transfer request of the processor A is further increased by one and set to the urgency level 1.

  Next, for example, when the processor C requests an instruction data transfer with an urgency level 1, the priority control unit 403 performs an urgency level 1 for an instruction data transfer request for the processor A and an urgency level 1 for an instruction data transfer request for the processor C. And compare. At this time, the urgency level of the instruction data transfer request of the processor A is the same as the urgency level of the instruction data transfer request of the processor C. In the second embodiment, the instruction data transfer request made earlier is given priority, and the priority of the instruction data transfer request of the processor A is set higher than that of the instruction data transfer request of the processor C.

  FIG. 9 is a diagram illustrating a request list table according to the second embodiment. In the request list table shown in FIG. 9, the command data transfer request by the processor C with the urgency level 4 is set to a higher priority than the command data transfer request with the higher urgency level. Such a setting is achieved by increasing the urgency every time an instruction data transfer request with a relatively low urgency is overtaken, and gaining a higher priority than a command data transfer request made later with a higher urgency. It was made.

  FIG. 10 is a timing chart showing an operation when the urgency of the instruction data transfer request that has been overtaken is increased when the instruction data transfer request is overtaken. According to FIG. 10, as shown in FIG. 7, the processor C generates a command data transfer request with an urgency level 2 in the third cycle. Before the command data transfer by this request is executed, the processor A makes a command data transfer request with an urgent level of 0.

  In such a case, in the operation shown in FIG. 10, the memory control unit 103 causes the processor A to transfer instruction data prior to the instruction data transfer request from the processor C, as in the operation shown in FIG. However, since priority is set in consideration of overtaking of the instruction data transfer request, the urgency of the instruction data transfer request of the processor D made in the third cycle is changed from 2 to 1. Therefore, in the example of FIG. 10, the priority order of the instruction data transfer request of the processor C is the same as the instruction data transfer request of the processor B (urgent level 1) made later. If the urgency is the same, the command data transfer request made earlier is prioritized. For this reason, the memory control unit 103 executes the instruction data transfer request of the processor C in preference to the instruction data transfer request of the processor B.

As described above, the operation shown in FIG. 10 shortens the waiting time for the instruction data transfer request of the processor C than the operation shown in FIG. It is possible to prevent the execution from becoming impossible.
In the second embodiment, when overtaking of instruction data transfer occurs, instruction data transfer with relatively low urgency is achieved while increasing the urgency of the instruction data transfer request made earlier and suppressing the memory stall of the processor. It is possible to prevent the request from becoming substantially unexecutable.

  In the second embodiment described above, when an overtaking of instruction data transfer occurs, the urgency of the overwritten instruction data transfer is increased by one. However, the second embodiment is not limited to such a configuration, and the number of urgency levels may be increased depending on the specifications and operations of the processor and the processing to be executed.

It is a figure for demonstrating a processor common to Embodiment 1 and Embodiment 2 of this invention. It is the figure which showed the structure of the processor main body shown in FIG. 1 in detail. It is the figure which showed an example of the urgency determination table shown in FIG. FIG. 2 is a diagram showing the configuration of the memory control unit shown in FIG. 1 in more detail, FIG. 5 is a diagram illustrating an example of a request list table according to the first embodiment illustrated in FIG. 4. 6 is a flowchart for explaining processing for changing priority order setting according to the first embodiment; 3 is a timing chart illustrating an operation of the processor according to the first embodiment. 6 is a timing chart showing an operation of a conventional multi-thread processor listed for comparison with the first embodiment. It is a figure which shows an example of the request | requirement list table of Embodiment 2. 10 is a timing chart illustrating an operation of the processor according to the second embodiment. It is the figure which illustrated the structure where a multithread processor accesses the memory divided into banks.

Explanation of symbols

1 processor main body, 101 memory, 103 memory control unit 105a, 105b, 105c, 105d program control unit 107a, 107b, 107c, 107d fetch unit 109a, 109b, 109c, 109d fetch buffer 111a fetch buffer management unit, 113 decoding unit 117a, 117b, 117c, 117d Register unit 200, 201, 202 Buffer 205 Branch condition status register, 206 Register file 207 Instruction data read control unit, 208 Urgency determination table 209 Program counter, 210 Branch determination unit 401 Processor interface unit, 402 Address decoding unit 403 Priority control unit, 404 Request list table, 405 Memory access control unit

Claims (5)

A processor that fetches instructions from a memory in which the instructions are stored,
It includes a fetch means for fetching an instruction, instruction requested by the fetch unit, a memory control means for transferring the fetched unit that requested the instruction, and
The fetch means comprises:
Command storage means for storing transferred commands;
An urgency level setting means that indicates a degree of urgency of instruction acquisition in the fetch means based on a state of an actual instruction that is actually executed among the instructions stored in the instruction storage means;
Fetch request means for outputting the urgency level set by the urgency level setting means to the memory control means and requesting transfer of instructions, and
The memory control means includes
Fetch priority order setting means for determining the priority order of instruction transfer based on the urgency level output by the fetch request means;
Memory access control means for reading out an instruction relating to a fetch request from the memory according to the priority set by the fetch priority setting means;
A processor comprising: A processor that executes a plurality of instructions in parallel,
A plurality of fetch means for fetching an instruction, and a memory control means for transferring an instruction requested by the fetch means to the fetch means that requested the instruction,
The fetch means comprises:
Command storage means for storing transferred commands;
An urgency level setting means that indicates a degree of urgency of instruction acquisition in the fetch means based on a state of an actual instruction that is an actually executed instruction among the instructions stored in the instruction storage means;
Fetch request means for outputting the urgency level set by the urgency level setting means to the memory control means and requesting transfer of instructions, and
The memory control means includes
Fetch priority setting means for determining the priority of instruction transfer based on the urgency output by the fetch request means;
Memory access control means for reading an instruction relating to a fetch request from the memory in accordance with the priority set by the fetch priority setting means;
A processor comprising:   3. The processor according to claim 1, wherein the urgency level setting unit sets the urgency level according to a stored number of instructions stored in the command storage unit. The second fetching unit requests the second instruction after the first fetching unit requests the first instruction among the plurality of fetching units and before the transfer of the first instruction is completed. 3. The transfer apparatus according to claim 2, wherein when the transfer is completed prior to the transfer of the first instruction, the priority setting unit updates the setting of the priority of the instruction transfer of the first instruction to a higher rank. The processor described in. 5. The processor according to claim 1, wherein the memory control unit is connected to the memory in a single port and transfers instructions one by one to one of the fetch units. 6.

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