JPH07134642A - Data transfer device - Google Patents

Abstract

PURPOSE:To simultaneously execute plural decoding processings and to improve the throughput of the data output of a data transfer device by providing a memory access mediation device. CONSTITUTION:The memory access mediation device 7 reads data from a memory 3 and delivers the memory data to plural data decoders, read timings from the respective decoders are controlled by a mediation circuit 14 and the data read from the memory 3 are stored in registers 15 and 16. An STR1-115 and an STR2-119 are write signals for fetching the memory data to the registers 15 and 16 and become strobe signals for informing the data decoders of that the data are readable at the same time. The data decoders read the memory data stored in the registers 15 and 16 after it is confirmed that the strobe signals became active. By such constitution, access from the plural data decoders to the memory 3 is mediated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a data transfer device.

[0002]

2. Description of the Related Art An example of a conventional data transfer device will be described.
FIG. 3 is a block diagram of a conventional data transfer device. Reference numeral 20 is an MPU I / F for controlling input / output of data, address and control signal of the MPU (1), reference numerals 21 and 22 are a plurality of data decoders, and reference numeral 23 is a data decoder (21) for reading data from the memory (3). , 22) for passing the memory data to the memory I / F.

For example, data is compressed by entropy coding such as arithmetic code and Huffman code, and the compressed data is stored in a memory. By decoding the data stored in the memory by the data decoder (21, 22) and reading the decoded data from the MPU, the MPU seems to read the original data from the memory.
By applying a decoder that uses high-efficiency compression technology, such as an arithmetic code decoder or a Huffman code decoder, as a data decoder, it is possible to access a memory that has an apparently larger capacity than the actual memory capacity. It is visible from the MPU.

When a plurality of data encoders (21, 22) are built in the data transfer device, the MPU (1) is MPU /
For the F (20), the data transfer device is accessed through the MPU control signal (141), the address signal (142), and the data signal (143). MPU I / F is MPU
A signal for controlling the data decoder 1 (21) and the data decoder 2 (22) is generated from the control signal (141) and the address signal (142).

DEN1 (144) is the data decoder 1 (2
When the DEN1 is the enable signal of 1) and the DEN1 is activated, the data decoder performs the decoding process. RDY1 (14
5) is a data ready signal of the data decoder 1, which decodes the compressed data stored in the memory (3), and when the buffer of the data decoder 1 is completely filled with the decoded data, the MPU reads the decoded data. This is a signal notifying that it can be taken out. When RDY1 (145) becomes active, the MPU disables DEN1 (144), stops the decoding process of the data decoder 1 (21), and reads the decoded data by the DATA1 signal (147). Reference numeral 146 is various control signals for controlling the data decoder 1 (21), and AD1 (148) is an address signal for accessing the internal register of the data decoder 1. In the data decoder 2 (22), the definition of each signal is the same as that of the data decoder 1 (21).
49) is an enable signal for the data decoder 2 (22), R
DY2 (150) is a data ready signal of the data decoder 2 (22), 151 is various control signals from the MPU for the data decoder 2, DATA2 (152) is a data signal, and AD2 (153) is the data decoder 2 This is an address signal for accessing the internal register of (22).

Data decoder 1 (21) and data decoder 2
(22) are RD signals (159, 161) and memory addresses (160, 16) for the memory (3), respectively.
2) is generated, and the data stored in the memory is read from the memory data signal MD (156). Memory I / F
Then, select these signals by MUX, and select the memory (3)
RD signal (157) and memory address MD (1
58) is output. At this time, the selection of RD signals and memory addresses output from the plurality of data decoding devices is M
It is controlled by the MSEL (154) output from the PUI / F.

[0007]

However, in the above-mentioned conventional technique, when the data is read by the data decoder 1, the data decoder 1 (21) is enabled by DEN1, and the memory address is switched by MSEL to switch the data code. The memory in which the data compressed by the compression technique of the device 1 is stored is accessed. On the other hand, when data is read by the data decoder 2, the data decoder 2 (22) is enabled by DEN2, MSEL is switched to the address of the data decoder 2, and the memory is accessed. At this time, the data decoder 1 needs to be disabled, and a plurality of data decoders cannot be simultaneously enabled and operated.

When the MPU is operating the data decoder 1 (21) and it becomes necessary to read data from the data decoder 2 (22), the data decoder 1 (21)
After stopping the processing of (1) and switching the mode to the data decoder 2 (22), the processing of the data decoder 2 is started,
A procedure of reading the decoded data is required, and when the data of the data decoder 1 and the data decoder 2 are alternately read and the operating state is frequently changed, the overall processing efficiency becomes poor.

Further, the data decoding process of the arithmetic encoder or the like requires a large number of processing steps and the processing time becomes long. At this time, the MPU waits for the processing of the data decoding device until the decoded data is output.

By adding means for arbitrating access to the memory from a plurality of data decoders to the data transfer device, data compressed by different compression techniques can be performed without stopping the processing of the plurality of data encoding devices. Can be decoded at the same time. Therefore, the MPU can alternately access the data decoder and read the data, and the memory access can be efficiently performed. Further, the data decoder switching processing routine such as stopping the data decoder can be deleted.

As described above, an object of the present invention is to simplify the control from the MPU and to improve the throughput of data output of the data transfer device by simultaneously executing a plurality of decoding processes.

[0012]

A data transfer apparatus according to claim 1 of the present invention comprises a microprocessor (MPU),
MPU that controls input / output of data, address, and control signals
It is characterized by comprising an I / F, a plurality of data decoders for decoding compressed data, and a memory access arbitration device.

[0013]

The details of the present invention will be described below with reference to Examples.

In this embodiment, a device that arbitrates access to the memory is applied to a plurality of data decoders as a memory I / F. This allows the MPU to operate in the memory as compared with the conventional system. It is possible to access efficiently.

FIG. 1 is a block diagram showing the configuration of the present invention. Reference numeral 1 is a microprocessor (MPU), 2 is a data transfer device of the present invention, 3 is a general-purpose memory such as ROM, flash memory, RAM, and 4 is an MPU.
Control signal (101) of (1), address signal (10)
2), MPU for controlling input / output of data signal (103)
I / F, 5 and 6 are a plurality of data encoders, and 7
Is a memory access arbitration device that reads data from the memory (3) and transfers the memory data to the data decoders (5, 6). Although FIG. 1 shows an example of two data decoders as the data decoder, the number of data decoders is not limited. Also, as a data decoder, arithmetic code,
Data decoder for entropy code such as Huffman code,
A data decoder that performs some processing on the data, such as cutting out the data stored in the memory to a predetermined bit length, outputs the data, an image encoder that uses a high-efficiency compression technology such as JPEG, or data that transparently reads the memory data. There is a decoder. The data decoders 1 and 2 can use two data decoders having the same function or can use data decoders having different functions.

When a plurality of data encoders (5, 6) are built in the data transfer device, the MPU (1) operates as an MPU I / F.
The data transfer device is accessed through (4). MPU
The I / F (4) generates a signal for controlling the data decoder 1 (5) and the data decoder 2 (6) from the control signal (101) from the MPU, the address signal (102) and the data signal (103). .

DR1 (104) is a data read signal, and the data decoded by the data decoder 1 (5) is M
This is a signal notifying that the PU has read. RDY1
(105) is a data ready signal of the data decoder 1, which decodes the compressed data stored in the memory (3), the buffer of the data decoder 1 is completely filled with the decoded data, and the MPU reads the decoded data. It is a signal notifying that it is possible. Reference numeral 106 is various control signals for controlling the data decoder 1 (5), and AD1 (108) is an address signal for accessing the internal register of the data decoder 1. The decoded data is the data signal DATA1 (1
07), it is read by the MPU through the MPU I / F. In the present embodiment of FIG. 1, DEN is different from the conventional example of FIG.
The decoding enable signals 1 and 2 are deleted and DR1 is added. When the internal data buffer becomes full, the data decoder notifies the MPU that the data can be read by the RDY1 (105) and at the same time suspends the data decoding process. When the MPU reads the data decoded by the data decoder 1, MPUI /
F activates DR1 (104). The data decoder 1 restarts the decoding process by using DR1 as the restart signal for the decoding process. By implementing such a processing procedure, the MPU can decode consecutive compressed data only by reading the decoded data through the data register. Further, even when the transparent reading means is applied as the data decoder, it is possible to continuously read the data from the specified memory address by reading the data from the data register by having the function of automatically generating the next address. it can.

Also in the data decoder 2 (6), the definition of each control signal is the same as that in the data decoder 1 (5), and DR
2 (109) is a data read signal of the data decoder 2, R
DY2 (110) is a data ready signal of the data decoder 2 (6), 111 is various control signals from the MPU for the data decoder 2, DATA2 (112) is a data signal, and AD2 (113) is the data decoder 2 This is an address signal for accessing the internal register of (6).

In the conventional example shown in FIG. 3, the data decoder 1
(21) and the data decoder 2 (22) generate RD signals (159, 161) and memory addresses (160, 162) for the memory (3) and access the memories. At this time, MSEL specified by MPU (1)
Which of the data decoders is to be selected is selected according to, and the data stored in the memory is read from the memory data signal MD (156). In the conventional configuration, since only one of the data decoding devices is activated and operated, the process in which one data decoding device accesses the memory while the other data decoding device cannot be realized.

In the data transfer device of the present invention, by using the memory access arbitration device, it is possible to operate a plurality of data decoders simultaneously and efficiently access the memory from the MPU.

FIG. 2 is a block diagram showing the configuration of the memory access arbitration device (7). Reference numerals 11 and 12 are registers for storing the address signals from the data decoders (5, 6), and 13 is an address MAD1 (1
30), MAD2 (131), and a multiplexer (MUX) that outputs the memory address MA (123) to the memory (3), 15 and 16 are registers that store the data output from the memory, and 14 is Data request signals REQ1 and REQ2 from the data decoders 1 and 2
(114, 118) are input to output a MUX select signal (132), a memory read signal (122), and a memory data write signal (115, 119) to output data from the data decoders 1 and 2. An arbitration circuit that arbitrates the memory read requests REQ1 and REQ2 issued from each.

Memory addresses MAD1 (116) and REQ1 (11) storing compressed data from the data decoder 1
4) is input to the memory access arbitration device (7) and stored in the register (11). If the read process of the data decoder 2 is not performed, the read process of inputting the memory address MAD1 of the data decoder 1 and the read signal (122) to the memory and outputting the memory data MA can be immediately performed. it can. However, when data read processing is being performed from the memory by the read request REQ2 of the data decoder 2, the data decoder 1
Cannot access memory. The arbitration circuit (14) controls the read timing from each decoder. The data read from the memory (3) is stored in the registers (15, 16). STR1 (115),
STR2 (119) is a write signal for loading memory data into the register and at the same time is a strobe signal for notifying the data decoders 1 and 2 that the data can be read. After confirming that the strobe signal has become active, the data decoder reads the memory data stored in the registers (15, 16). With the above configuration, access from a plurality of data decoders to the memory is arbitrated.

In this embodiment, two methods will be described as the configuration of the arbitration circuit 14.

FIG. 4 is a diagram for explaining the memory read arbitration by the competition selection method. In the competition selection method, until the memory read requests REQ1 and REQ2 issued first become valid and the memory data is stored in the registers (15, 16), the later issued request is not accepted, and the R issued first.
After the EQ read processing is completed, the request REQ issued later
Is performed.

The definition of each signal shown in FIG. 4 is in accordance with FIG. Further, EVENT indicates the number of events obtained by counting the number of clocks.

When a read request REQ1 is issued from the data decoder 1 in EVENT1, and if REQ2 is not requested here, the arbitration circuit selects MAD1 as MA, activates the RD signal to read the memory data, and EVENT5 Then, STR1 is activated and the register (15) is updated.

REQ from the data decoder 2 at EVENT 4
Although 2 is requested, the read processing waits until the processing of REQ1 ends. Then from EVENT6 to R
The processing of EQ2 starts, the memory is accessed with MAD2 set as MA, and STR2 is activated at EVENT9 to update the register (16).

EVENT11 requests REQ2, and EVENT12 requests REQ1. The method of FIG. 4 gives priority to the processing of the data decoder which made the request first, and therefore executes the processing of writing the data of the A2-2 address in the register 16 through EVENT 11-15.
Subsequently, the processing of REQ1 issued by EVENT12 is performed, and the processing of reading the data of the A1-2 address is performed.

As described above, the competition selection method is a method in which the previously requested data is always output first. However, when read requests are issued at the same time, one of them is given priority.

FIG. 5 is a diagram for explaining memory read arbitration by the priority selection method. The priority selection method gives priority to the data decoders 1 and 2, and when a read request is made from a data decoder having a high priority during a read request process from a data decoder having a low priority, the priority of the data decoder This is a method in which the reading process of the low data decoder is stopped and the reading process of the high priority data decoder is executed first.

The definition of each signal shown in FIG. 5 is in accordance with FIG. EVENT indicates the number of events obtained by counting the number of clocks. The priority order of REQ1 is high (REQ1> REQ2).

The processing up to EVENT 9 is the same as the method shown in FIG. However, RE in EVENT4
In response to the request of Q2, the processing of REQ2 is waiting until the memory read processing of REQ1 of EVENT5 is completed, but this is in the processing waiting state because the priority of REQ1 is high.

EVENT11 requests REQ2, and EVENT12 requests REQ1. Since the method of FIG. 5 gives priority to the processing of the data decoder having the higher priority, the processing of REQ2 issued in EVENT11 is stopped, and the processing of REQ1 in which the data of the A1-2 address is written to the register 15 through EVENT12-16. To execute. REQ issued in EVENT11
The process of 1 is re-executed, and the process of reading the data of the A2-2 address is performed.

As described above, the priority selection method is a method in which the data of the data decoder having a high priority is output first, so that when the data read request of the data decoder having a high priority is frequently made. , A data decoder with a lower priority may not be able to read data, and the throughput of memory data transfer may deteriorate as a whole, but the data decoder with a lower priority may be used by methods such as defining the shortest access time. Control can be transferred to the reading process.

[0035]

As described above, according to the present invention, a plurality of data decoders are operated at the same time, and while one data decoder is performing the data decoding process, the MPU can read data from the other data decoder. Therefore, the throughput of memory access is improved.

The data compressed by using the high-efficiency compression technique such as the arithmetic code and the Huffman code is stored in the memory, and the decoded data is read by the MPU, so that the MPU seems to read the original data. . At this time, by using the data read signal as the restart signal of the decoding operation of the next data, the MPU only sets a predetermined parameter at the time of decoding start, and the compressed data stored in consecutive addresses is read every time the register is read. Can be read. Further, when a highly efficient compression technique is used as the data decoder, it seems that the MPU is accessing a memory having an apparently larger capacity than the actual capacity of the memory. Further, when data having different properties such as voice and image are stored in the same memory, the compression rate can be expected to be improved by adaptively switching data decoders using different compression techniques.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data transfer device according to the configuration of the present invention.

FIG. 2 is a block diagram showing the configuration of a memory access arbitration device.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a diagram illustrating a competition selection method in an arbitration circuit.

FIG. 5 is a diagram illustrating a priority selection method in an arbitration circuit.

[Explanation of symbols]

 1 ... Microprocessor (MPU) 2 ... Data transfer device 3 ... Memory 4 ... MPU I / F 5 ... Data decoder 1 6 ... Data decoder 2 7 ... Memory access Arbitration device 11 ... Address register 12 ... Address register 13 ... Multiplexer (MUX) 14 ... Arbitration circuit 15 ... Data register 16 ... Data register 20 ... MPUI / F 21 ... -Data decoder 1 22 ... Data decoder 2 23 ... Memory I / F 24 ... Multiplexer 25 ... Multiplexer 101 ... Control signal 102 ... Address signal 103 ... Data signal 104 ... Data read signal 105 ... Data ready signal 106 ... Control signal 107 ... Data signal 108 ... Address signal 09 ... Data read signal 110 ... Data ready signal 111 ... Control signal 112 ... Data signal 113 ... Address signal 114 ... Data read request signal 115 ... Data strobe signal 116 ... Memory address signal 117 ... Memory data signal 118 ... Data read request signal 119 ... Data strobe signal 120 ... Memory address signal 121 ... Memory data signal 122 ... Read signal 123 ... Memory address signal 124 ... Memory data signal 130 ... Memory address signal 131 ... Memory address signal 132 ... Select signal 141 ... Control signal 142 ... Address signal 143 ... Data signal 144. ..Decoding enable signal 145 ... Data ready -Signal 146 ... Control signal 147 ... Data signal 148 ... Address signal 149 ... Decoding enable signal 150 ... Data ready signal 151 ... Control signal 152 ... Data signal 153 ... Address signal 154 ... Mode select signal 156 ... Memory data signal 157 ... Read signal 158 ... Memory address signal 159 ... Memory read signal 160 ... Memory address signal 161 ... Memory read signal 162 ... Memory address signal

Claims (1)

[Claims] 1. A data comprising an MPUI / F for controlling input / output of data, an address and a control signal, a plurality of data decoders for decoding compressed data, and a memory access arbitration device. Transfer device.