JPH05314049A - Channel device - Google Patents

Abstract

PURPOSE:To reduce the frequency of contention for data transfer requests and to improve the efficiency of data transfer by eliminating the prefetch of unwanted data. CONSTITUTION:This channel device is provided with data prefetch control tables 151-15n storing information in areas corresponding to respective devices so as to show whether transfer accompanies data or not corresponding to the kinds of devices, read circuits 161-16n for reading the area corresponding to the device to be started from the data prefetch control table, decode circuits 171-17n for decoding a command to be immediately operated among the commands of channel command words, selector circuits 181-18n to select which bit of the data prefetch control table is read by the docode circuit, and channel control circuits 141-14n to report the read instruction of data to a data transfer circuit 12 corresponding to the information read out of the data prefetch control table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device, and more particularly to prefetch control of data in a channel device of a large computer.

[0002]

2. Description of the Related Art In a conventional channel device of this type, in the case of a write system input / output operation, data is pre-fetched and stored in a channel data buffer in order to improve the efficiency of data transfer. This is because the same command code may cause different operations depending on the type of input / output device, the operation depends on the input / output device, and the channel device cannot determine whether or not the command involves data transfer.

[0003]

In the above-described conventional channel device, especially when the number of channels is large, the contention frequency of data transfer requests due to preemption of unnecessary data increases, which causes a decrease in data transfer efficiency. There is a drawback.

[0004]

The device of the present invention is a channel device for decoding a channel command word, activating a designated input / output device, and controlling a data transfer operation.
A data prefetch control table in which information indicating whether or not the transfer is accompanied by data depending on the type of device is stored in an area corresponding to each device; and a circuit for reading the area corresponding to the device to be activated from the data prefetch control table. , A decoding circuit for decoding a command that performs an immediate operation among commands of a channel command word, a selector circuit that selects which bit of the data prefetch control table is read by the decoding circuit, and a data prefetch control table It is characterized in that it has a channel control circuit which makes a data read instruction a data transfer circuit according to the read information.

[0005]

The present invention will be described below with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, the present embodiment includes an input / output processing device 1, an arithmetic processing device 2,
It comprises a system controller 3 and a main memory 4. Further, the input / output processing device 1 includes a micro program control device 11, a data transfer circuit 12, and n channel devices 1.
3 _{1 to} 13 _n, and each of the channel devices 13 _{1 to} 13 _n has the same configuration.

The micro program control circuit 11 controls the channel data transfer in accordance with the channel state management, the channel activation control and the description of the channel program. The data transfer circuit 12 controls the channels 13 _{1 to} 13 _n according to the instruction of the microprogram control circuit 11 to transfer data between an input / output device (not shown) and the main storage device 4.

The channels 13 _{1 to} 13 _n have channel control circuits 14 _{1 to} 14 _n , data prefetch control tables 15 ₁ to 15 _n , and areas corresponding to devices to be activated from the data prefetch control tables 15 ₁ to 15 _n. The read circuits 16 _{1 to} 16 _{n for} reading, the decoding circuits 17 _{1 to} 17 _n for decoding the commands that perform the immediate operation among the commands of the channel command words, and the data prefetch control tables 15 ₁ to 15 by the decoding circuits 17 _{1 to} 17 _n. Selector circuits 18 ₁ to 18 _n for selecting which bit of _n to read and data buffer 1
9 _{1 to} 19 _n .

The channel control circuits 14 _{1 to} 14 _n include a micro program control circuit 11 and a data transfer circuit 12.
Management of the protocol with the input / output device,
Controls the performance of data transfers. Data prefetch table 1
As shown in FIG. 2, each of 5 ₁ to 15 _n has an area for each IOC, each area has a bit for each command, and each bit has information as to whether or not to prefetch data.

Next, the operation of this embodiment having the above configuration will be described.

The micro program control circuit 11 activated by the input / output start instruction executed by the arithmetic processing unit 2 via the system control unit 3 reads out the channel program stored in the main storage unit 4, and executes the channel command. The word is sent via the data transfer circuit 12 to the channel devices 13 _{1 to} 13 _n corresponding to the input / output device to be activated.

Channel device 13 ₁ for instructing input / output operation
.About.13 _n decode the channel command word by the channel control circuits 14 _{1 to} 14 _n and activate the designated input / output device. Further, the read circuits 16 _{1 to} 16 _n read the data prefetch control tables 15 ₁ to 15 _n at the IOC address given at the time of activation from the arithmetic processing unit 2, and the commands of the above channel command words are decoded to the decoders 17 ₁ to.
Decoding is performed by 17 _n , and the decoded value is used as a select signal of the selector circuits 18 ₁ to 18 _n to select 1 bit of the information read from the data prefetch control tables 15 ₁ to 15 _n .

The channel control circuits 14 _{1 to} 14 _{n make} a data prefetch request to the data transfer circuit 12 if one bit of the information read from the data prefetch control tables 15 ₁ to 15 _n is "0". The requested data transfer circuit 12 prefetches the data from the main memory 4 according to the byte count value and stores it in the data buffers 19 _{1 to} 19 _n of the channel devices 13 _{1 to} 13 _n . If it is “1”, it means that data prefetching is not necessary, and therefore data prefetching is not performed.

[0014]

As described above, according to the present invention, it is possible to prevent unnecessary data prefetching by having information on whether or not to prefetch data depending on the type of device. And the efficiency of data transfer is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data prefetch control table 15 shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input / output processing device 2 Arithmetic processing device 3 System control device 4 Main memory device 11 Micro program control circuit 12 Data transfer circuit 13 _{1 to} 13 _n Channel device 14 _{1 to} 14 _n Channel control circuit 15 ₁ to 15 _n Data prefetch table 16 _{1 to} 16 _n read circuit 17 _{1 to} 17 _n decoder circuit 18 ₁ to 18 _n selector circuit 19 _{1 to} 19 _n data buffer

Claims (1)

[Claims] 1. A channel device which decodes a channel command word, activates a designated input / output device, and controls a data transfer operation. In a channel device, the data is transferred to an area corresponding to each device depending on the type of the device. A data prefetch control table that stores information about whether or not information is stored, a circuit that reads an area corresponding to the device to be activated from the data prefetch control table, and a command for decoding the immediate operation command of the channel command word commands. A decoder circuit, a selector circuit for selecting which bit of the data prefetch control table is read by the decode circuit, and a data transfer circuit that gives a data read instruction by the information read from the data prefetch control table. Characterized by having a channel control circuit Yaneru apparatus.