JPH0250238A - Data processor with cache memory - Google Patents

Data processor with cache memory

Info

Publication number
JPH0250238A
JPH0250238A JP63198869A JP19886988A JPH0250238A JP H0250238 A JPH0250238 A JP H0250238A JP 63198869 A JP63198869 A JP 63198869A JP 19886988 A JP19886988 A JP 19886988A JP H0250238 A JPH0250238 A JP H0250238A
Authority
JP
Japan
Prior art keywords
cache
cache memory
memory
mode
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63198869A
Other languages
Japanese (ja)
Other versions
JP2811678B2 (en
Inventor
Fumio Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63198869A priority Critical patent/JP2811678B2/en
Publication of JPH0250238A publication Critical patent/JPH0250238A/en
Application granted granted Critical
Publication of JP2811678B2 publication Critical patent/JP2811678B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To improve a cache bit rate by providing a microprocessor on a control means and setting a mode to make access to a cache memory.
CONSTITUTION: In the control means to control a cache memory 210, a host processor 100, a microprocessor 220 to execute data transfer control between a memory unit 300 and the cache memory 210, a directory memory 230, an instruction decoding circuit 260, a device cache using mode accumulating circuit 270 and an instruction cache using mode accumulating circuit 280 are provided. Thus, the cache bit rate is improved and the processing ability of a system can be improved.
COPYRIGHT: (C)1990,JPO&Japio
JP63198869A 1988-08-11 1988-08-11 Data processing device with cache memory Expired - Lifetime JP2811678B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63198869A JP2811678B2 (en) 1988-08-11 1988-08-11 Data processing device with cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63198869A JP2811678B2 (en) 1988-08-11 1988-08-11 Data processing device with cache memory

Publications (2)

Publication Number Publication Date
JPH0250238A true JPH0250238A (en) 1990-02-20
JP2811678B2 JP2811678B2 (en) 1998-10-15

Family

ID=16398278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63198869A Expired - Lifetime JP2811678B2 (en) 1988-08-11 1988-08-11 Data processing device with cache memory

Country Status (1)

Country Link
JP (1) JP2811678B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612685B2 (en) 2007-10-11 2013-12-17 Nec Corporation Processor, information processing device and cache control method of processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157055A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash control unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157055A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash control unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612685B2 (en) 2007-10-11 2013-12-17 Nec Corporation Processor, information processing device and cache control method of processor

Also Published As

Publication number Publication date
JP2811678B2 (en) 1998-10-15

Similar Documents

Publication Publication Date Title
JPH01263760A (en) Data transfer control method and its circuit for coprocessor
JPH04256143A (en) Peripheral sub-system and control method
JPS5326539A (en) Data exchenge system
JPH02284229A (en) State storage device for microprocessor
JPH0250238A (en) Data processor with cache memory
JPH02287665A (en) Interface module
JPS6285372A (en) Comparing and swapping system in multi-processor system
JPS6132144A (en) Exclusive data processing system by microprogram control
JPS5563423A (en) Data transfer system
JPH04275693A (en) Data processing system
JPS63142416A (en) Input/output control system
JPS5487140A (en) Data transfer control system
JPS626355A (en) Computer
JPH03282667A (en) Computer device
JPS62263550A (en) Cache memory invalidating system
JPH0233636A (en) Picture processor
JPS63153653A (en) Buffer memory control system
JPS6180437A (en) Data processing system
JPS6249744A (en) Teletex equipment
JPS63141150A (en) Memory interlock control system
JPH0253152A (en) Cache memory controller
JPS5891570A (en) Information processing system
JPS61292746A (en) Memory controller
JPH03240131A (en) Information processor
JPS59123054A (en) Initial detecting system

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070807

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080807

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080807

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090807

Year of fee payment: 11

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090807

Year of fee payment: 11