JPH0250238A - Data processor with cache memory - Google Patents

Abstract

PURPOSE:To improve a cache bit rate by providing a microprocessor on a control means and setting a mode to make access to a cache memory. CONSTITUTION:In the control means to control a cache memory 210, a host processor 100, a microprocessor 220 to execute data transfer control between a memory unit 300 and the cache memory 210, a directory memory 230, an instruction decoding circuit 260, a device cache using mode accumulating circuit 270 and an instruction cache using mode accumulating circuit 280 are provided. Thus, the cache bit rate is improved and the processing ability of a system can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device with a cache memory,
In particular, the present invention is applied to a data processing apparatus with a cache memory that can improve the cache hit rate by setting a mode for accessing the cache memory.

[Prior Art] A conventional data processing device with a cache memory cannot accept only the cache usage mode (sequential mode, etc.) of a device under the data processing device subsystem as data transferred from a host processor in response to a cache embedding instruction. I was taking it. Then, read/write for each device according to its cache usage mode.
It was supposed to handle write instructions.

[Problems to be solved] The conventional data processing device with cache memory described above has the following problems:
The host processor can only specify the cache use mode of the device, which poses a problem in that the means for improving the cache hit rate are limited.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data processing device with a cache memory that can improve the cash hit rate.

[Means for Solving Problems] In order to achieve the above object, a data processing device with a cache memory of the present invention includes data transfer means for transferring data between an external host processor and a memory unit, and a data processing device provided by the host processor. In the data processing device with a cache memory, the data processing device includes a cache memory for storing files stored in the cache memory, and a control means for controlling the data transfer means and the cache memory. A microprocessor that controls the leap data transfer, a directory memory that manages file information on the cache memory under the control of this microprocessor, and a cache embedding command or data read/write sent from the host processor. an instruction decoding circuit that decodes a write instruction; and a device cache usage mode storage circuit that stores a cache usage mode for each device transferred from the host processor in conjunction with the cache embedding instruction according to a command from the instruction decoding circuit. , an instruction cache use mode storage circuit that stores a cache use mode for each data read/write instruction transferred from the host processor in conjunction with the data read/write instruction according to a command from the instruction decoding circuit. It is.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a data processing device with a cache memory according to an embodiment of the present invention, and FIG. 2 is a processing flowchart showing the operation of the data processing device with a cache memory of FIG.

It is.

In the figure, 100 is a host processor, 200 is a data processing device with a cache memory, and 300 is a memory unit that stores a plurality of files. In the data processing device 200 with cache memory, 210 is a cache memory that stores files given from the host processor, and 220 is a cache memory that stores files given by the host processor 1.
00 is a microprocessor that controls data transfer between the memory unit 300 and the cache memory 210; 230 is a directory memory that manages file information on the cache memory under the control of the microprocessor 220; and 240 is a directory memory that manages file information on the cache memory. It is a data transfer means.

Furthermore, a hint/cache 250 checks the cache hit/cache miss status of the input/output request to/from the memory unit 300 sent from the host processor 100 under the control of the microprocessor 220 .
A miss checking means 260 is an instruction decoding means for decoding the cache embedding instruction or data read/write instruction sent from the host processor 100 prior to the input/output request. Device cache usage mode storage means 280 stores the cache usage mode for each device transferred from the host processor in conjunction with the cache installation instruction; 280 is the instruction decoding means 260;
An instruction cache use mode storage means stores a cache use mode for each data read/write command transferred from the host processor in accordance with the data read/write command.

That is, the features of the present invention include an instruction decoding means 260 for decoding a cache installation instruction or a data read/write instruction sent from a host processor in FIG. Accordingly, device cache usage mode storage means 270 stores the cache usage mode for each device transferred from the host processor.
and cache use mode storage means 280 for each data read/write command transferred from the host processor in conjunction with the data read/write command according to the designation from the command decoder 260.

Next, the operation of the data processing apparatus with cache memory having the above configuration will be explained according to the processing flowchart shown in FIG.

First, the microprocessor 220 is the host processor 1
When a command is received from 00, it is checked whether the command is a read/write command (400), and read/i
! If it is not an F write instruction, the instruction processing (48
0) and ends the instruction execution (900).

On the other hand, if it is a read/write instruction, it is checked whether it is a cache use request (410).

If it is a cache use request, or it is not a cache use request, but the device cache use mode received from the host processor with a cache embedding instruction is a cache use request (420).
If it is, the directory is scanned (,500) and the requested file is found in the hit block (,500).
510). If it is not a hit block, use the free block if there is a free block, or use LRU (LEAST REC) if there is no free block.
ENTLY USE) block to MRU (MO3T
RECENTLY USE) (600).

Furthermore, instructions from the host processor are read instructions (
700), and if it is a read instruction, the data read from the memory unit is transferred to the MRLI block of the cache memory and at the same time to the host processor (800), and the execution of the instruction is ended (
900). On the other hand, if it is a write command, the data is transferred from the host processor to the memory unit (820) and the execution of the command ends.

Furthermore, in the directory scan (500), if the requested file is a hit block (510), the hit block is made an MRU (610). Then, it is further checked whether the instruction from the host processor is a read instruction (710), and if it is a read instruction, data is transferred from the MRU block of the cache memory to the host processor (810), and execution of the instruction is ended (900). )do. However, if it is a write instruction, data is transferred from the host processor to the cache memory and memory unit (820), and execution of the instruction ends (900).

If the request from the host processor is not a cache use request (420) and the device cache use mode received from the host processor with a cache embedding instruction is not a cache use request, a check is made to see if it is a read instruction (740). If it is a read instruction, the data is transferred from the memory unit to the host processor (840) and execution of the instruction is terminated (840).
900) L/, in the case of a write instruction, data is transferred from the host processor to the memory unit (850) and execution of the instruction is ended (900).

In this way, the present embodiment includes a cache memory that is located between a host processor and a memory unit that stores a plurality of files and that stores files given from the host processor, and a cache memory that stores files given from the host processor, and a A microprocessor that controls data transfer to and from the cache memory, a directory memory that manages file information on the cache memory under the control of this microprocessor, and cache embedding instructions sent from the host processor. or an instruction decoding means for decoding a data read/write instruction, and a device cache storing the cache use mode for each device transferred from the host processor in accordance with the instructions from the instruction decoding means and the cache embedding instruction. instruction cache use mode storage for storing a cache use mode for each data read/write instruction transferred from the host processor in conjunction with the data read/write instruction according to instructions from the use mode storage means and the instruction decoding means; It consists of means.

[Effects of the Invention] As described above, the present invention has the effect of providing a data processing device with a cache memory that can improve the cash hit rate and, in turn, improve the processing performance of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device with a cache memory according to an embodiment of the present invention, and FIG. 2 is a processing flow chart showing the operation of the data processing device with a cache memory of FIG. 100: Host processor 200: Data processing device with cache memory 210: Cache memory 220: Microprocessor 230: Directory memory 240: Data transfer means 250: Hit/miss inspection means 260: Instruction decoding means 270: Device cache usage mode storage means 280
: Instruction cache use mode storage means 300 : Memory unit

Claims (1)

[Claims] A data transfer means for transferring data between an external host processor and a memory unit, a cache memory for storing a file given from the host processor, and a control means for controlling the data transfer means and the cache memory. In the data processing device with a cache memory, the control means includes a microprocessor that controls data transfer between the host processor, the unit, and the cache memory, and a microprocessor that controls data transfer between the host processor, the unit, and the cache memory, and a microprocessor that controls data transfer between the host processor, the unit, and the cache memory, and a microprocessor that controls data transfer between the host processor, the unit, and the cache memory, and a microprocessor that controls data transfer between the host processor, the unit, and the cache memory; A directory memory that manages file information, an instruction decoding circuit that decodes cache embedding instructions or data read/write instructions sent from the host processor, and a device that is transferred from the host processor in conjunction with the cache embedding instructions. a device cache usage mode storage circuit that stores cache usage modes for each device according to instructions from the instruction decoding circuit;
and an instruction cache use mode storage circuit that stores a cache use mode for each data read/write instruction transferred from the host processor in conjunction with the data read/write instruction according to a command from the instruction decoding circuit. Data processing device with cache memory.