JPH0520188A - Cache controller - Google Patents

Abstract

PURPOSE:To improve the prereading effect, to shorten the replacement time, and to prevent the read of the invalid data by increasing the replacement value between the programs and the instructions having the space locality and reducing the replacement value between the programs and the data having the reduced space locality. CONSTITUTION:When a main storage 2 of a CPU 1 is read, a cache control part 3 decides whether the data are already stored in a cache memory 4 or not by the information on an address line 6. If not, a replacement data value deciding part 12 decides the replacement data value based on the information on a control information line 8. A bus control part 13 controls a system bus control part 5 and then takes the data out of the storage 2 to write them into the memory 4. Then a valid flag of a cache control table 14 is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control device, and more particularly to a replacement control system at the time of a mishit.

[0002]

2. Description of the Related Art A conventional cashier control device has a replacement method at the time of a cache miss hit whether a single block is replaced or a next block on an address of a block having a cache access is a prefetch target. It was fixed regardless of the type of reading.

Further, in order to change the block size depending on the type of memory read, a plurality of cache control devices have been prepared.

[0004]

In this conventional cache control device, since the replacement amount has nothing to do with the reading of the address, the instruction, or the data, the replacement is always fixed, and if the replacement data amount is small, the prefetch effect is obtained. However, if the amount of replacement data is large, the next memory request of the processing device is made to wait for replacement processing, and the prefetch data becomes invalid.

In addition, preparing a plurality of cache control devices as a memory read type has a drawback that the amount of metal is large. Further, since the data replacement unit is a block unit, there is a drawback that the replacement unit becomes too large.

[0006]

SUMMARY OF THE INVENTION A cache control device of the present invention is a cache control device for controlling a cache memory which is a buffer record between a processing device and a main storage device, and when a cache mishit occurs, address information is generated. And means for determining the replacement memory amount based on the information of instruction read or data read, and the main memory memory read request is made a number of times corresponding to the replacement memory amount, and the read data is fetched to the corresponding block and fetched on the cache management table. And means for validating the cache memory valid / invalid flag corresponding to the data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. When a command or data read occurs in the main memory 2, the processing unit (CPU) 1 outputs a command / data type and memory read request information on the address line 6 and the control information line 8. The cache control unit 3 determines from the address line 6 whether or not it already exists in the cache memory 4.

If not in the cache memory 4, the replacement data amount determination unit 12 determines the instruction / data type from the information on the control information line 8 and determines the replacement data amount together with the information on the address line 6. The determination method is, for example, that the address space is 4
Divide into two, and as the replacement amount goes up,
Change to 2, 4, 8 times. In the case of instructions and data, the instructions are exchanged twice as much as the data.

For example, in the case of instruction reading, if 16 bytes are replaced, memory read requests are issued to the bus control unit 13 for the number of replacement cycles determined by the following equation.

Number of replacement cycles = 16 bytes / read data width upon replacement The bus control unit 13 makes a memory read request to the system bus control unit 5 via the bus control information line 9. The system bus control unit 5 takes out data from the main storage device 2 via the system bus 10 and transfers it to the CPU 1 and the cache memory 4 via the data line 7. The cache memory control line 11 controls writing to the cache memory 4.

Next, when the data read from the CPU 1 is data, the replacement data amount determination unit 12 determines, for example, 4-byte replacement. The bus control unit 13 makes a memory read request for the number of replacement cycles determined by the variation.

Number of replacement cycles = 4 bytes / read data bus width at the time of replacement When data is fetched, the cache management table 14
Set the valid flag for. When there is a cache hit, data is passed from the cache memory 4 to the CPU 1.

[0014]

As described above, according to the present invention, a prefetch effect can be expected by determining the replacement data amount at the time of a cache miss by the command / data type requested by the processing device and the address space information. In the case of, that is, when there is spatial locality, the amount of replacement data is increased, and when reading data, that is, when there is little spatial locality, the amount of replacement data is decreased, and the memory read time by pre-reading and waiting by replacement Has the effect of reducing time and invalid lookahead.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Processor (CPU) 2 Main Storage Device 3 Cache Control Unit 4 Cache Memory 5 System Bus Control Unit 12 Replacement Data Amount Determination Unit 13 Bus Control Unit 14 Cache Management Table

Claims (1)

Claim: What is claimed is: 1. A cache control device for controlling a cache memory, which is a buffer recording between a processing device and a main memory device, in case of a cache mishit, read address information and instruction or data read. Means for determining the amount of replacement memory based on the information, and a read request is made to the main memory device for a number of times corresponding to the amount of replacement memory, and read data is fetched into the corresponding block. A cache control device comprising means for validating a valid / invalid flag.