JPH04326125A - Information processor - Google Patents

Abstract

PURPOSE:To speed up control over the processor by a microprogram. CONSTITUTION:This processor is provided with a central control storage 1 which controls the whole processor and a local control storage 9 which controls parts 6.1-6.n of the processor respectively. Actuation information (address) is supplied to the central control storage 1 from outside or the local control storage 9 and actuation information is supplied to the local control storage 9 from outside or the central control storage 1. A process which needs to be performed fast can be controlled by actuating the local control storage 9, so the process can be performed fast.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to an information processing device that operates using a microprogram.

0002

2. Description of the Related Art Conventionally, in an information processing apparatus controlled by a microprogram, one control memory is provided for the processing apparatus, and the apparatus is controlled from the output of the control memory. Furthermore, in a device having many control points, the output of the control memory is decoded and control is performed based on the decoded output.

FIG. 5 is a block diagram showing such a conventional microprogram control system. 50 is a control memory that stores microprograms. 51 is a register that holds the address of the control memory 50; 56 is control memory 5
This is a selector that supplies an address to 0. 52 is a register that receives the output of the control memory 50; Decoders 53 to 55 decode the output of the control storage register 52 to control the corresponding data processing sections.

First, at the start of an instruction, a control memory activation address is externally applied, and the address supply selector selects the control storage activation address and sets it in the control address register 51. Next, information in the control memory 50 with the contents of the control address register 51 as an address is set in the control memory register 52, and a part of the information in the control memory 50 is set in the control memory address register 51 as the next control memory address. .

On the other hand, control decoders 53 to 55 decode part of the information set in the control storage register 52, and their outputs are used to control each part of the information processing device.

In recent years, as LSIs have become more highly integrated and gate delays have become faster, attempts have been made to increase processing speed by shortening machine cycles. However, L.S.
At present, the increase in the degree of integration of high-speed memories lags behind the increase in the degree of integration of high-speed memories. Therefore, in devices, the proportion of memory for control storage is becoming larger than that of circuits that perform actual calculations.

[0007] Taking these points into consideration, if we consider an information processing apparatus that operates by a microprogram as an extension of the conventional system, it will be as shown in FIG. 6. The difference in FIG. 6 compared to FIG. 5 is that from the control storage register 52 to the control decoders 53 to 55
When transferring control information to the control storage registers 60-6
2, each relay is relayed once.

This is because, as mentioned above, the ratio occupied by the control memory 50 has increased, and the distance between the controlled side and the control memory has become longer compared to the conventional machine cycle ratio. . In such a configuration, it takes one machine cycle for the control information from the control memory to reach the processing unit, which slows down the processing when executing a branch instruction in a microprogram.

[0009]

OBJECTS OF THE INVENTION It is an object of the present invention to provide an information processing device controlled by a microprogram that improves processing speed.

0010

SUMMARY OF THE INVENTION According to the present invention, there is provided an information processing device that operates according to a microprogram, which includes a central control storage means for controlling the entire device, and at least one local control device for controlling a part of the device. storage means, and means for controlling activation of the central control storage means in accordance with control information output from an external or local control storage means;
There is obtained an information processing apparatus characterized in that the information processing apparatus includes means for controlling activation of the local control storage means in accordance with activation information output from an external or central control storage control means.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Reference numeral 1 denotes a central control memory, which is a large-capacity memory in which a microprogram capable of controlling all processing units is stored.

Reference numeral 2 is a register in which the output of the central control memory 1 is set. 3 is a read address register of the central control memory 2; 4 is an address supply selector which selects an address of the central control memory and supplies it to the central control memory.

6.1 to 6.n are n Ls to be controlled
This is an SI device, and all LSIs 6.1 to 6.n have the same configuration, and for the sake of simplicity, only the configuration of LSI 6.1 is shown.

9 is a local control memory, and LSI 6.
This is a memory in which a microprogram that controls the 1 is stored. 8 is a read address register of the local control memory 9, and 7 is a selector that selects the read address and supplies it to the local control memory 9.

11 is a local control register;
is a selector that selects one of the information in the local control memory 9 and the output information of the central control register 2. 12 is a control decoder, which decodes the output of the local control register 11 and controls the processing section 14; Reference numeral 13 denotes a relay register, which relays activation information when the central control memory 1 is activated using a local address.

Reference numerals 29 and 30 are registers for setting an external activation address, and register 30 is an external activation address register for LSI6.1, and LSI6.2 to 6.n.
Although external activation address registers are provided corresponding to each of these registers, they are not shown.

FIG. 2 shows the configuration of the control circuit of the address supply selector 4 which supplies addresses to the central control memory 1. In this example, a case is shown in which three LSIs 6.1 to 6.3 are used. The address supply selector 4 receives the relay registers 13.1 to 13.3, the central control register, or the activation address from the outside, and selects which input is selected based on the information of the flags 33 to 35 and the relay registers 13.1 to 13.3. Decide what to do.

That is, when the flag 33 is set to 1, the external start address 29 is selected, and when the start instruction is issued from the relay register 13.1, the relay register 1
3. Start address from 1 is selected and relay register 1
If a startup instruction is issued from 3.2, relay register 13.
The starting address from 2 is selected, and the relay register 13.
When a start instruction is issued from 3, the start address from relay register 13.3 is selected, and when flag 35 is lit, data obtained by adding 1 to the contents of central control address 3 is selected, and flag 34 is set. When set to 1, the input from central control register 2 is selected.

Furthermore, the flag 33 becomes 1 for only one machine cycle due to an external activation signal. Flag 35 is set to 1 in flag 33 or relay register 13
- If a startup instruction is output from 1 to 13/3, it becomes 1 for only one machine cycle. The flag 34 is set to 1 when the flag 35 is set to 1, and holds 1 until a local control storage activation signal, which is information from the central control register 2, is output and reset by that signal.

FIG. 3 shows the configuration of the control circuit of the address supply selector 7 and control information selector 10 of the local control storage. Address supply selector 7 has local control memory 9
, the activation address from the central control 2 or from outside is input, and which input is selected is determined by the information in the flags 36 to 38 or the central control register 2.

That is, when the flag 36 is set to 1, the external start address 30 is selected, and when a start instruction is output on the central control register 2, the start address from the central control register 2 is selected. , if the flag 37 is set to 1, the input from the local control storage 9 is selected. Further, the flag 36 becomes 1 for only one machine cycle due to an external activation signal.

The flag 37 is set to 1 when the flag 36 is set to 1 or an activation instruction is output from the central control register 2, and the central control memory activation signal in the information of the relay register 13 is output. and holds 1 until set by that signal.

The control information selector 10 receives input from the local control memory 9 or information from the central control register 2, and determines which input to select based on the flag 38. That is, if the flag 38 is 1, the input from the local control memory 9 is selected, and if the flag 38 is 0, the input from the central control register 2 is selected. flag 38
If either flag 36 or 37 is set to 1, it will be set to 1 only for the next one machine cycle.

FIG. 4 shows a field diagram of central control storage and local control storage.

Next, the operation will be explained. When an instruction is started, an activation signal and an activation address are externally set in either the central control memory 1 or the local control memories 9.1 to 9.n depending on the type of instruction.

Assume that the central control memory 1 is activated from the outside. First, the flag 33 is set to 1 by the external activation signal, and the external activation address is set in the external activation address register 29. In the next machine cycle, the address supply selector 4 selects the external activation address by the flag 33 and sets it in the central control address register 3, and the flag 35 is set to 1 by the flag 33 for one machine cycle.

In the next machine cycle, the output of the control memory 1 with the information in the central control address register 3 as an address is set in the central control register 2, and the flag 33 sets the output of the control memory 1 to the address of the next control memory 1, that is, the central address register. Add 1 data to central control address register 3,
Each flag 35 is set to 1.

In the next machine cycle, since the flag 38 is not set to 1, the control information selector 10 selects the output of the central control register 2 and sets it in the local control register 11, and also selects the output of the central control register 2 and sets it in the local control register 11. Since the address of 1 is not set to 1 in the flag 37, the information in the central control register 2 is set. Thereafter, the central control memory 1 continues to operate using its own information, that is, the information in the central control register 2, as the next address until its own processing is completed. Information set in the local control register 11 controls the corresponding processing section 14 through the control decoder 12.

Next, the operation of the local control memory 9 will be explained. When entrusting processing to the local control memory, the central control memory 1 sets a local control memory activation instruction and a local control memory activation address on the central control register 2.

In the next machine cycle, the address supply selector 7 selects the information in the central control register 2 and sets it in the local control address register 8, and flags 37 and 38 are lit and flag 34 is reset.

In the next machine cycle, the control information selector 10 sets the output of the local control memory 9 whose address is the information in the local control address register 8 to the flag 38.
is selected and set in the local control register 11. At the same time, the address supply selector 7 sets the output of the local control memory 9 in the local control address register 8 because the flag 37 is set to 1.

Thereafter, the local control memory 9 continues to operate using its own output as an address until its own processing is completed. The information set in the local control register 11 is decoded by the control decoder 12 and controls the processing section 14. External activation of local control storage and activation of central control storage from local control storage are performed in a similar manner.

It should be noted here that when controlling each processing unit from the central control memory, compared to receiving and controlling from the central control register 2 and local control register 11,
When controlling each processing unit using local control storage, the control can be performed using information received once by the local control register 11.

In other words, processes that can be processed by each processing section and require high speed can be left to the local control memory, while processes that can be slow can be left to the central control memory.

[0036]

As described above, according to the present invention, a central control memory that controls the entire device and a local control memory that controls a part of the device are provided. By controlling the entire device by transferring startup information from the system, processing that requires high speed can be performed in the local control memory, and other processes can be performed in the central control memory, thereby creating a device with high processing performance. This has the effect of making it possible to

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing details of a peripheral control section of the selector 4. FIG.

FIG. 3 is a diagram showing details of a peripheral control section of the selector 7. FIG.

FIG. 4 (A) is a diagram showing an example of data in the central control memory 1;
(B) is a diagram showing an example of data in the local control storage 9.

FIG. 5 is a block diagram showing an example of a conventional microprogram control method.

FIG. 6 is a block diagram showing another example of the conventional microprogram control method.

[Explanation of symbols]

1 Central control memory 2 Central control register 3 Central control address register 4 Central control address selector 6.1~6.n LSI 7 Local control address selector 8 Local control address register 9. Local control memory 11 Local control register 12 Control decoder 13 Relay register 14 Processing section

Claims (1)

[Claims] 1. An information processing device operated by a microprogram, comprising a central control storage means for controlling the entire device, at least one local control storage means for controlling a part of the device, and an external or means for starting and controlling the central control storage means according to control information output from the local control storage means; and means for starting and controlling the local control storage means according to activation information output from an external or central control storage control means. Information processing equipment including.