JPH05181739A - Memory access controller - Google Patents

Abstract

PURPOSE:To unnecesitate a software program for switching a buffer area and to improve the whole processing efficiency by allowing a buffer switching circuit to switch a buffer area in a memory by a hardware means to use a switched buffer area. CONSTITUTION:The buffer switching circuit is provided with an address controller 33 for changing the preceding state in accordance with a previously determined sequence, shifting the preceding state to a current state and outputting a flag signal corresponding to the current state and an address modifier 32 for modifying an address signal to be applied to a memory correspondingly to the flag signal. In the case of accessing the memory from one CPU, the address controller 33 changes the preceding state to the current state and forms a flag signal corresponding to the current state and the address modifier 32 modifies an address sent from the CPU in accordance with the flag signal and applies the modified address to the memory to control memory access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device used when a memory having divided areas is accessed by a plurality of CPUs. More specifically, the amount of software programs involved in the memory access is reduced. To improve.

[0002]

2. Description of the Related Art In a system having a plurality of CPUs, one of the conventional methods for these CPUs to access the same memory such as RAM without waiting time is shown in FIG.
6 and 7, the conventional technique will be described with reference to these drawings. FIG. 5 is a diagram showing a case where the first CPU 1 and the second CPU 2 access one memory M. This memory M has a first buffer area #
0, second buffer area # 1, third buffer area # 2
The first CPU 1 and the second CPU 2 access the areas # 0, # 1, # 2 so as not to overlap each other. Therefore, a control register CR as shown in FIG. 6 is separately provided, and the first CPU 1 and the second CPU 2 are provided.
This register CR can be accessed from both of the two, and the buffer area of the memory M is controlled to be switched. Specifically, in the control register CR, status S0 represents the status of buffer area # 0, status S1 represents the status of buffer area # 1, status S2 represents the status of buffer area # 2, and CPU1, CPU2 Is control register CR
To switch the buffer area of the memory M. For example, when the CPU 1 accesses the memory M, the status Si (i = 0, 1, 2) of the control register CR
And if Si ≠ 0, buffer #i is used.
Then, the status Si + 1 is checked for each access, and if the status Si + 1 ≠ 0, the status Si is written to “0” and the buffer # i + 1 is used. On the other hand, when the CPU 2 accesses the memory M, the status Sj (j = 0, 1, 2) is referred to, and when Sj = 0, the buffer #j is used. Then, the status Sj + 1 is checked for each access, and when the status Sj + 1 = 0, the status Sj is written to “1” and the buffer #
Use i + 1. However, the status is 2 or more "1"
In case of, writing is not performed. Further, FIG. 7 is a state transition diagram when the CPU 2 accesses the memory M. In this way, the two CPUs 1 and 2 can access the memory M without waiting time.

[0003]

As described above, the first CPU 1 and the second CPU 2 have memory
I am accessing, but to realize the above function,
Usually, a software program is used. However, when such a software program is used, there is a problem that the program amount of the CPU becomes large and the overall processing efficiency becomes poor.

The present invention solves such a problem, and an object of the present invention is to enable switching of memory areas to be controlled by hardware and to reduce the amount of programming.

[0005]

According to the present invention, which has solved the above-mentioned problems, a memory access for controlling the memory access of two CPUs so that the respective areas of a memory divided into a plurality of areas do not overlap. In the control device, when one of the CPUs starts to access, the address controller that changes the previous state and shifts to the current state according to a predetermined sequence and outputs the flag signal corresponding to the current state; And an address modify for modifying an address signal to be supplied to the memory.

[0006]

According to the memory access control device of the present invention, when one CPU accesses the memory, the address controller changes the previous state and shifts to the present state, and at the same time generates a flag signal corresponding to the present state. , The address modify is C according to this flag.
The address sent by the PU is modified and given to the memory to control memory access.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a memory access control device embodying the present invention will be described with reference to the drawings. FIG. 1 is an overall schematic diagram showing a memory access control device of the present invention.
In this figure, the first CPU 1, the second CPU 2, and the memory M have the same configuration as the conventional one shown in FIG. 5, and the feature of the present invention is that the buffer switching circuit 3 is provided. Specifically, the CPU 1 and the CPU 2 have a bus right request signal BUSREQ * (low active) and a bus acknowledge signal BUSACK *.
Connected to the buffer switching circuit 3 from the CPUs 1 and 2 to the address bus AB, the data bus DB, the write enable signal WE * (row active), and the output enable signal OE * (row active). Active), the CPU 2 gives a bus acknowledge signal BUSACK *. Further, the memory M has a write enable signal WE * and a chip select signal CS * from the CPUs 1 and 2.
(Row active) is connected, and the address signal MA modified by the buffer switching circuit 3 and the memory output enable signal RAMOE * (row active) are applied via the modify address bus MAB. A detailed configuration of the buffer switching circuit 3 is shown in FIG. When the CPU 1 or CPU 2 issues an access request, the access request (A13 ...
15) is given to the decoder 31, and the signal Y4 * (row active) representing the memory access becomes active,
This signal Y4 * is given to the address modify 32. As a result, the address modify 32 sends the carry signal CA * (row active) to the address controller 33. The address controller 33 receives the product of the carry signal CA * and the write enable signal WE * as the clock CLK and at the same time carries the carry signal CA *.
The product of * and the output enable signal OE * is the enable signal OE *.
Given as. The address controller 33 operates according to the clock CLK, and the input state ID
It functions as a sequencer that sends output states OD0-2 to 0-2. At this time, the flags FLGH and FLGL are sent to the address modify 32 at the transition from the input state ID0 to 2 to the output state OD0 to 2. The address modify 32 modifies the signals A8 to 12 on the address bus AB according to the signal states of the flags FLGH and FLGL, and stores the modified address MA (MA8 to 12) in the memory M.
To address A8-12. Specifically, FIG.
As shown in, the flags [FLGH, FLGL] are modified addresses MA12, 11, buffer areas # 0 of the memory M when the flags are [0, 1], and buffers of the memory M when the flags are [1, 0]. When the area # 1 and the flag [1,1] are set, the buffer area # 2 of the memory M is modified. Next, the state transition from the input state ID0-2 to the output states OD0-2 and the output states of the flags FLGH and FLGL in the address controller 33 are shown in FIG. That is, given input state IDs 0 to 2 [x, x,
X] (x is 0, 1) for flags [FLGH, FLGL]
(FLGH and FLGL are 0 and 1) and output state OD0
It is a state of shifting to 2, and [×, ×, ×] corresponds to each status in the conventional control register CR. In this figure, the solid line represents the operation of the first CPU 1 and the dotted line represents the operation of the second CPU 2. However, when the CPU 1 accesses, the address modify 32 modifies the addresses A8 to 12, and when the CPU 2 accesses, the address modify 32 makes the addresses A8 to 12 through. still,
This sequence is represented by CPUs 1 and C shown in FIGS.
This corresponds to the switching operation of the buffer areas # 0, 1, 2 for each access of the PU2. Now, the operation of the device of the present invention configured as described above will be described. (a) When the first CPU 1 accesses the memory M The CPU 1 issues a bus right request BUSREQ * to the CPU 2 and receives the bus acknowledge signal BUSACK * "L" to start the access. Then, the address modify 32 receives the bus acknowledge signal BUSACK * "L" and sends a carry signal CA * to the address controller 33. The address controller 33 uses the current state
Input OD0 ~ 2 as input state ID0 ~ 2, and proceed the sequence of Fig. 4 by clock CLK = CA * ・ WE *.
Transition to a new state and output the corresponding flags FLGH and FLGL. Address Modify 32 uses this flag FL
Upon receiving GH and FLGL, the modified address MA is output, and one of the buffer areas # 0, 1 and 2 in the memory M is designated by this modified address MA. In this way, the first CPU 1 can access while designating the buffer areas # 0, 1, 2 of the memory M. (b) When the second CPU 2 accesses the memory M The CPU 2 starts the access as the bus acknowledge signal BUSACK * "H". Then, the CPU 2 reads the output states OD0 to OD2 of the address controller 33 in the buffer switching circuit 3. At this time, the memory enable signal RAMOE * is controlled to "H" so that the data from the memory M and the output states OD0 to 2 do not conflict with each other on the data bus DB. Subsequently, the CPU 2 rewrites the state so as to shift to the state shown by the dotted line in FIG.
At this time, the state transition condition of the CPU 2 is as shown by the dotted line in FIG.
Realize at the table. When the CPU 2 makes an access, the bus acknowledge signal BUSACK * is "H", the addresses A8 to 12 are through in the address modify 32, and the address modify on the address bus AB is not performed. That is, the CPU 2 has already incorporated the sequence as shown in FIG. 5, and the CPU 2 switches and uses the areas # 0, 1, 2 of the memory M without address modification. In this way, the first CPU 1 and the second CPU 1
CPUs 2 of the memory M are buffer areas # 0, # of the memory M to each other.
1 and # 2 are switched to access.

[0008]

As described above, according to the memory access control device of the present invention, when a memory divided into several areas is accessed from a plurality of CPUs, the buffer switching circuit allows the memory to be stored in hardware. Since the buffer area is switched and used, a software program for switching the buffer area is unnecessary, and the overall processing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is an overall schematic diagram of a memory access control device of the present invention.

FIG. 2 is a configuration block diagram of a buffer switching circuit in the device of the present invention.

FIG. 3 is a diagram showing a concept of memory access of a first CPU in the device of the present invention.

FIG. 4 is a state transition diagram of the address controller in the buffer switching circuit in the device of the present invention.

FIG. 5 is a diagram showing a case where a plurality of CPUs access an area-divided memory.

FIG. 6 is a diagram showing a control register to be referred to when a plurality of CPUs access an area-divided memory.

FIG. 7 is a diagram showing a state transition of a control register when a second CPU among a plurality of CPUs accesses a memory.

[Explanation of symbols]

 1 First CPU 2 Second CPU 3 Buffer Switching Circuit 31 Decoder 32 Address Modify 33 Address Controller M Memory AB Address Bus DB Data Bus MAB Modify Address Bus

Claims (1)

[Claims] 1. A memory access control device for controlling memory access of two CPUs so as not to overlap respective areas of a memory divided into a plurality of areas,
When one of the CPUs starts access, an address controller that changes the previous state according to a predetermined sequence and shifts to the current state and outputs a flag signal corresponding to the current state, and the memory corresponding to the flag signal. And an address modify for modifying an address signal given to the memory access control device.