JPS58115677A - Dma data transfer system for transfer in the same memory - Google Patents

Abstract

PURPOSE:To realize DMA data transfer in the same memory by carrying out data transfer through an intermediate buffer. CONSTITUTION:For DMA data transfer between two areas in a memory 1, a source address is set in a DMA address counterIand a destination address is set in a DMA address counter II firstly; and data length is set in byte count registersIand II. The DMA channelIis actuated firstly to perform the DMA data transfer from the memory 1 to the intermediate buffer 9, where data is stored temporarily. Then, the DMA channel II is actuated to perform the DMA data transfer from the intermediate buffer 9 to the memory 1. Said operation is repeated to realize the DMA transfer from the memory to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a DMA data transfer method in a computer system in which DMA data transfer within the same memory is performed twice via an intermediate buffer.

(2) Technical background DMA (Direct Memory Acc)
ess) is a method that uses a dedicated DMA device to transfer a large amount of data between a memory and an I10 device at high speed, which is almost impossible by program transfer. Due to this limitation, conventional DMA devices were designed only for DMA data transfer between a memory and an I10 board, and could not be used for data transfer within the same memory.

However, in recent years, the use of ultra-LSI memories has progressed, and many computer systems are now equipped with large-capacity internal memories. Therefore, data movement within the same memory [
The number of changes has also increased, and the amount of time that the CPU is occupied with it has become non-negligible.

(3) Purpose of the Invention The purpose of the present invention is to realize DMA data transfer within the same memory, which was previously impossible, by relatively simple means.

(4) Structure of the Invention According to the present invention, in order to realize DMA data transfer between different areas in a memory, a buffer is provided in the middle, and this buffer is used as a relay point for DMA data transfer.

FIG. 1 is an explanatory diagram showing the concept of the present invention.

When transferring data from area A on the memory map to area B, the data is transferred from the source address to the destination address one address at a time, but once the memory DMA one address worth of data from the source address of area A to the intermediate buffer
Transfer I7, then DMA transfer the data from the intermediate buffer to the destination address in memory area B again, and so on, data transfer for one address is performed by two-step DMA transfer.
This is executed as a process, and this process is repeated as many times as necessary.

Therefore, the present invention provides a computer system with a configuration for that purpose, which includes a memory, a DMA control circuit having a first and a DMA channel, and an intermediate buffer. DMA data transfer between the two areas is performed using the upper F first DMA channel to transfer DMA data from the memory to the intermediate buffer, and the above F first DMA channel to transfer the DMA data from the intermediate buffer to the memory.
This book is characterized in that it is executed in combination with the operation of A data transfer.

(5) Embodiment of the Invention 'F42 Diagram* is a block diagram showing the schematic configuration of the YJ game according to the embodiment of the invention. In the figure, 1 is a memory, 2 is a 9-element circuit of channel (1) of a DMA device, and 3-digit DM
A address counter (1), 4 is byte count
Similarly, register (I), 5 is the circuit element of channel 2 of the DMA device, 6 is the DMA address counter (u), 7 is the byte count register (II), 8 is the multiplexer MPX, 9 is the intermediate buffer, 10 is the Shows data bus.

The DMA device uses two channels as shown. One is used for DMA data transfer from memory 1 to offer 1 buffer 9, and the other one is used for DMA data transfer from intermediate buffer 9 to memory 1. Multiplexer 8 is used to switch between the memory source address and the tastenation O address.

When performing DMA data transfer between two areas in memo IJl, first input the source address into the DMA address counter (1) and write the source address into the DMA address e counter (Il).
Set the destination address in l, and
．． Then, set the data length in the byte count registers (1) and (IN).

First, the DMA channel (1) is activated, DMA data is transferred from the memory 1 to the intermediate buffer 9, and the data is temporarily stored in the intermediate buffer 9. Then the DMA channel (If)
f starts up and performs DMA data transfer from the intermediate buffer 9 to the memory 1. This repetition completes the Dt4A transfer of data from memory to memory.

FIG. 3 is a more detailed configuration diagram of an embodiment of the present invention. For convenience of explanation,! The 10 control circuit portion is omitted. In the figure, 11 is a memory, 12 is a CPU,
13 is the DMA circuit, 14 is the address e of channel (1)
15 is the channel (II) address counter, 16 is the channel (I) no-kite count register, and 17 is the channel (II) no-kite count register.
18 is a register, 19 is an intermediate buffer, 19 is a control unit, 20 is a register selector for switching the DMA channel,
21 address buses, 22 data nodes, and 23 control buses.

Address counter 14.15, byte count register 16.17, and intermediate buffer 18 are turtles that perform the same functions as described in FIG.

The control unit 19 includes a CPU, memory, I10 channel device (
(omitted for convenience of explanation), communicates with the internal circuit of the DMA, requests the CPU to open the bus, reads/writes to the memory)
(R/W) control, Il omitted in this example
It receives the transfer request from o, grants the transfer request, or controls the operations of internal registers, counters, buffers, etc.

The register selector 20 switches the DMA channel between (1) and (II) in response to the switching of the DM transfer direction between the memory and the intermediate node 7.The register selector also switches the DMA channel between (1) and (II). , before the DMA operation, arbitrarily select the address counter, byte e count own register, and other various registers (not shown), set the memory address, number of transferred bytes, and other control information for each, and set the control information as necessary. It is also used to read the contents of these registers.

In operation, the CPU inputs from the data bus into the address counter (1) (ID) a source address and a destination address, respectively, which are the starting addresses of the two areas to be transferred in memory. and byte count register <1), (1
), set the number of words of the same transfer data.

Next, the control unit 19 adds register selector D.
Start MA channel (1) and restart CPUt? Enable DMA. This is Matsu, Address Counter (1)
The source address of nl is applied to the memory via the address bus.The control unit 19 also sends a read signal (R/
W) is provided to the memory ttC via the control bus.

Data is therefore read from the source address of the memory onto the data bus. At this time, the control unit 19 activates the intermediate buffer 18, and the data is stored on this intermediate buffer.

When data transfer for one address from the main buffer to the intermediate buffer is completed, the contents of the address counter (1) will be +1.
．． on the other hand, the byte count.

0ζ is subtracted by 1 from the contents of the register (I).The control unit 19 then instructs the register selector to add D.
Activate the MA channel (It).

DMA? Janel (When starting up, the destination of 1 address counter (II) is displayed in the main Jf page.
An address is given, and a write signal (R/W) is given under control 1119. At the same time, the intermediate buffer 18
The data previously written therein is read out by the control unit 19 and written via the data bus to the digitization address of the memory indicated by the address counter (IOK). When writing is completed, the address counter (n) is incremented by 1 and the byte count register (If) is incremented by 1.

The above operation is performed by the Byteken count register (I), (
The contents of II) are repeated until both become zero, and when they become zero, the DMA data transfer operation is terminated.

Although the intermediate buffer 18 is shown in the block of the DMA device 13 in FIG. 3, it may be provided independently outside. In this case, conventional DMA circuits can be used with little modification. this is,
The intermediate buffer 18 may be coupled to the data q bus, and a signal indicating the in-memory DMA data transfer mode may be created 17 to control the coupling. Also, lead/
As the write signal, a read/write signal (R/W) output from the control section 19 to the memory 11 may be taken out from the control bus, inverted, and used.

(6) Effects of the Invention According to the method of the present invention, DMA data transfer within the same memory, which was previously impossible, can be easily achieved with the addition of a small amount of hardware, and the computer system processing This can have a significant effect on improving efficiency.

[Brief explanation of the drawing]

The IDI diagram is a conceptual explanatory diagram of the present invention, FIG. 2 is a schematic configuration diagram of an embodiment of the present invention, and FIG. 3 is a detailed diagram of the configuration of an embodiment of the present invention. In the figure, 1 is the memory and 2 is the DMA channel of the DMA device! element, 3 is DMA address e counter L 4 is byte count register 1, 5 is DMA channel element, 6 is DMA address reference counter ', 7 is byte count - register z18 is multiplexer, 9 is intermediate buffer, 1oFi The data bus is shown. Patent applicant Fujitsu Limited

Claims (1)

[Claims] 1! t) In the 4m system, memo! 7. ! :, #!
The device includes a DMA control circuit having I and II-th DMA channels, and an intermediate buffer, and transfers data between two different areas in the memory by using the II-th DMA channel to transfer DMA data from the memory to the intermediate buffer. DMA data transfer within the same memory is performed by a combination of an operation of transferring data and an operation of transferring DMA data from the intermediate buffer to the memory using the above-mentioned first DMA channel.
MA data transfer method.