JPS6145343A - Swapping control system - Google Patents

Abstract

PURPOSE:To improve the swapping control efficiency by securing the actuation of a high-speed/medium capacity memory (MSU) even in a data transfer mode. CONSTITUTION:An MSU 2 which performs a swapping action with a superhigh- speed/small capacity memory BS1 contains write data registers 32I-32M for temporary storage of plural data, read data registers 24I-24M for temporary storage of plural data, memories 22I-22M and a control circuit 21. The circuit 21 confirms that memories 22I-22M perform no writing nor reading action in a data transfer mode after reading actions out of the memories 22I-22M or before writing action to these memories. Then the circuit 21 performs reading actions through memories 22I-22M in the next swapping action.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Industrial application field The present invention is a storage device swap control method that transfers write data and read data in a time-sharing manner (2) Prior art] When data processing is performed by a computer, etc. In order to perform ultra-high-speed processing, it is desirable that the storage device be an ultra-high-speed semiconductor memory that can read and write at ultra-high speed.

However, ultrahigh-speed semiconductor memories are generally expensive in terms of storage capacity, and are not suitable for large-capacity storage devices. On the other hand, high-speed semiconductor memory is suitable for medium-capacity storage. Therefore, as shown in FIG. 3, an ultra-high-speed small-capacity storage device 1 (hereinafter abbreviated as buffer storage-BS), typified by the ultra-high-speed semiconductor memory, etc., and a high-speed medium-capacity storage device 1, typified by the aforementioned In combination with a capacity storage device 2 (hereinafter referred to as main storage unit = MSU), only the data necessary for each data processing is stored in the MSU.
After transferring the data to the BS and performing ultra-high-speed processing, the data is
A method is often used in which data is transferred from the BS to the MSU, and the next data is transferred from the MSU to the BS.

In that case, in order to make maximum use of the memory areas of the BS and MSU, data that has been processed in the BS is transferred to the MSU.
Control is performed such that the data in the BS and the MSU are replaced by returning data from the MSU. Such control is called swap control, and how to perform swap control efficiently is an important issue in order to perform data processing at high speed.

The conventional swap control method is outlined below. First, the BS and MSU are connected by a data bus (Figure 3)
. That is, data transfer from BS to MSU and
Data transfer from the BS to the BS can be performed in units of N bytes. And MSU is for reading (MUS-4BS)
It has a data register with a capacity of MXN bytes and a data register with the same capacity for writing (BS-MSU), and the swap operation between BS and MSU is performed in units of MXN bytes via the above two data registers. N to split
Reading and writing are performed by repeating data transfer in units of bytes M times.

Figure 4 shows the concept of its operation. When the CPU (central processing unit) issues a swap control command, first, a command to read the first MXN bytes of data is issued to the MSU. As a result, the MSU first reads MXN bytes of data from the memory into the read register from time tl to t2.

Then, the MXN byte data read into the read register from time t2 to ts is transferred to the BS.

The BS takes in MXN bytes of data transferred from the MSU at high speed from t4 to tl. This completes the first read operation Ro and data transfer. Subsequently, a data write command is issued to the MSU, and the BS first retrieves MXN bytes of data at high speed from te to tl and transfers it to the MSU. In the MSU, the transferred MXN bytes of data are taken into the write register at the time from ts to tl. After all MXN bytes of data have been imported, continue (from ts to tlO
The MXN bytes of data taken into the write register at the time are written to the memory. This completes the write operation Wo corresponding to the first read operation Ro.

1 by the above read operation Ro and write operation Wo.
The second swap operation ends. The subsequent second swap operation is also performed in the same manner as the first swap operation.

(3) Problems to be Solved by the Invention The above is the operational concept of the conventional swap control system. In the case of the above swap control method, for example, from t2 to
Although the time is for data transfer and the memory of the MSU is not operating, the CPU recognizes that the MSU is operating due to the busy signal from the MSU.
The MSU cannot be made to perform the next swap operation. That is, the CPU cannot perform the next swap operation on the MSU until time t9 when the first swap operation ends. The memory operating time of the MSU from te to tl and from tl to tlO is long because the operating speed of the MSU is slower than that of the BS, and during this time the BS does not perform any operation.

This poses a problem in that the entire swapping operation time becomes longer.

In order to eliminate the above-mentioned problems, the present invention provides a storage device that can perform swap control efficiently by allowing MSU memory operations to be performed even during data transfer time. purpose.

(4) Means for solving the problem The above purpose is to provide a write data register that temporarily stores multiple data and a read data register that temporarily stores multiple data in a storage device that performs swap operations with an upper storage device. It has a register and a control device, and the data write operation is performed by storing a plurality of write data transferred from the upper storage device to the storage device in the write data register, and then writing the number of pieces of data in the storage device. The data read operation is performed by reading the data from the memory, thereby reading and storing a plurality of digital data in the read register, and then transferring the data to the upper storage device, and after the read operation from the memory or During a data transfer time before a write operation to the memory, the control device recognizes that the memory is not performing a write or read operation, and performs a read operation from the memory in the next swap operation. The objective is to provide a storage device that

(5) Examples of the invention Examples of the present invention will be described in detail below.

FIG. 1 is an overall configuration diagram of a BS and MSU according to the present invention. First, the BSI is the control circuit 11. Memory 12. Write register 13. The write register 13 consists of a control write 11 and a control line 1.
11, and is also connected to a data bus 4 and a memory 12. The read register 14 is connected to the control circuit 11 by a control line 113, and is also connected to the data bus 3 and the memory 12. Further, the memory 12 is connected to the control circuit 11 by a control line 112. Next, MSU2 is the control circuit 2
1. Memory 221.222. ..., 22M', write register 231.232. ..., 23M'
, and read registers 241.242. ...
, 24M', write registers 231.232
．． ....

23M' is the control circuit 21 and the control line 2111.2 respectively.
112, . ..., 22
read registers 241 .
242. . . , 24M' are the control circuit 21 and the control lines 2131, 2132 . ..., 213M
”, and also connected to data bus 4 and memory 221 .
222. ..., 22M', respectively.

Also, memory 221.222. ..., 22M' is the control circuit 21 and the control line 2121.2122°..., 2
Connected by 12+'l'. Reference numeral 5 denotes a control device that performs a swath knob operation between the BSI and the MSU 2.

The operation of the storage device configured as above will be explained using the explanatory diagram of FIG. 2. First, in FIG. 1, data buses 3 and 4 connecting the BSI and MSU 2 are parallel buses of, for example, N bytes. The write register 13 and read register 14 of the BSI are N-byte buffer registers. Also, the write registers 231, 232 . ..., each of the 23M' devices has a parallel buffer of the same size as data bus 3.
(N bytes in this case), which is about 64 bytes, whereas conventionally it was about 8 bytes. Read register 241.242. ..., 24M' are also the same.

The following description will be made with reference to FIG. 1 and FIG. 2 in sequence. First, when the CPU (not shown in FIG. 1) issues a swap control command, the control device 5 first issues a swap control command to the control circuit 21 of the MSU2.
A data read command for the first MXN bytes is issued,
As a result, control lines 2121, 2122 . ...,
212M' (these also include the address lines) to the memory 221.222. ....

A data read command is issued at 22M. As a result, first, from time t+' to t2', read registers 241, 242 . ..., M×NXN to 24M'
Byte data is stored in memory 221.222. ....

22M'. Then, from the following t2゛t
Control line at time 3' 2131.2132. ...
.

213M” through read register 241.242
．． ..., 24M' are sequentially issued with transfer commands, and M
The data of the XN hide is transferred N bytes at a time to the BS1 via the data bus 4. In the BSI, first, the control circuit 11 receives a transfer start signal from the control device 5. Then, the N bytes of data transferred from MSU2 from Lm'' to L and H are written into write register 1.
3, and each time it is input to the memory 12 at high speed, a total of MXN bytes are input. Note that this operation is performed by the control circuit 11 through the control line 111 and the control line 112 (
' (including address lines). Next, BS1 conversely sends a transfer start signal to MSU2.
After outputting to SU2 via control line 5, from ta' to tt'
At the time of , data of a total of MXN bytes is read from the memory 12 in increments of N bytes and is outputted to the data bus 3 via the register 1.4% and transferred to the MSU 2. This operation is controlled by signals output from the control circuit 11 to control lines 112 (including address lines) and control lines 113. ,M
In SU2, after the control circuit 21 receives a transfer start signal from the control device 5, control lines 2111, 2112, .
..., write register 23 via 211M'
1.232. ..., giving commands to 23M' in sequence,
Data transferred from BSI from tI+' to t9'
Write registers 231, 232, . . . , 2 at times of
Import N bytes into 3M'. After reading all the data, continue (from t9' to tlO', the write register 231
．． 232. ..., the contents of 23M' are stored in the memory 221
．． 222. . . , 22M". This operation is carried out from the control circuit 21 to the control line 2111. .

2112, . . . , 211M' and control lines 2121, 2122°, . . . , 212M' (including address lines). Above is the data transfer of MXN bytes from MSU2 to BSI.
The operation of transferring MXN bytes of data from BS1 to MSU2 is the first swap operation, but t2'
The time indicated by the broken line from t9' to t9' is the data transfer time, and the time from memory 221.222. ..., 22
M' is not performing memory operations. In such a case, the control circuit 21 does not output a busy signal (a signal indicating that the memory is in operation) to the control device 5. Therefore, unless a busy signal is outputted via the control device 6, the CPU can perform the data read operation R1 for the second swap operation. That is, time t
Before the data write operation Wo for the first swamp operation is performed at time t++' between 2' and t9'', a second swap operation command is issued to the control device 6. As a result, from t2' to t9' A second data read operation R+ is performed in the same manner as the first time from time t++' to t12' within the data transfer time of 221, 222, .
..., 22M" read register 241.24
2. ..., 24M'. At this time,
If the read start time t12' must not come before the end time to' of the first data transfer from the MSU2 to the BSI.

This is due to the following reasons.

What is the time required for read operation (Ro, R+)?

This is the time for transmitting signals (RAS, CAS, address signals, etc.) for specifying addresses from the control circuit 21 to the memories 221 to 22M'. Therefore, memory 221
It is at point t12 that data is read from registers 241 to 24M' from 22M' to 24M'.

Therefore, control is performed so that t12 does not come before t8. The same can be said for writing Wo, W'+.

The second MXN byte data read as described above is transferred to the BSI via the data bus 4 from t12' to t13'. As a result, IJSI is 1
Time t when the first write data has been transferred to MSU2
Immediately after 7'', a transfer start signal is obtained from MSU1 via control line 5, and from time t+4' to tri', MSU
The second MXN bytes of data from 2 can be taken into the memory 12. And in BSI.

The second write data of MXN bytes is transferred to the MSU2 via the data bus 3 from t16' to t17'. At this time, MSU2 does not output a busy signal, so as mentioned above, ts' to too'
Write operation W for the first swap operation at time
e is performed.

In the meantime, the second M that was transferred from BSI
XN bytes of write data are written to write registers 231, 232 .
..., 23M''.

The second deku imported in the above manner is t1
9′ to t 20′ memory 221.222
゜..., is written to 22M', and the second swan-pu operation is completed. Thereafter, the read operation for the next swap operation is similarly performed using the data transfer time.

As described above, by causing the MSU 2 to perform the memory operation even during the data transfer time, the swap operation can be performed at high speed.

(6) Effects of the Invention According to the present invention, by performing the memory read operation for the next swap operation during the data transfer time when the memory of the MSU is not operating, it is possible to waste the idle time of the BS. This makes it possible to perform highly efficient swap operations.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the swap operation according to the present invention, and FIG.
3 is an explanatory diagram of a swap operation between a BS and an MSU, and FIG. 4 is an explanatory diagram of a conventional swap operation. 1・・・−・・−BS, 2−・−・−・M
S.U. 11.21------Control circuit, 221
, 222. ... , 23M'--Memory, 231,232. ..., 23M'・
-------One write register. 241, 242. ..., 24M'--...--
-Read register, 5...-1-----Control device.

Claims (1)

[Claims] A storage device having an upper storage device, a write data register for temporarily storing a plurality of data, a read data register for temporarily storing a plurality of data, and control for controlling a swap operation between the upper storage device and the storage device. The data write operation is performed by storing a plurality of write data transferred from the upper storage device to the storage device in the write data register, and then writing the data to the memory in the storage device. The read operation is a read operation from the memory, whereby a plurality of data are read and stored in the read register, and then
In the system that performs transfer to the upper storage device, the control device determines that the memory is not performing a write or read operation during a data transfer time after a read operation from the memory or before a write operation to the memory. A swap control method characterized in that the control device recognizes and performs a read operation from the memory in the next swap operation.