JPH01147651A - Common bus access system - Google Patents

Abstract

PURPOSE:To avoid deterioration of a bus cycle due to the communication carried out between processors by producing an access display signal when a certain processor receives on access from another processor. CONSTITUTION:Plural processors 11-1m are connected to a common bus and each processor sends a bus acquisition request signal to a bus controller 3 to give an access to the bus 2 as long as a bus application signal is received from the controller 3. Then each processor sets an access request destination address given from another bus master and received via the bus 2 to an address buffer 21. This address is decoded by a decoder 22 and an access is identified. Thus a signal 220 is transmitted. Then an AND is secured by an AND circuit 6 between the signal 220 and a timing signal TG2 given from a timing circuit 5 and showing an access cycle busy mode. Then an access display signal ACC is transmitted.

Description

[Detailed Description of the Invention] [Summary] Regarding a common bus access method in a multiprocessor system that uses a common bus for transmitting addresses and data, the reduction in bus cycles due to communication between processors, which requires time for access, can be reduced by In order to prevent the increase in hardware and the complexity of control, each processor is provided with an access indication signal generation means that generates an access indication signal indicating that it is being accessed by another processor. When the access display signal generating means outputs an access display signal indicating that the processor is being accessed by another processor, reception of the bus use permission signal and bus acquisition and transmission of the acquisition request signal are prevented. Configured.

[Industrial application field]

This invention relates to a common bus access method in a multiprocessor system that uses a common bus for transmitting addresses and data.

[Conventional technology]

FIG. 3 shows the configuration of a conventional processor applied to a common bus access method for transmitting addresses and data.

A plurality of processors 11*12*... are connected to the common bus 2.
1m, a main storage device 4, etc. are connected, and access from these processors to the common bus 2 is controlled by a bus control device 3. The plurality of processors 11.12. . . . 1m have substantially the same configuration, and this figure shows only one processor 1. This section specifically shows the structure of the following.

This processor 1. This processor 1 . Code that specifies and registers to access 111.1
12.11 When the processor 1m sends an access address including a code specifying n, the processor 11 receives it and stores it from the reception tristate buffer 20 into the address buffer 21.

The decoder 22 decodes the access address stored in this address buffer and stores the data to be sent back to the other processor in the register 11. ．． 11□
, -.-1I n respectively. ．． 22□,... The output from 22n is connected to AND circuits 233.232. ...-23n is supplied to one input terminal of the AND circuits 23, . 23. ,−
The timing signal TG is supplied in parallel from the timing circuit T to the other input terminal of -23n, so data is read from the selected register during the period in which this timing signal exists.

At the same time, a switching signal is output from the output terminal 22° of the decoder 22 to switch the multiplexer 12 so as to send the data read from the selected register to the internal bus 13. Data is sent to one input terminal of multiplexer 16.

When access is requested from another processor, the bus controller 25 switches the multiplexer 16 so that the input from the internal bus 13 is sent to the tri-state buffer 17 on the transmitting side. The data from the registered registers is output onto the common bus 2, and the data from the processor 1. It is received by other processors 1m that have accessed it.

If this processor 11 accesses the main memory 4 or another processor, e.g. 12, via the common bus 2, the bus controller 25 switches the multiplexers 14 and 16 so that Addresses specifying the processor to be accessed and the register to be read are sent to the multiplexer 14;
It is sent from the tristate buffer 17 to the common bus 2 via the internal bus 15 and the multiplexer 16 mentioned above.

For example, if writing is to another processor or the main memory 4, the bus controller 25 then switches the multiplexer 14 and transfers the data stored in the data buffer 19 to the common bus in the same manner as described above. 2 and received by the main memory processor or main memory device 4.

If this access from the processor 11 is for writing data from another processor or the main memory device, a response is returned from the other processor or the main memory device 4 in response to the sending of the above access address. The data is transferred from the common bus 2 to the register 11 via the tri-state buffer 20 on the receiving side. , 112.・－・・・ll
n, and writing to a predetermined register is performed using the timing signal TG from the timing circuit T.

[Problem that the invention seeks to solve]

As described above, when accessed from another processor, for example 1m, via the common bus 2 to which the other processors 1112+, 1n and the main memory 4 are connected, the multiplexer 16 is connected to the internal bus from the multiplexer 12. When the processor 11 is ready to output data from the internal bus 13 and the processor 11 itself accesses the common bus 2, the multiplexer 16 is switched to output data from the internal bus 15 from the multiplexer 14.

Therefore, certain processors, for example 1. When using this common bus immediately after being accessed by another processor 1m via the common bus 2, it is necessary to switch the multiplexer 16 from the internal bus 13 side to the internal bus 15 side. The drawback was that it required time.

In order to reduce the time required for this switching, it would be possible to speed up this switching, but this would not only significantly increase the amount of hardware but also complicate the control, so this is not desirable as a practical solution. It wasn't.

Therefore, as an alternative method, when communicating between processors, the common bus is occupied for an extra period of time for switching the multiplexer than the cycle required for data transfer between processors, but the accessed processor immediately The common bus is not necessarily accessed, and other processors are unnecessarily prevented from accessing the common bus during this extra period.

Communication between processors as described above is less frequent than communication between processors and main memory, but the bus cycle of the common bus must be determined so that there is no problem even with the longest-required access. The bus cycles required for communication between processors as described above result in the use of slow bus cycles, and the switching of the multiplexer described above has been a cause of degrading the performance of the system.

An object of the present invention is to prevent a reduction in bus cycles due to communication between processors that requires time for access, without increasing hardware and complicating control.

[Means for solving problems]

As shown in the principle embodiment of FIG. 1, at least a plurality of processors 1. ．． 12. -1m is connected to the common bus 2, and when these processors access other processors etc. connected to this common bus via this common bus, the bus control device 3 uses the bus. In a multiprocessor system configured to send a bus acquisition request signal to this bus control device on the condition that a permission signal is present, and then access this common bus, each of the above processors has a An access display signal generating means including, for example, a timing circuit 5, an AND circuit 6, and an inverter 7 is provided to generate an access display signal indicating that the processor is accessing the processor. When an access display signal indicating that access is being made is being outputted, reception of the bus use permission signal and transmission of the bus acquisition request signal are prevented.

[Production m: Each processor sets in the address buffer 21 an address that specifies the destination of an access request from another bus mask received from the common bus 2, and decodes this address with the decoder 22 so that its own processor is accessed. When this decoder identifies that its own processor is being accessed, it outputs a signal 22° indicating that its own processor is being accessed, and an AND circuit 6 performs an AND operation with the timing signal TG2 indicating that the access cycle is in progress from the timing circuit 5. This generates an access indication signal ACC indicating that it is being accessed by another processor.

When this access display signal is being output, this signal inverted via the inverter 7 shuts off the AND circuit 8 and prevents the bus controller 25 from sending the bus acquisition request signal REQ to the bus control device 3. At the same time, the AND circuit 9 is cut off to prevent reception of the bus use permission signal REQEN from the bus control device 3.

〔Example〕

In the explanatory diagram of the embodiment in FIG. 1, the same reference numerals are given to the components corresponding to the components in the conventional example explained in FIG. A timing circuit 5 is added to the conventional example shown in FIG. 3 and generates a second timing signal TG2 in place of the timing circuit 24 shown in FIG.

The decoder 22 outputs a switching output 22° indicating that it is being accessed from another processor, and the second
During the period in which the timing signal TG2 is output from the timing circuit 5, the output from the AND circuit 6 is at the "1" level, and the voltage level applied to one of the input terminals of the AND circuit 8 via the inverter 7 is Since it becomes “0”,
Even if the bus acquisition request signal REQ' is output from the bus controller 25, this bus acquisition request signal does not reach the bus control device 3.

Further, as mentioned above, while the output of the inverter 7 is "0", the AND circuit 9 is cut off by this inverter output, so even if the bus use permission signal REQEN from the bus control device 3 arrives, the AND circuit 9 is cut off. The bus controller 2°5 receives the bus use permission signal R.
EQEN' does not arrive, so this processor cannot use the bus.

FIG. 2 shows a time chart of the common bus access method according to the present invention, in which processor 1 and processor 1□
This figure shows the operation when this processor 12 issues a bus use request immediately after reading the register.

The bus use permission signal REQεN from the bus control device 3 is
Processor 11.12.・During the period when none of the processors 1m is accessing the common bus 2, the potential is maintained at the "1" level, which allows all of these processors to use the bus, but in the bus cycle #2, the processor When the processor 11 sends a bus request signal REQ' to read the register of the processor 1□, the potential of the bus use enable signal REQEN is set to the "0" level.

Then, during the next bus cycle #3, this processor 11 sends an address specifying the processor 1 □ to be accessed and the register to be read by the processor 1 □ onto the common bus, and the processor 1 □ sends an address to the common bus during the following bus cycle #4. The access is indicated by the output from the AND circuit 6, which takes the logical product of the signal 22° indicating that the own processor is being accessed, obtained by decoding this address during the period, and the timing signal TG2 from the timing circuit 5. A signal ACC is output, and at the same time data from required registers is sent onto the common bus, and the processor 1 takes in this data.

Note that in this #4 bus cycle, processor 1
．． Bus control device 3 has completed bus acquisition.
returns the bus use permission signal REQEN to the "L" level.

When the bus controller 25 of the processor 12 sends the bus acquisition request signal REQ' during the #4 bus cycle period, the second timing signal TG2 outputted from the timing circuit 5 and the own processor Decoder output 22. indicating that is being accessed.
The “1” level signal of the access display signal ACC, which is the logical product of the AND circuit 6 and the
Since this bus acquisition request signal REQ' is supplied to one input terminal of the AND circuit 8 as a potential of 0'' level, it is not transferred to the bus control device 3.

In the next bus cycle #5, since the decoder output 22° indicating that the decoder 22 is being accessed is 0''' due to the completion of access, the access display signal ACC becomes "0", and the inverter Since this signal inverted to "1" by 7 is supplied to one input terminal of the AND circuit 8, the bus acquisition request signal REQ' from the bus controller 25 is sent to the bus control device 3 as a bus acquisition request signal. REQ, and as a result, during the next bus cycle #6, an address designating the processor to be accessed, for example 1m, and the register to be read is sent onto the common bus 2.

[Effects of the Invention] According to the present invention, a reduction in bus cycles due to communication between processors that takes time to access can be prevented by adding only a few components without requiring software control. effect can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the common bus access method according to the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a diagram showing a conventional common bus access method. 13.1 z,---1n is a plurality of processors, 2 is a common bus, 3 is a bus control device, timing circuit 5,
The AND circuit 6 and the inverter 7 are components of access display signal generation means.

Claims (1)

[Claims] At least a plurality of processors (1_1, 1_2, . . .
1_m) is connected to a common bus (2), and when these processors access other processors etc. connected to this common bus via this common bus, the bus control device (3) Bus use permission signal (REQEN
) is configured to send a bus acquisition request signal (REQ) to this bus control device on the condition that the common bus is present, and thereafter access this common bus, each of the above processors: Access indication signal (AC
C) Access display signal generating means (5, 6, 7)
), and when the access indication signal generation means outputs the access indication signal indicating that the processor is being accessed by another processor, it receives the bus use permission signal and sends the bus acquisition request signal. A common bus access method characterized by preventing