JPS61125655A - Memory access controller - Google Patents

Abstract

PURPOSE:To shorten an access time by transmitting a request to the 2nd main memory access circuit for high performance accesses when a high performance display flag is set at '1'. CONSTITUTION:When a request A is sent from a peripheral controller, an acceptance circuit 20 accepts the request A. In such a case, a high performance display flag F/F23 is set at logic '0'. Then the request Q is transmitted to a request holding circuit 21 via the 2nd AND gate, and the circuit 20 accepts the 2nd request B. This request B sets the flag F/F23 at logic '1' and is transmitted to the 2nd main memory access circuit 24 via the 1st AND gate 25. The 1st and 2nd main memory access circuits 24 and 25 send the different requests to a main memory 10. The circuit 10 decides the priority and processes the circuit 24 earlier than the circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory access control device used in an information processing device.

(Prior Art) In conventional memory access control devices, requests from multiple peripheral control devices whose priorities are determined are sometimes accepted with priority control, and the data is received from the data bus by the receiving system. , was sending a request to main memory. By adopting a pipeline mechanism in which the next request is accepted until the response is returned from the main memory, the requests are sequentially sent to the main memory, and the response is waited for. I went through several receptions before I returned. The response from the main storage device is determined by the order in which the request was sent to the main storage device, that is, the reception by the memory access control device is determined by time priority control. Therefore, when a request from a peripheral control device that requires an access time is accepted, if the other peripheral control device has already processed the request, in the above configuration, the request may be sent to the main memory. Since it has been determined, the memory access time becomes #@ including the preceding access request.

(Problem to be Solved by the Invention) When attempting to connect a peripheral control device that requires high performance access time to such a system, it is necessary to increase the memory access control device and main storage device to meet the highest required performance. The drawback is that it is expensive because it requires improved performance.

In addition, in order to shorten only the access time, if requests were sent to the main memory unit individually without collectively controlling access to the main memory unit, a bus structure could not be adopted and the amount of hardware would increase. .

The purpose of the present invention is to read the state in which the high-performance display flag F/F is set/reset when accepting a request from a peripheral control device, and when the request is accepted from a circuit for high-performance access when it is set. The button is transmitted to the main memory access circuit and accesses the main memory separately from the preceding memory access request.This button eliminates the above disadvantages and is useful when connecting a peripheral control device that requires high-speed access time. An object of the present invention is to provide a memory access control device configured to speed up memory access time regardless of other requests that are in advance.

Measures for solving problem 8) The memory access control device according to the present invention is a main storage device,
and a plurality of peripheral control devices to collectively control access from the peripheral control devices to the main storage device.The reception circuit is connected to the circuit and 111! It is configured to include the above request holding circuit, first and second main memory access circuits, and a high performance display flag F/F.

The reception circuit is for receiving requests from peripheral control devices.

The request holding circuit is for holding the received request.

The first and second main memory access circuits are for directly accessing the main memory.

The high performance display flag F/F is for displaying high performance at the time of reception.

In the present invention, in the above configuration, the high performance display flag F'/
When F is set, the request is transmitted from the reception circuit to the first main memory access circuit through the request holding circuit, and when the high performance display flag F/F is set, the request is transmitted from the reception circuit to the first main memory access circuit. The signal is transmitted to the second main memory access circuit and the main memory is accessed.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a memory access control device t according to the present invention.
FIG. 2 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 4C, lO is the main originating tl' device, 11 is memory access 1-limit-ambiguity, 12 hatetahas, 13-16
20 is a reception circuit, 21 is a request holding circuit, 22 and 24 are first and second main memory access circuits, respectively, 23 is a high performance display flag F/F,
25 and 26 are first and second AND gates, 30 is a main memory response circuit, 31 and 32 are first and second memory circuits, respectively, and 33 is a bus response circuit.

The reception circuit 20 performs priority control of requests from a plurality of peripheral control devices 13 to 16, gives the priority peripheral control device the right to use the data bus 12, and receives details of requests for addresses and write data. be. The request holding circuit 21 is for holding a request until the first main memory access circuit z2 finishes accessing the main memory device 10.

The first and second main memory access circuits 22 and 24 are
This circuit is for outputting details of K, address, write data, and request code at the same time as sending a request to main memory #10. The main memory access circuit @2 is a circuit used only when high performance is required. The high performance display flag F/F 23 connects the first and second AND gates according to the output signal of the flag. Alternatively, it is used to gate which of the second main memory access circuits 24 the signal is transmitted to. Main memory response circuit 30
receives the response from the main memory bag jil 10, and
This is for receiving read data and status information.

First and second memory circuits 31, 32 of first-in, first-out type
is a read/write request when accessing the main memory circuit IO.
The content of the write request is stored and the content is continuously output when a response is returned.

The bus response circuit 33 checks the in-use flag of the data bus 12, and if it is not in use, receives a response from the main memory response circuit 30, outputs it to the data bus 12, and outputs it to the peripheral control device.
This is a circuit that reports completion to 13 to 17.

Next, the operation of the real S column will be explained.

Here, the requester is a request for normal processing, and the request Bi is a request characterized by high performance access time. First, when a requester is sent from the peripheral control device, the reception is processed by the circuit 20. At this time, the state of the high performance display flag F/F 23 is set to logic "0#", the request is transmitted to the request holding circuit 21 via the second AND gate, and the reception is performed in the circuit 20, and the next reception is Processing is performed.The next accepted request B has a high performance display flag F/
When the state of Fz3 is set to logic '1' and this flag becomes logic '1', request B is transmitted to the second main memory access circuit 24 via the first AND gate 25.

While the first main memory access circuit 22 is processing, the requester remains held in the holding circuit 21.

The first and second main memory access circuits 24 and 25 separately send requests to the main memory 10, and the main memory 10 determines the priority order, and the second main memory access circuit 24 is sent first. to be processed. When the access from the first main memory access circuit 22 to the main memory device 10 is completed, the first main memory access circuit 22 takes out the requester from the holding circuit 21 and accesses the main memory device 10 . In the response from the main memory bag 1i10, the first b is the second main memory access circuit 22.
This information causes the main memory response circuit 30 to respond to the first and second memory circuits 3.
Read/write information is read from one of 1 and 32. In order to give priority to the first main memory access circuit 22 in the main memory device 10, the response B is sent to the main memory circuit 3 before the response A.
0.

Therefore, the main memory response circuit 30 outputs data M6 from the second memory circuit 32 and controls it, and transmits the data to the bus response circuit 33. When the response B is transmitted to the bus response circuit 33, the response A is received by the main memory circuit 30 and sent to the first memory circuit 31.
Read the contents of and perform the same processing. Therefore, the order of output to the data bus L2 is for response B first, followed by the responder.

FIG. 2 shows the operation sequence of the embodiment shown in FIG. Symbols a - e each represent a request.

Request d is a request from a peripheral dftJ device that requires high performance.

In this implementation, the order of the access results for request C and request d is response C, which is followed by response d1. In the case of normal processing, the access time is T1, and when the high performance display flag F/F 23 indicating high performance is set to 11 m, the access time becomes T4, and the access time can be shortened.

Further, the number of holding circuits is not one stage as in this embodiment, but can be expanded to n8 stages according to the processing performance time of the main storage device and peripheral control device. In this case, if high-speed processing is performed, the main memory can be accessed from the request n times earlier.

(Effects of the Invention) As explained above, in the present invention, the high performance display flag F/
When the flag is set to "l" with F, the request is accepted by the circuit and transmitted to the main memory access circuit of vX2 for high performance access.
This has the effect of shortening the processing time required to access the main memory, and also shortening the access time when a peripheral control device that requires high performance access time is connected. Furthermore, by adopting the bus structure and configuring the memory access control device Wt, there is an effect that an increase in the number of dunnians can be prevented.

FIG. 2 is a block diagram illustrating an example.

Figure 2 shows the memory access system shown in Figure 1.
3 is a time chart showing an example of an operation sequence.

10...Lord f! IJ@t12...data bus 13-16...peripheral? tllJa11 device 20... Reception circuit 21... Request holding circuit 22
, 24... Main memory access circuit 23... High performance display flag F/F 25, 26... AND gate 30... Main memory response circuit 31. 32... Memory circuit 33... Bus response Circuit diagram 1

Claims (1)

[Claims] In an access control device connected to a main storage device and a plurality of peripheral control devices and for collectively controlling access from the peripheral control device to the main storage device, reception for accepting a request from the peripheral control device. a circuit, one or more request holding circuits for holding said accepted requests, first and second main memory access circuits for directly accessing said main memory, and displaying high performance upon said acceptance. and a high performance display flag F/F for the first main memory access circuit. transmitted to,
The present invention is characterized in that when the high performance display flag F/F is set, the request is transmitted from the reception circuit to the second main memory access circuit and the main memory is accessed. memory access control device.