JPS60123956A - Memory writing device - Google Patents

Abstract

PURPOSE:To shorten the memory writing time of a processor, by sending out data of the same contents and continuous memory addresses at once from the processor to a data transfer controlling device, when said data are written in the continuous memory addresses. CONSTITUTION:A data register 10, address register 11 which is capable of update by (+1), and subtracting by (-1) register 16 which performs count-up control on the address register 11 are installed to a data transfer controlling device 2. The subtraction counter 16 once stores the number of continuous addresses and performs (-1) subtraction whenever memory writing is performed. A flip- flop 26 controls the output of a memory writing request signal. Each register 10, 11, and 16 decodes a memory writing request from a common bus 3 by means of a decoder 25 and writing is simultaneously performed synchronously to a timing pulse 30. The number of continuous addresses is set in the subtraction counter 16 from a signal line 18 and subtraction by (-1) is performed at every memory transfer. This operation is repeated until all the outputs are reduced to zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transfer device for convolving all data of the same content into consecutive memory addresses.

[Purpose of the invention]

An object of the present invention is to convolute data of the same content into consecutive memory addresses without performing data communication between the processing unit and the main memory (C or lower MM) every - times of data transfer. An object of the present invention is to provide a device that significantly shortens the memory writing time of a processing device by sending consecutive addresses n=i from the processing device to a data transfer control unit (hereinafter referred to as MCU).

[Background of the invention]

The hardware that is the object of the present invention is shown in FIG.

1 is the main memory, 2 is the MCU, 3 is the common node, 4 to 6
Is it a processing device? show. Data transfer requests from the processing units 4 to 6 are all output to the common processing unit 3, and the MCU 2 determines the priority and sequentially transfers data to the IMI? Let's do it. In this case, there are three types of information: (a) data, (b) data transfer direction, and (C) MM address, and transfer information is exchanged for each word. Therefore, even when data of the same content is written to consecutive MM addresses, the data is transferred from the processing device again even though the data is in the MCU, which is inefficient. Figure M2 is a detailed view of Figure 1. The common bus 3 is composed of a data bus 7, an MM address bus 8, and a bus indicating a data transfer direction 9.
The MCU 2 is connected to a data register 10°, an MM address register l l %, and a data transport control circuit 12, respectively. Similarly, the processing devices 4 and 5 have registers 13 . There are a register 14 for sending MM addresses and a control circuit 15 for specifying the direction of data transfer, which are connected to the common bus 3.

FIG. 3 shows a data transfer time chart on the common bus 3, showing MM addresses 8 (memory addresses) n, n+1 .
Data 7 “l bl cl d” for m and m+l respectively
It is recommended to transfer the information. FIG. 4 shows a case in which the same data is transferred to consecutive addresses, which is the object of the present invention, and represents that data a is transferred from address n to address n+4.

[Summary of the invention]

What are the main points of the present invention shown in Figures 5 to 7? show.

FIG. 5 shows the data structure which is the key point of the present invention. Number of consecutive words in parallel with written data (continuous addresses)
By sending all the data, it becomes possible to write the same data to n consecutive addresses in one transfer. In FIG. 5, bits 0 to 15 indicate write data [7, bits 16 to 15]
19 indicates a continuous address bus. In other words, if the number of consecutive addresses is 5, the same data can be stored in 5 consecutive addresses.
To transfer times? means. FIG. 6 shows the hardware 9 of the present invention. ~1cU2 contains data register l
In addition to O, there is an address register ll that can be updated by +1, and a counter 16 that controls the total number of new and new addresses in this address register 11 and decreases the number of successive addresses n busy once every time the memory is written.
However, the common bus 3 also has a continuous number of addresses on the signal line 18 for communication. The processing unit 4 also has a continuous address register 17. FIG. 7 shows a time chart of data transfer according to the present invention.

Here, an example will be shown in which a booter a is written at memory addresses 1000 to 1007. On the common bus 3, the memory address i'11000 is sent out onto the 21st address bus, and at the same time, data a is sent out onto the 24th data bus. 2 at the same time as data transmission
Continuous address designation "8" is sent on the 0 signal line. Only this one data transfer is performed on the third common bus. Next, MCU2. The memory address bus 23 and the data bus 22 are used to transfer data between MMIs.
The data "Se" is transferred at address 1007 in order. Therefore, whereas conventionally the common bus 3 was occupied during the time period for data transfer up to address 1007, it is now possible to release the common bus 3 from '1' in the figure, and during this period, mutual communication between the processing units 4 to 7, etc. It can be used for other purposes, and the processing performance of the entire processing apparatus can be improved.

[Embodiments of the invention]

A specific embodiment of the present invention is shown in FIG. MCU2 has data register 10 and +1 updateable address register 1.
1. Is this address register 11 count up control?
-1 subtraction counter 16 The subtraction counter 16 performs an operation of storing 'In' in successive addresses and incrementing the memory by 1 every - times. Reference numeral 26 indicates a free-lag frog, which controls the output of the memory 1 loading request signal. Reference numeral 27 indicates a memory write request signal, and 28 indicates a response signal thereof.

10.11.16 Each register receives a memory write request from common node 3? 25 decoders, and 3
Writing is performed simultaneously in synchronization with the 0 timing pulse. 29 is a data transfer control signal line of common node (3), which controls the data transfer direction and timing.The number of consecutive addresses is sent from the 18 signal lines to the 16 subtraction counter, and is decremented by 1 for each memory transfer. , all outputs are O
This operation is repeated until . Through these operations, data with the same content 'fI' is stored in consecutive memory addresses.
: Enables writing.

[Screaming effect]

According to the present invention, if km of the same data is stored in consecutive addresses, it is possible to transfer n consecutive addresses, which frees up space and can be used for other purposes such as common basketball.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the conventional target configuration, Fig. 2 is a detailed view of Fig. 1, Figs. 3 and 4 are conventional data transfer time charts, and Fig. 5 shows the data format of the present invention. FIG. 6 is a hardware configuration diagram of an embodiment of the present invention, FIG. 7 is a data transfer time chart of the present invention, and FIG. 8 is a circuit diagram of the present invention. 11... Address register, 16... Subtraction counter. Agent Patent Attorney Akio Takahashi $7 figure memo'/7 dress (=7t sheet) ◇72'j Ya Zoku Ato U
SwI glance A sig==1−=Σ−″.

Claims (1)

[Claims] 1. In a data transfer device between a main storage device and a processing device, when data with the same content is written to consecutive addresses,
The number of consecutive transfer words ni is sent at the same time as the data, so that n consecutive words are transmitted in one data transfer? For batch transfer, a device that controls all data transfer between the main storage device and the processing device has a first counter that increments all transfer addresses by 1, and the output of this counter is set as the address of the main storage device. a second counter that stores n consecutive words and increments by 1 for each memory write; and means for writing the same data into the main memory until the content of the second counter becomes 0. A memory writing device characterized by: