JPS63165940A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity as well as the cost of a data processor by utilizing a signal line in a system bus to perform an interruption. CONSTITUTION:In case a system bus 5 has a split cycle synchronous with a clock, a channel 3a receives an opportunity to give an access to an MMU 1 via the bus 5 from a prescribed protocol or a bus arbiter. In this case, a memory 4 of the MMU 1 is fetched to check whether the contents of the memory 4 are blank (0) or not. If so, a semaphore signal is set to prevent another channel from writing data into the memory 4. Then the memory 4 is fetched again after confirming whether the semaphore signals received from its own channel is set or not. A format is written into the memory 4 after confirming that the contents of the memory 4 are equal to 0. Then the semaphore signal is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and particularly to a circuit for issuing an interrupt from a channel to a central processing unit (hereinafter abbreviated as CPυ).

[Conventional technology]

FIG. 4 is a block diagram showing interrupt-related circuits in a conventional device. In the figure, 11) is the main memory (hereinafter abbreviated as "main storage"), (2) is the CPU, (3a) t (
3b) are respective channels (hereinafter abbreviated as CIA')
,! 51 is the system path, -16) is the response line,
(7) is the data/address line, and (8) is the ID line (to make the drawing easier to read, the data/address line (7) and ID line (8) are
) are shown together.

(9) is a semaphore (signal for external control) line, (41) is an interrupt line, (42) is a priority (priority instruction) line, (43a) and (43b) are respective interrupt generation circuits,
(44a) and (44b) are priority order determining circuits, respectively.

Next, the operation will be explained. Channel (3a) is CPU
When issuing an interrupt to T21, the interrupt generation circuit (43a
) f, operates and sets the signal logic on interrupt #I (41) to "1". When this interrupt is accepted by the cPU (2), the CPU 121 learns of the occurrence of the interrupt from the signal logic on the interrupt line (41) and starts interrupt processing. That is, when a read request signal is issued from the CPU (1), the channel with the highest priority (for example, CHA (3a)) among the channels currently attempting to issue an interrupt returns the channel address of that channel. The priority of each channel is determined by the signal logic on the priority line (42), and in the simplest case of the system shown in FIG. When the upstream channel operates the interrupt generation circuit, the signal logic on the priority line (42) from that channel becomes, for example, rOJ, which also suppresses the operation of the downstream channel's interrupt generation circuit. Enable.

CPU t21 receives the channel address of CHA (3a) and performs necessary interrupt processing.

[Problem that the invention seeks to solve]

Since the conventional device is configured as described above, it requires an interrupt line (41) and a priority line (42) in addition to the system bus (5), and an interrupt generating circuit and a priority determining circuit are installed in each channel. Therefore, there was a problem in that the amount of hardware constituting the system increased.

The present invention was made to solve the above-mentioned problems, and its object is to configure a data processing device that can issue an interrupt request using only the system path.

[Means for solving problems]

In the device of this invention, when a channel issues an interrupt request to the CPU, the channel address of the channel is stored at a specific address in the cabinet, and in order to notify the CPU that an interrupt request has been issued, a A signal indicating the generation of an interrupt request was sent to the CPU using the ID line and response line.

[Effect]

When the CPU learns that an interrupt request has occurred, it reads the specific address of m and performs interrupt processing accordingly, and when the interrupt processing is completed, the content of the specific area is blanked. Therefore, in other channels, when a key pattern and channel address are set at a specific address, it is understood that the CPU is processing an interrupt and interrupts are prohibited until the content of the specific address becomes blank. do.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, and (4) is MM.
This is the memory at a specific address within U(1).

FIG. 2 is a format diagram showing the signals written to the memory (4) in FIG. 1, where (21) is a specific key pattern,
(22) is the channel address, and the key pattern (21
) indicates that the channel at channel address (22) is currently raising an interrupt and is waiting for the CPU 121 to finish this interrupt processing.

FIG. 3 is a flowchart showing a part of the operation of the apparatus shown in FIG. 1, and (301) to (310) are each step.

The operation of the apparatus shown in FIG. 1 will be explained below with reference to the $3 diagram.

If system path (5) is a clocked split-cycle system path (5), channel (3
a) is given the opportunity to access the MV[U lit via the system bus (5) by a predetermined protocol or by a bus arbiter (not shown). Taking advantage of this opportunity, enter step (301) and fetch the memory (4) of MMU 111, and check whether the content is blank (hereinafter denoted by O) or not (step (302)). Wait until it reaches 0. If O, other channels are memory (
A semaphore signal is set to prevent writing to 41 (step (303)). However, if there is a semaphore signal set by another channel, the own channel
The channel semaphore signal cannot be set.

After checking whether Sema 7 OR from own channel was set in step (304), step (305)
After fetching the memory (41) of the MVfLT 111 again and confirming that the content of the memory (4) is 0 in step (306), write the format shown in Figure 2 to the memory (4) of the MMLT 111. After doing so (step (307)), the semaphore signal (308) is reset.After that, an interrupt request is issued to the CPU 121 using a signal line used for other purposes within the system bus (5). Notify (step (309))
.

For example, a bit pattern indicating the occurrence of an interrupt is placed on the ID line 181, and the signal logic on the response line (6) is set to ``1''.
”. CPU +21 sees the signals on the ID line (8) and response line (6) and knows that an interrupt has occurred, and then sends NjNLU
After reading the contents of ill's memo (January 4) and performing the corresponding interrupt processing, the contents of the memory (4) are set to 0.

If the determinations in steps (304) and (306) are NO, the semaphore signal is reset in step (310), and then the process returns to step (301).

〔Effect of the invention〕

As described above, according to the present invention, interrupts can be raised using the signal line in the system bus without the need to provide a special signal line exclusively for interrupts, which reduces the amount of hardware required and reduces the cost. It is possible to configure various devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a format diagram showing signals written to the memory at a specific address in FIG. 1, and FIG. 3 is an illustration of the operation of the device shown in FIG. FIG. 4 is a block diagram showing a conventional device. (1) is m, (2) is CPU, (3a) is channel, (4) memory at specific address 111 of Habato, (5) is system bus, (6) is response line, (7) is data /
Address line, (8) is ID line, (9) is semaphore gamma ray. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) In a data processing device configured by a central processing unit, a main storage device, and a channel connected to a clock-synchronized split-cycle system bus, the central processing A specific memory that stores a key pattern indicating that the device is processing an interrupt and the channel address of the channel that requested the interrupt. After checking, writing the key pattern and the channel address of the channel in the specific memory, and then notifying the central processing unit of the occurrence of an interrupt using a signal line used for other purposes within the system bus. , means for the central processing unit to execute interrupt processing according to the contents of the specific memory after learning of the occurrence of an interrupt, and to erase the contents of the specific memory after the interrupt processing is completed. Device. (2) The means by which the channel attempting to issue an interrupt request writes the key pattern and the address of the channel to the specific memory after confirming that the contents of the specific memory are blank is 2. The data processing device according to claim 1, wherein writing is performed after setting an exclusive control signal on an exclusive control signal (semaphore) line on a bus. (3) The signal lines used by the channel to notify the central processing unit of the occurrence of an interrupt are an ID line and a response signal (response) line within the system bus, as set forth in claim 1. data processing equipment.