JPS5953959A - Shared memory device - Google Patents

Abstract

PURPOSE:To cause no confliction in a shared memory, by providing clocks whose phase is different to each signal group, and generating a read-out/write-in request signal synchronously with these clocks. CONSTITUTION:Data processing devices 1', 2' are connected to a shared memory device 3' through a receiving signal line 11', a transmitting signal line 12' and a clock line 13', and a receiving signal line 21', a transmitting signal line 22' and a clock line 23', respectively. Also, a memory device controlling circuit 4' in the device 3' transmits a clock generated in the inside, through the line 13' and 23'. Subsequently, synchronously with them, a memory request signal, an address, a read-out/write-in designation and a write data which are sent through the lines 11', 21' from the device 1', 2', respectively are received, the address and the read-out/write-in data are transmitted to a memory device 5' through a memory operating signal 31', and a read-out or write-in operation is executed to a designated address of the device 5'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared memory device that is connected to a plurality of data processing devices and used in common.

<Prior Art> Conventionally, a shared memory device connected to a plurality of data processing devices has a configuration as shown in FIG. 1, for example. That is,
Data processing devices 1 and 2 include a shared memory device 3, a receiving signal line 11, a transmitting signal line 12, and a receiving signal line 2, respectively.
1. The memory device control circuit 84 in the shared memory device 3 is connected via the transmission signal line 22 and is connected to the reception signal lines 11 and 2.
1 receives the memory request signal, address and read/write designation transmitted by the data processing device 1.2;
The address, read/write timing, and write data are transmitted to the memory device 5 in the shared memory device 3 via the memory operation signal line 31, and the memory device 5 writes or specifies the specified address based on these signals. In the case of reading, the read data is transmitted to the memory device control circuit 4 via the read data line 32, and the memory device hardening circuit 4 performs data processing 'i'.
′! Read data was transmitted via the transmission signal line 12 or 22 at the request of the devices 1 and 2.

In the conventional device shown in FIG. 1, two groups of memory request signals, addresses, and read/write designations received by the memory device control circuit 4 via reception signal lines 11 and 21 are sent to data processing devices 1 and 2, respectively. Since the signals coming from the data processing devices 1 and 2 are given asynchronously, it is necessary to take measures to avoid collisions between these signals within the memory device control circuit 4, and also to prevent accidental failures caused by such collisions. It could be the cause of.

<Summary of the Invention> An object of the present invention is to provide a shared memory device which receives memory request signals from a plurality of data processing devices and avoids conflicts among these memory request signals.

Another object of the present invention is to synchronize the reception time of each signal group with a clock in a memory device that receives a plurality of groups of memory request signals, addresses, read/write specifications, and write data, and to receive the signals at predetermined times. By doing so, it is an object of the present invention to easily realize a memory device that eliminates contention between these signals, and to provide a shared memory device that can prevent accidental failures due to contention.

According to the present invention, a signal group including memory request signals, addresses, read/write designations, and notification data issued from a plurality of data processing devices is received by the first means in synchronization with clocks having different periodic phases. , the address, read/write designation, and write data generated by the first means in accordance with the signal group are input, reading or writing is performed in the storage means according to the address, and the read data that is the output of the storage means is stored in the storage means. The signal group is configured to be outputted from the second means in response to a request for a signal group.

First Embodiment> Next, an embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 2 showing the first embodiment of the present invention, data processing devices 1 and 2'' are connected to a shared memory device 3', a receiving signal line 11', a transmitting signal line 12', and a clock line 13', respectively.
, and are connected via the receiving signal line 21', the transmitting signal line 22', and the clock line 23'.
The memory device control circuit 4' in the internal memory device control circuit 4' transmits internally generated clocks via the clock lines 13' and 23', and in synchronization with these, the memory device control circuit 4' transmits internally generated clocks to the data processing device 1', respectively.
and 2' via the reception signal lines 11' and 21', and receives the memory request signal, address, read/write designation, and write data sent to the memory device 5' via the memory operation signal line 31'. A read/write signal and write data are transmitted to perform a read or write operation to a designated address of the memory device 5'. If this is a read operation, the read data is received by the memory device control circuit 4' via the read data line 32', and the signal sent via the receive signal line 11' or 21' is also transmitted. The read data is transmitted to the data processing device 1' or 2' via the signal line 12' or 22'.

The timing relationship of each signal in this first embodiment is shown in FIG. 3 with the timing normalized by the period T.

In the following explanation, the signal line numbers used in FIG. 2 are also used as signal numbers, and it is assumed that the leading edge of the clock is valid and the high level of other signals is valid. The clocks 13' and 23' have a period of 2T and are out of phase with each other by T, and the memory request signal, address, read/write designation, and write data are sent to the clocks 13' and 23' as received signals 11' and 21'. These received signals 11' or 21' are used to control the memory device control circuit 4.
At ', a memory operation signal 31' including an address, read/write signal, and write data is output and applied to the memory device 5' to perform a write operation or a read operation.
The work is done.

If it is read and one work, read data 32'
is output, given to the memory device control circuit 4', and sent to the requested data processing device 1' or 2' according to the request of the received signal 11' or 21' (i signal 12' or 22').
given as.

As can be seen from Figure 3, clock 13'(23')
, received signal 11'(21')→memory operation signal 31'→
Successive data 32'→transmission signal 12'(22') are generated in this order, and the interval between them is 02 in this example.
5T, 0.5T, and 0.25T, and since clocks 13' and 23' are generated every other IT, the memory operation signal 31' is valid between ITs and is valid between 0.5T. The read data 32' is processed by the data processing device 1' or 2.
, there is no collision on the signal lines 31' and 32' due to the request of 2' can perform read or threat operations on the shared memory device ξ5' every IT without delay. In addition, in FIG. 3, the memory operation signal 31
The 'read data 32' is shown separately for each request source.

<Second Embodiment> Next, in FIG. 4 showing a second example fj(, 6) of the present invention, the data processing devices 1" and 2I and the shared memory device 3" are connected to the receiving signal line 11", respectively. Transmission signal line 127
Clock line 13'', reception signal line 21'', transmission signal line 2
2″, connected via clock line 23″, shared memory I
The memory device control circuit 4'' in the Jy4 box 3'' sends addresses, read/write designations, and write data to the data processing devices 1'' and 2'' in synchronization with clocks transmitted via clock lines 13'' and 23'', respectively. It is believed that signals containing
1-1'' and 21'', and sends the address,
Send read/write signals and write data to the memory device 5
Write or read operation to the specified address within "or 6". If this is a read operation, the memory device control circuit 4'' receives read data output from the memory device 5'' or 6'' via the read data output line 32'' and outputs the read data on the reception signal line 11'' or 21''. According to the applied signal, it is applied to the requested data processing device 1'' or 2'' via the transmission signal line 12'' or 22#.

Note that memory devices #5' and #6'' are assumed to be connected to the same signal line with the memory device control circuit 4'', but some read/write signals and memory It may be considered that there are separate signal lines for transferring signals specifying the device 5'' or 6''.

Next, the operation of the second practical fj (6 examples) of this invention will be explained using the timing diagram normalized to the period T shown in FIG. is indicated by the number of the signal line, and assumes that the clock is at the leading edge and the other signals are high level or valid.Referring to FIG. The reception signals 11 and 21" including the address, read number designation, and write data are received by the memory device control circuit 4" in synchronization with the clocks 13' and 23", respectively. The memory operation signal 31'' containing data is transmitted to the storage devices 5#, 6
”, and in the case of a read operation, the read data 3
2" is outputted from one of the storage devices 5" or 6# and given as a transmission signal 12" or 22# from the memory device control circuit 4" to the requested data processing device 1" or 2".

Here, as shown in FIG. 5, there is an IT phase difference with the clocks 13'&23'', and each is generated with a period of 2T,
These signals are clock 13″ (23, received signal 1)
"(21") → Memory operation signal 31" → Read data 3
0.5 each in the order of 2″→transmission signal 12″ (22″)
T, IT, generated at 0.5T, memory operation signal 3
1'' and read data 32'' are valid during IT, there is no signal conflict on signal lines 31 and 321. The access time of memory devices 5″ and 6″ is IT,
If the cycle time is 2T, data processing devices 1' and 2'' or different memory devices 5'' and 6'' are used in parallel, respectively.
There is no contention (, IT
There is a conflict only when a read/write request is made to the same memory device 5" or 6", and the memory device control circuit 4" needs to operate to eliminate the conflict. In such a case, for example, The memory request received first shall be given priority.

As is clear from the description of the first and second embodiments of the present invention, by receiving read/write requests consisting of different signal groups in synchronization with clocks of different phases generated by the shared memory device, the shared Conflicts of read convolution requests in the memory device can be avoided, but for this purpose the data processing 9fi coupled to the shared memory device must perform read and write requests in synchronization with the clock of the shared memory. It will be clear that this synchronization request circuit can be easily implemented with well-known synchronization circuits.

<Effects> As described in Section 2, according to the present invention, in a shared memory device that receives readout requests from different devices via different signal line groups, clocks with different phases can be applied to each signal line group. By issuing read/write request signals in synchronization with these clocks, it is possible to provide a device free from contention within the shared memory device.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional shared memory device, Figure 2 is a block diagram showing a conventional shared memory device.
3 is a block diagram showing an example of the operation timing of the first embodiment, FIG. 4 is a block diagram showing a second embodiment of the invention, FIG. 5 is a diagram showing an example of the operation timing of the second embodiment. 1, 2. 1', 2', ]#, 2'': data processing device, 3°3', 3': shared memory device, 4.
4', 4": Memory device control circuit, 5 + 52 5
″, 6″: Memory device, ], ],, 21. 1
], ", 21', 11", 211': Received signal, 12, 22, 1.2', 22', 12", 22": Transmitted signal, 13', 23', 13", 23"
: Clock, 31.31', 32": Memory production signal, 32.32'32' Read data. Patent applicant Takashi Kusano, agent for NEC Corporation

Claims (1)

[Claims] (1) A first means for receiving a signal group including memory request signals, addresses, read/write designations, and write data issued from a plurality of data processing devices in synchronization with clocks having different periodic phases; A storage means receives as input an address, a read/write signal, and write data generated by the first means according to the group, reads or writes according to the address, and reads the read data output from the storage means into the signal. and second means for outputting in response to a request of the group.