JPS6213689B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display device, and more particularly to a CRT display device in which a CRT screen can be arbitrarily divided horizontally and displayed.

A typical conventional CRT display device has a display capacity of 24 lines x 80 characters = 1920 characters, and there is a one-to-one correspondence between the display position on the screen and the storage device. In this case, when displaying data with only 40 characters per line, the right half of the screen was left blank and the data was displayed on the left half of the screen.

The purpose of the present invention is to make it possible to display other data on the right half of the screen in such a case, and to
Furthermore, it is an object of the present invention to provide a CRT display device that can display the screen divided into two or more in the horizontal direction, thereby making effective use of the screen.

According to the present invention, at least a storage device in which display data is stored, a processing device, a direct memory access control unit that directly controls access to the storage device, and a CRT that controls the display screen of a CRT.
a control section, a distributor is provided in a direct memory access request signal circuit from the CRT control section to the direct memory access control section, and a distributor is provided in an interrupt signal circuit from the direct memory access control section to the processing device. /n counter (n≧2)
A CRT display device is provided, wherein the count output of the 1/n counter controls the output of the distributor, and the full count output of the 1/n counter is used as an interrupt signal to the processing device. It will be done.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. This CRT display device includes at least a memory device (MEM) 1 into which display data is stored, a processing device (CPU) 2 that controls the entire device, and an n-channel direct memory access (DMA) controller that directly controls access to the memory device 1. 3. CRT control unit 4 that controls the display screen of CRT 5, the MEM 1, CPU 2, DMA control unit 3, and
Address and control bus 8 and data bus 9 connected to CRT control unit 4, CRT control unit 4
A distributor 6 provided in the DMA request signal circuit from to the DMA control unit 3, and from the DMA control unit 3 to the CPU
2 is provided in the interrupt signal circuit to 2, and further includes a 1/n counter 7 that controls the output of the distributor.

DMA from the CRT control unit 4 to the DMA control unit 3
Upon issuing a request, the DMA control unit 3 directly accesses the MEM 1 and sends one line of display data to the data register in the CRT control unit 4. The CRT control unit 4 converts it into a video signal according to the display timing, and converts it into a video signal according to the display timing.
Send the video signal and synchronization signal to 5.

Before the CRT control unit 4 starts display operation,
DMA for n channels from CPU 2 to DMA control unit 3
The address of MEM1 and the number of transferred data to be displayed in n divisions on the first line of the display screen are set in the address register and transfer number counter, respectively.

Next, when the CPU 2 instructs the CRT control unit 4 to start the display operation, the CRT control unit 4
In order to receive the data to be displayed on the first row into the data register, a DMA request is issued to the DMA control section 3 via the distributor 6 at a timing before the data is displayed on the first row. As a result, the DMA control unit 3 issues a hold request to the CPU 2. If the CPU 2 gives permission, it issues a hold acknowledge signal to the DMA control unit 3, and the CPU 2 stops its operation and relinquishes exclusive rights to the address and control bus 8 and data bus 9. The DMA control unit 3 has exclusive rights to the address bus, control bus 8, and data bus 9.

The DMA control unit 3 reads data from the memory address set in the DMA address register of the first channel of n channels, and outputs the data to the CRT.
The number of data specified in the data register of the control unit 4 is transferred by DMA. This is 1 of the display screen of CRT5
1/n of the row will be sent.

When the DMA transfer is completed, the DMA end signal becomes 1/
It is sent to n counter 7. At this time, no signal is sent from the 1/n counter 7 to the CPU 2. This is because the 1/n counter 7 has not reached a full count. However, since the 1/n counter 7 counts 1, its count output is sent to the distributor 6.

FIG. 2 is a circuit diagram showing an example of the distributor 6.
In this example, when n=3, the number of inputs from the CRT control unit 4 to the distributor 6 is one;
There are three outputs from the DMA controller 3. The distributor 6 has three AND circuits 61, 62, and 63, and the output from the CRT control unit 4 is connected in parallel to the input thereof, and the signal from the 1/n counter 7 is input to the AND circuit 61. A signal "0" designating the register of the first channel is added, a signal "1" designating the register of the second channel is added to the AND circuit 62, and a signal "2" designating the register of the third channel is added to the AND circuit 63. It will be done.

Therefore, the output of 1/n counter 7 is "0"
In this case, the DMA request signal from the CRT control section 4 reaches the DMA control section 3 via the AND circuit 61 of the distributor 6. Also, when the 1/n counter 7 counts 1, "1" is sent from the 1/n counter 7, and when it counts 2 more, "2" is sent to the distributor 6, and the DMA request signal from the CRT control unit 4 is sent to the distributor 6. The signal is then sent to the DMA control unit 3 via AND circuits 62 and 63.

Returning to the explanation of FIG. 1, since the data register of the CRT control unit 4 is not full for one row, DMA requests continue to be issued. The DMA request is sent to the DMA control unit 3 via the AND circuit 62 of the distributor 6.
is input to. The DMA control unit 3 controls the second channel.
Data is transferred from the memory address set in the DMA address register to the data register of the CRT control unit 4, and a DMA transfer end signal is sent to the 1/n counter 7.

If the 1/n counter 7 does not have a full count, the DMA control section 3 continues DMA transfer in response to the next DMA transfer request from the CRT control section 4 until the data register of the CRT control section 4 becomes full. 1/n
When the counter 7 reaches a full count, the transfer of one line of display data to the data register of the CRT control unit 4 is completed, and an interrupt signal is generated to the CPU 2.

Upon receiving the interrupt signal, the CPU 2 sets the address of the MEM 1 and the number of data to be displayed on the second line of the display screen in the DMA address register and transfer number counter of each channel of the DMA control unit 3. By repeating the above operations,
The CRT5 can be divided horizontally into n parts for display.

FIG. 3 is a time chart of the main part of FIG. 1 when n=3. FIG. 3A shows a DMA request signal sent from the CRT control unit 4 to the DMA control unit 3, which is on between times _t1 and _t2 , _t4 and _t5 , and _t7 and _t8 , and is on at other times. is off. Figure 3B shows that the DMA control unit 3 uses the MEM in response to the DMA request signal in Figure 3A.
This shows a state in which DMA transfer is performed from 1 to the data register of the CRT control unit 4. FIG. 3C shows a DMA transfer end signal sent from the DMA control unit 3 to the 1/n counter 7, which is generated at times t ₂ , t ₅ and t ₈ when the DMA transfer in FIG. 3B ends. Figure 3 D is 1/n
The state in which the count output of the counter 7 changes is shown. At times t 3 , t ₆ and t ₉ when the DMA transfer end signal in FIG. _3C disappears, the count output of the 1/n counter 7 increases by one. Then, it returns to "0" again at time _t9 , and the same cycle is repeated thereafter.
Figure 3 (e) is a signal sent from the 1/n counter 7 to the CPU 2, and the DMA transfer end signal in Figure 3 (c) is 3.
When the count is reached, the 1/n counter 7 reaches a full count and generates an interrupt signal to the CPU 2 at time _t8 .

As is clear from the above explanation, the features of the present invention are
A distributor 6 is provided in the DMA request signal circuit from the CRT control section 4 to the DMA control section 3, and a 1/n counter 7 is provided in the interrupt signal circuit from the DMA control section 3 to the CPU 2. The output of the distributor 6 is controlled by the count output, and 1/n
By using the full count output of the counter 7 as an interrupt signal to the CPU 2, the CRT screen can be divided into n parts in the horizontal direction and displayed.

FIG. 4 is a diagram showing the position addresses of the display screen of the CRT 5, illustrating a screen with 24 lines of 80 characters per line. Also, Figure 5 corresponds to Figure 4.
This is an example of memory allocation for MEM1, and numbers from 0 to 1919 represent one page.

FIG. 6 shows a first display example of the CRT5. 6th
Figure A shows the memory contents of MEM1, from page 0 to page 2, and this is an example in which the shaded portions P ₁ , Q ₁ , and R ₁ are extracted. 6th
Figure B shows the CRT5 screen displayed in the shaded area of Figure 6 A, and Figure 6 C shows the state in which the CRT5 screen is displayed in the shaded area of Figure 6 A.
The table contents of CPU2 indicate the start address of MEM1 to be displayed on each line of the display screen.

FIG. 7 shows a second display example of the CRT5. 7th
Figure A differs from Figure 6 B only in _P2 . FIG. 7B shows the table contents of the CPU 2 in the case of FIG. 7B. As is clear from FIG. 7B, P ₂ in FIG. 7A indicates a state in which P ₁ in FIG. 6C is shifted by two lines. In this way, the display can be shifted depending on the contents of the table of the CPU 2, and the screen can also be divided.

FIG. 8 shows a third display example of the CRT5. 6th
Figure 7 and Figure 7 are examples of dividing 80 bytes per line into two equal parts, 40 bytes each on the left and right.
The figure shows that it is also possible to divide the left and right parts into unequal parts. FIG. 8A shows an example of the memory contents of MEM1, in which the shaded sentences P ₃ , Q ₃ , and R ₃ are extracted. In Figure 8 A, P ₃ and Q ₃ are 60 bytes, and R ₃ is
It is divided into 20 bytes in a 3:1 ratio. FIG. 8(b) shows a state in which the screen is displayed in the shaded area of FIG. 8(a), and FIG. 8(c) shows the contents of the table of the CPU 2 at this time.

FIG. 9 shows a fourth display example of the CRT5. 9th
Figure A is an example of the memory contents of MEM1, and the shaded area
This is an example of extracting P ₄ , Q ₄ , and R ₄ . FIG. 9A is an example in which the screen is divided in the horizontal direction at an arbitrary ratio and an arbitrary portion is extracted from three pages in the vertical direction. 9B shows the screen displayed in the shaded area of FIG. 9A, and FIG. 9C shows the contents of the table of the CPU 2 at this time.

As explained above, according to the CRT display device of the present invention, the CRT display screen can be arbitrarily divided and displayed in the horizontal direction, so various data can be displayed in parallel on the CRT screen. This allows you to use the screen effectively.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of the distributor of Fig. 1, and Fig. 3 shows the main parts of the embodiment shown in Fig. 1. Figure 4 is a diagram showing the position address of the CRT display screen, Figure 5 is a diagram showing an example of memory allocation of the storage device, Figure 6 is the first display example of the CRT, and A is the memory. Figure 7 shows the memory contents of the device, B shows the display screen status of the CRT, C shows the table contents of the processing device, and Figure 7 shows the CRT.
Figure 8 and Figure 9 are the third and fourth display examples of the CRT. A is a diagram showing the memory contents of the storage device, B is a diagram showing the display screen state of the CRT, and C is a diagram showing the table contents of the processing device. 1... Storage device (MEM), 2... Processing unit (CPU), 3... Direct access (DMA) control unit,
4...CRT control unit, 5...CRT, 6...Distributor, 7...1/n counter, 8...Address and control bus, 9...Data bus.

Claims (1)

[Claims] 1. A storage device in which at least display data is stored, a processing device, and a direct memory access control unit that directly controls access to the storage device;
It has a CRT control unit that controls the CRT display screen,
A distributor is provided in the direct memory access request signal circuit from the CRT control section to the direct memory access control section, and a 1/n counter (n≧ 2), the output of the distributor is controlled by the counter output of the 1/n counter, and the full count output of the 1/n counter is used as an interrupt signal to the processing device. .