JPS5739439A - Input-output controller - Google Patents

Input-output controller

Info

Publication number
JPS5739439A
JPS5739439A JP11265680A JP11265680A JPS5739439A JP S5739439 A JPS5739439 A JP S5739439A JP 11265680 A JP11265680 A JP 11265680A JP 11265680 A JP11265680 A JP 11265680A JP S5739439 A JPS5739439 A JP S5739439A
Authority
JP
Japan
Prior art keywords
control part
dma
bus
local
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11265680A
Other languages
Japanese (ja)
Inventor
Ichiro Ohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11265680A priority Critical patent/JPS5739439A/en
Publication of JPS5739439A publication Critical patent/JPS5739439A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To execute a DMA transfer between an input/output buffer memory and an input/output control part, by use of a local bus line which is different from a main bus line being under control of a microprocessor. CONSTITUTION:When a CRT control part 6 starts a display control, it executes a DMA request to a local DMA control part 13 as a transfer request of display information of the next line, simultaneously separates a picture buffer memory 12, the CRT control part 6 and the local DMA control part 13 from a main bus, and connects them to a local bus, by controling the first bus changeover control part 9, the second bus changeover control part 10 and the third bus changeover control part 11. When the local DMA control part 13 receives the DMA request, it gives a DMA permission and starts DMA transfer control by use of the local bus. Display information stored in a picture buffer memory 12 is read out in order, and is displayed on a display screen of a CRT display part 8.
JP11265680A 1980-08-18 1980-08-18 Input-output controller Pending JPS5739439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11265680A JPS5739439A (en) 1980-08-18 1980-08-18 Input-output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11265680A JPS5739439A (en) 1980-08-18 1980-08-18 Input-output controller

Publications (1)

Publication Number Publication Date
JPS5739439A true JPS5739439A (en) 1982-03-04

Family

ID=14592183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11265680A Pending JPS5739439A (en) 1980-08-18 1980-08-18 Input-output controller

Country Status (1)

Country Link
JP (1) JPS5739439A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201463A (en) * 1984-03-27 1985-10-11 Oki Electric Ind Co Ltd Dma data transfer system
JPH07302251A (en) * 1987-03-13 1995-11-14 Texas Instr Inc <Ti> Data processor provided with plurality of on-chip memory buses
JP2002055941A (en) * 2000-07-17 2002-02-20 Arm Ltd Data processor
US6654836B1 (en) 2000-06-20 2003-11-25 International Business Machines Corporation Dual master device for improved utilization of a processor local bus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201463A (en) * 1984-03-27 1985-10-11 Oki Electric Ind Co Ltd Dma data transfer system
JPH07302251A (en) * 1987-03-13 1995-11-14 Texas Instr Inc <Ti> Data processor provided with plurality of on-chip memory buses
US6654836B1 (en) 2000-06-20 2003-11-25 International Business Machines Corporation Dual master device for improved utilization of a processor local bus
JP2002055941A (en) * 2000-07-17 2002-02-20 Arm Ltd Data processor

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