JPS576921A - Loading system of initial program - Google Patents

Loading system of initial program

Info

Publication number
JPS576921A
JPS576921A JP7988280A JP7988280A JPS576921A JP S576921 A JPS576921 A JP S576921A JP 7988280 A JP7988280 A JP 7988280A JP 7988280 A JP7988280 A JP 7988280A JP S576921 A JPS576921 A JP S576921A
Authority
JP
Japan
Prior art keywords
address
region
initial program
length
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7988280A
Other languages
Japanese (ja)
Other versions
JPS596407B2 (en
Inventor
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55079882A priority Critical patent/JPS596407B2/en
Publication of JPS576921A publication Critical patent/JPS576921A/en
Publication of JPS596407B2 publication Critical patent/JPS596407B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize a variable loading of an initial program, by providing a WCR when loading the initial program into an optional address of a memory in a channel with a prescribed length and then carrying out a process by the contents of the WCR and through an MPU. CONSTITUTION:An initial program in the region of an address A having a length L in a main memory 2 is loaded into the region of an address B of a RAM13 of the channel CMC3 by a command of a CPU1. In this case, the address B region of a RAM13, the address A region of the memory 2 and the number of bytes showing the length L are written along with the type of command into a write control register WCR15. These contents are decoded by a microprocessor MPU11, and then a command is indicated to start a DMA control circuit 19. Then the address A and the length L of the memory 2 are loaded into the address B of the RAM13 under the control of the loading program in a ROM12.
JP55079882A 1980-06-13 1980-06-13 Initial program loading method Expired JPS596407B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55079882A JPS596407B2 (en) 1980-06-13 1980-06-13 Initial program loading method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55079882A JPS596407B2 (en) 1980-06-13 1980-06-13 Initial program loading method

Publications (2)

Publication Number Publication Date
JPS576921A true JPS576921A (en) 1982-01-13
JPS596407B2 JPS596407B2 (en) 1984-02-10

Family

ID=13702611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55079882A Expired JPS596407B2 (en) 1980-06-13 1980-06-13 Initial program loading method

Country Status (1)

Country Link
JP (1) JPS596407B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501762A (en) * 1982-09-30 1984-10-18 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Direct memory access interface device
JPS61262955A (en) * 1985-05-17 1986-11-20 Fujitsu Ltd Buffer control system for communication controlling equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501762A (en) * 1982-09-30 1984-10-18 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Direct memory access interface device
JPH0420497B2 (en) * 1982-09-30 1992-04-03 Ei Teii Ando Teii Tekunorojiizu Inc
JPS61262955A (en) * 1985-05-17 1986-11-20 Fujitsu Ltd Buffer control system for communication controlling equipment

Also Published As

Publication number Publication date
JPS596407B2 (en) 1984-02-10

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