JPS57174723A - Bus load controlling system - Google Patents

Bus load controlling system

Info

Publication number
JPS57174723A
JPS57174723A JP56059856A JP5985681A JPS57174723A JP S57174723 A JPS57174723 A JP S57174723A JP 56059856 A JP56059856 A JP 56059856A JP 5985681 A JP5985681 A JP 5985681A JP S57174723 A JPS57174723 A JP S57174723A
Authority
JP
Japan
Prior art keywords
bus
data
control circuit
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56059856A
Other languages
Japanese (ja)
Inventor
Matsuaki Terada
Takaaki Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56059856A priority Critical patent/JPS57174723A/en
Publication of JPS57174723A publication Critical patent/JPS57174723A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Abstract

PURPOSE:To reduce the peak load of a bus, by monitoring the bus load through an input/output device and varying the using frequency of the bus in accordance with the bus load. CONSTITUTION:The data to be fed to a CPU1 from an input/output device 3 is prepared at a buffer memory 11. A DMA control circuit DMAC9 delivers a bus occupying request REQ2-3 to a bus occupancy control circuit BA4 and a DMA control circuit 1-2. The circuit BA4 sends back ACK2-4 in case when the bus 2 is not in use. Then the circuit DMAC9 reads the data by which the address of a counter 10 is transferred to an address bus 2-1 out of the memory 11 via a control circuit MCONT12 and then delivers it to a data bus 2-2. Thereafter, a data fetch request SRVI2-5 is delivered. The circuit 1-2 writes the data on the bus 2-2 into a memory 1-1. Then SRVO2-10 is delivered after the fetching of data is over.
JP56059856A 1981-04-22 1981-04-22 Bus load controlling system Pending JPS57174723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56059856A JPS57174723A (en) 1981-04-22 1981-04-22 Bus load controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56059856A JPS57174723A (en) 1981-04-22 1981-04-22 Bus load controlling system

Publications (1)

Publication Number Publication Date
JPS57174723A true JPS57174723A (en) 1982-10-27

Family

ID=13125237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56059856A Pending JPS57174723A (en) 1981-04-22 1981-04-22 Bus load controlling system

Country Status (1)

Country Link
JP (1) JPS57174723A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62100855A (en) * 1985-10-28 1987-05-11 Omron Tateisi Electronics Co Controller for dma transfer
US7536490B2 (en) * 2006-07-20 2009-05-19 Via Technologies, Inc. Method for link bandwidth management

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62100855A (en) * 1985-10-28 1987-05-11 Omron Tateisi Electronics Co Controller for dma transfer
US7536490B2 (en) * 2006-07-20 2009-05-19 Via Technologies, Inc. Method for link bandwidth management

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