JPS6250941A - Micro computer device - Google Patents

Abstract

PURPOSE:To improve the reliability of a system by using the undefined instruction of a CPU and operating the setting of a register to select the memory area of a limited memory area or above as a pseudo instruction of the CPU. CONSTITUTION:When the instruction is fetched by a CPU, the instruction code is outputted from a memory 1, and the code is inputted to a memory element 4. To the element 4, the information corresponding to the inputted instruction code, consequently, the information to show whether or not the information is the instruction defined by the CPU 2 is outputted. When the information is a defined instruction, a buffer 5 is controlled by a control circuit 7, the instruction code from the memory 1 is transmitted to the CPU 2, in case of the underfined instruction the buffer 5 is controlled by the circuit 7, the NOP instruction code not to give the influence to the CPU 2 is transmitted to the CPU 2 and a register 6 is set corresponding to the pseudo instruction. By the contents of the register 6, another area in the memory capacity of the memory area or above limited by the CPU 2 can be driven.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a micro combinator (1), particularly 8).
The present invention relates to a microcomputer device that uses a CPU and has a large capacity memory.

[Background of the invention]

In conventional devices, a bank switching method was used for memory expansion, but multiple memory areas that were the same as a part of one basic memory area were arranged, and the basic memory area was fragmented. It took time to switch. ("Transistor Technology" January 1985 issue, p. 422) [Object of the Invention] An object of the present invention is to increase the total access area of the limited memory of the CPU with a simple circuit configuration.

[Summary of the invention]

In the case of the bank switching method, it takes time to set the target memory space. Therefore, by using an undefined CPU instruction, register setting for selecting a memory area larger than the limited memory area is operated as a CPU pseudo-instruction.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Memory 1 is 8 bits) Maximum memory area of CPU 2 is 64K
It has a capacity that is an integral multiple of B. The decoder 3 includes a memory element 4 that determines whether the instruction fetched from the memory 1 is a pseudo-instruction, and an output from the memory element 4 that determines whether or not the instruction fetched from the memory 1 is a pseudo-instruction.
A buffer 5 that selects one of the P instruction codes and sends it to the CPU 2, and a corresponding memory area in the memory 1 according to the pseudo-instruction? It is composed of a register 6 for setting and a control circuit 7.

Next, the operation will be explained. When the CPU 2 etches an instruction, the instruction code is output from the memory 7, and the instruction code is not transmitted to the CPU 2 by the buffer 5, but is input to the storage element 4. Information corresponding to the input instruction code, that is, information indicating whether the instruction has been executed by the CPU 2 is output to the memory element 4 . With this information,
If it is a definition command, the buffer 5 is sent from the control circuit 7.
and transmits the instruction code from memory 1 to KCPU2. If it is an undefined instruction, the control circuit 7 controls the buffer 5, transmits a NOP instruction code that does not affect the CPU 2 to the CPU 2, and at the same time sets the register 6 in accordance with the pseudo instruction. From now on 1° register 6
A different area in the memory 1 is allocated to the CPU depending on the contents of the . As described above, by using an instruction food not defined by the CPU 2 as an instruction for setting the register 6, it is possible to drive a memory capacity larger than the memory area limited by the CPU 2.

Note that the information in the storage element 4 is not only the above information, but if an undefined instruction code other than a pseudo-instruction is fetched by the CPU 2, this is considered to be an abnormal operation of the system, so the CPU 2 is notified of the occurrence of the abnormality. It is also possible.

〔Effect of the invention〕

According to the invention, a CPU'U with limited memory capacity
The effect of being able to access a larger memory area without overhead in a microcomputer device having
It also has the effect of improving the reliability of the system because it can detect abnormal operations in the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Memory 2...CPU 3...Decoder 4...Memory element 5...Buffer 6...Register 7...Control circuit

Claims (1)

[Scope of Claims] 1. A microcomputer device having a memo larger than the area that can be driven by the central processing unit, characterized in that the central processing unit section is provided with a decoding circuit for decoding defined and undefined instructions. Microcomputer equipment. 2. A microcomputer device according to claim 1, wherein the decoder circuit has a memory element. 3. The memory has an area that is an integral multiple of the maximum drive area of the central processing unit, and the decoder circuit has one or more registers indicating one of the memories divided into the maximum drive area of the CPU. A microcomputer device according to claim 1, characterized in that: