JPH0660012A - Dma controller - Google Patents

Abstract

PURPOSE:To shorten a total channel switching time. CONSTITUTION:When one of DMA request signals 101 corresponding to plural channels becomes active, a DMA transfer start signal 103 is outputted, a bus cycle sequencer block 19 outputs a DMA transfer permission signal 109 corresponding to the DMA request channel, and a transfer frequency block 1 calculates the number of transfer bytes of data stored in a mode register 7. The DMA transfer request signal 101 is encoded and request data are inputted to a comparator 16 together with one of transfer start and interruption state signals 105 and 106; and the contents of a transfer byte storage register 2 and the number of transfer bytes generated by a constant generation block 9 are inputted to a comparator 17 simultaneously, and both the inputs are inputted to an AND circuit 18. When the value of a transfer byte storage register 2 is equal to or less than the value of the constant generation block 9, the comparator 17 generates a '0'-level output, the output of the comparator 16 is masked, and channel switching when the the remaining transfer bytes are small is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly to a DMA controller for transferring data between a memory and an I / O device.

[0002]

2. Description of the Related Art An internal block diagram of an example of a conventional DMA controller of this type is shown in FIG. Also, FIG.
(A), (b), (c), (d), (e), (f),
(G), (h), (i) and (j) are timing charts at the time of channel switching in the conventional example. The operation of the conventional example will be described below with reference to FIGS. 4 and 5.

As shown in FIG. 4, this conventional example uses DM.
A Transfer byte number is set before the transfer is started, and when the transfer is started after that, the remaining transfer byte number is updated at any time. Transfer byte storage register 2, adder / subtractor for updating the contents of the transfer byte storage register 2 5, the transfer count block 1 including the input buffers 3 and 4 for the adder / subtractor 5
A transfer mode block 6 including a transfer mode of a transfer channel, a mode register 7 for designating an I / O port width and a bus width, and a decoder 8 for decoding the contents of the mode register, and a decoder during a DMA transfer. 8
Internal ROM1 based on the result decoded by
Constant generation block 9 for generating the constant stored in 0
And a DMA request acceptance block 12 that accepts a DMA request signal 101 from an external requester and outputs a DMA transfer start signal 103, and a DMA request acceptance block 1
A priority encoder 13 for encoding the output of 2 and an OR circuit 14 for outputting the logical sum of the transfer start state signal 105 and the transfer interruption state signal 106;
Input the clock signal 102 from the outside to the CLK terminal,
The output of the OR circuit 14 is input to the S terminal and the output of the priority encoder 13 is input to the D terminal, and the output of the priority encoder 13 and the output of the D flip-flop 15 are compared, When both outputs are not equal, a comparator 16 which outputs a "1" level channel switching signal 104, the DMA transfer start signal 103 and the channel switching signal 104, and a bus release signal 107 from the outside are input. hand,
The transfer start state signal 105, the transfer interruption state signal 106, the bus release request signal 108 and the DMA
A bus cycle sequencer block 19 which outputs a transfer permission signal and controls a bus cycle is configured.

In this conventional example, during DMA transfer,
During the DMA transfer of a certain channel, when the DMA request signal 101 of another higher priority channel becomes active, the DMA transfer of the certain channel that was executed before that is unconditionally interrupted and the priority is given. It is switched to the DMA transfer of the higher order channel. After the DMA transfer of the higher priority channel is completed, the remaining DMA transfer of the interrupted channel is executed. In the conventional example, the DMA request signal 101 input to the DMA request receiving block 12 is omitted in FIG. 4, but four types of DMA requests corresponding to channels 0 to 3 input in parallel are provided. When a DMA request signal corresponding to one of the DMA request signals 101 is activated, the DMA acceptance block 12 starts a DMA transfer corresponding to the DMA request signal corresponding to the channel. The signal 103 is output as an active signal. DM
When the A transfer start signal 103 becomes active, the bus cycle sequencer block 19 performs bus cycle control, and the bus release request signal 108 is output as an active signal. In response to the active output of the bus release request signal 108, the DMA transfer permission signal 109 corresponding to the channel for which the DMA transfer request is issued becomes active and is output via the bus release signal 107 which is input in response from the outside. Then, it is indicated to the request source that the DMA transfer has been accepted.

On the other hand, the DMA transfer start signal 1
03 is the input buffer 3 included in the transfer count block 1
Are also input to the DMA transfer start signal 10
3 becomes active, the transfer count block 1 and the transfer mode block 6 output and update the address of the channel for which the DMA transfer is requested, and store the I / O width and bus width stored in the mode register 7. And data indicating the transfer direction are decoded by the decoder 8 and input to the constant generation block 9. The constant generation block 9 is composed of an internal ROM 10, and the ROM 1 is supplied via a decode output input from the control register 6.
The constant stored in 0 is read and input to the input buffer 4 included in the transfer count block 1. In the transfer count block 1, the number of transfer bytes stored in advance in the transfer byte storage register 2 is subtracted by the adder / subtractor 5 by the constant, and the remaining number of transfer bytes is calculated.

The DMA transfer request signal received by the DMA request receiving block 12 is encoded by the priority encoder 13. In this case, in the priority encoder 13, channel 0
The channel with the highest priority is selected from the DMA transfer requests 3 to 3, and the priority here is in the order of channels 0, 1, 2, 3. As for the encoded request data, one of the transfer start state signal 105 and the transfer stop state signal 106 generated by the bus cycle sequencer block 19 becomes “1” level via the OR circuit 14. At times, a set condition is set for the D flip-flop 15, and the output of the priority encoder 13 at that time becomes one input to the comparator 16. The output of the priority encoder 13 for each clock of the clock signal 102 is
It becomes the other input to the comparator 16, both of these inputs are compared in the comparator 16, and when they are not equal, the channel switching signal 1 output from the comparator 16
04 is output as "1" level, and the bus cycle
Input to sequence block 19. The fact that the channel switching signal 104 is output as a "1" level means that a DMA transfer request having a higher priority has come. In the bus cycle sequencer block 19, the bus release request signal is output. 108 and the DMA transfer permission signal 109 of the channels 0 to 3 are made inactive to interrupt the DMA transfer of the channel being executed and switch to the DMA transfer of the channel having the higher priority.

5 (a), (b), (c), (d),
(E), (f), (g), (h), (i) and (j)
FIG. 4 is a timing diagram showing an operation when a DMA transfer request for channel 0 is input during a DMA transfer for channel 1, as an example.

First, when the DMA request signal 101 corresponding to channel 1 becomes active, the bus release request signal 10
8 becomes active and the external bus master is requested to release the bus. When the bus is released in response to the active bus release request signal 108, the bus release signal 107 is input as an active signal, and the DMA transfer permission signal 109 is activated to the request source so that the transfer request is issued. It is communicated that permission has been granted. When the DMA request signal 101 corresponding to the channel 0 becomes active during the DMA transfer in the channel 1, the bus release request signal 108 and the channel 1 are assigned to the channel release request signal 108 because the channel 0 has a higher priority than the channel 1. The corresponding DMA transfer permission signal 109 is made inactive, and the channel switching operation is unconditionally started. After that, the bus release request signal 108 is activated and the bus release signal 1 is sent in order to perform the DMA transfer of the channel 0.
When 07 becomes active, DM corresponding to channel 0
A transfer permission signal 109 is activated, and channel 0
DMA transfer is executed. After the completion of the DMA transfer in the channel 0, the bus release request signal 10 is again sent for the remaining DMA transfer in the channel 1.
When 8 is activated and the bus release signal 107 is input as an active signal, the DM corresponding to channel 1
The A transfer permission signal 109 is activated, and the remaining DMA transfer in the channel 1 is performed.

As is clear from the above description of operation, D
If the MA transfer channel is unconditionally executed, DM
In the channel 1 in which the A transfer is suspended, the bus release request signal 108 is activated and the bus release signal 107 is set.
Wait operation (hereinafter, such a wait operation is referred to as overhead) for waiting for the activation of the DMA is required in order to execute the remaining DMA transfer. In this case, if the remaining number of DMA transfers in channel 1 is small, the overhead causes the DMA transfer time to be deadly required.

[0010]

DISCLOSURE OF THE INVENTION Conventional DMA described above
In the controller, when switching is performed to a channel having a higher priority than a channel having a lower priority, the DMA transfer state of the channel having a lower priority is unconditionally switched. If channel switching occurs when the number of remaining transfer bytes is small, a bus release request is output to the bus master again after the DMA transfer in the higher priority channel ends because of the remaining several bytes. As a result, the overhead of waiting for the bus to be released is unnecessarily increased, and the DMA transfer efficiency in the low priority channel is significantly deteriorated.

[0011]

SUMMARY OF THE INVENTION A DMA controller of the present invention receives a data transfer request from the outside and performs a DM data transfer in advance in a DMA controller that transfers DMA data.
A transfer byte number of A data is set, the transfer byte storage register in which the remaining byte number is updated with the start of transfer, an adder / subtractor for updating the storage content of the transfer byte storage register, and a DMA A mode register for designating a transfer mode of a channel for data transfer, an I / O port width and a bus width, a decoder for decoding the contents of the mode register, and a DMA data transfer receiving an output of the decoder, A constant generation block that outputs a predetermined constant stored in advance and a data transfer request signal for each channel from the outside are received, and D
DMA for outputting MA request and DMA transfer start signal
A request receiving block, a priority encoder that encodes the output of the DMA request receiving block, and a specific level signal that is set at the S terminal, the output of the priority encoder is input to the D terminal, and an external clock signal is input. A D flip-flop that operates by inputting a signal to the CLK terminal, the output of the priority encoder, and the output of the D flip-flop are compared, and a "1" level is output when these two outputs are not equal. Comparing the output of the transfer byte storage register with the output of the constant generation block, and the output of the transfer byte storage register is
When it is equal to or less than the output of the constant generation block, it outputs a "0" level, and when the output of the transfer byte storage register is larger than the output of the constant generation block, it outputs "1". A second comparator that outputs a level and an AND circuit that takes a logical product of the outputs of the first and second comparators and outputs as a channel switching signal, and a DMA transfer output from the DMA request acceptance block In response to the input of the start signal and the channel switching signal output from the AND circuit, a bus release request signal is output, and a bus release signal is received from the outside to permit DMA transfer to the outside. A bus cycle sequencer block that outputs a signal and internally outputs a transfer start state signal or a transfer suspend state signal The ORs the transfer start state signal and said transfer interrupt state signal, said a particular level signals, an OR circuit for outputting the S terminal of the D flip-flop, and a comprising a.

The storage means of the constant generation block may be a ROM or a register.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. 3 (a), (b), (c),
(D), (e), (f), (g), (h), (i) and (j) are timing charts at the time of channel switching in the present embodiment. The operation of this embodiment will be described below with reference to FIGS. 1 and 3.

As shown in FIG. 1, this embodiment has a transfer count block 1 including a transfer byte storage register 2, input buffers 3 and 4, and an adder / subtractor 5, and a transfer mode including a mode register 7 and a decoder 8.・ Block 6
A constant generation block 9 including a ROM 10 inside, and a DMA
DMA acceptance block 11 including request acceptance block 12, priority encoder 13, OR circuit 14, D flip-flop 15, comparators 16 and 17, and AND circuit 18, and bus cycle sequencer block 1
9 and 9.

In FIG. 1, when the DMA request signal corresponding to any one of the DMA request signals 101 corresponding to channels 0, 1, 2, 3 becomes active, DM
The A request acceptance block 12 outputs the DMA transfer start signal 103 as an active signal, and the bus cycle sequencer block 19 and the data register 1
Are input to the input buffers 3 and 4 included in. The bus cycle sequencer block 19 receives the active DMA transfer start signal 103 and starts control of the bus cycle. As a result, the bus release request signal 108 is output as an active signal and sent to the external bus master. When a bus release signal 107 is input as a response from the bus master, the DMA transfer permission signal 109 corresponding to the channel for which the DMA request is issued is output as an active signal, and the request source accepts the DMA transfer. What is done is transmitted.

In the transfer count block 1, the input buffers 3 and 4 are activated in response to the active DMA transfer start signal 103, and the I / O width, bus width and transfer stored in the mode register 7 are transferred. The data indicating the direction is decoded by the decoder 8 and the number of remaining transfer bytes is calculated.

The DMA transfer request signal received by the DMA request receiving block 12 is encoded by the priority encoder 13. In this case, in the priority encoder 13, channel 0
The highest priority channel is selected from the DMA transfer requests of 3 to 3, and the priority order here is the order of channels 0, 1, 2, 3 as in the case of the above-mentioned conventional example. The encoded request data includes a transfer start state signal 105 and a transfer interrupt state signal 106 generated by the bus cycle sequencer block 19.
When either one of the signals becomes the "1" level via the OR circuit 14, the set condition for the D flip-flop 15 is established, and the priority encoder 13 at that time is set.
Is output to one input terminal of the comparator 16. Then, the output of the priority encoder 13 for each clock of the clock signal 102 is input to the other input terminal of the comparator 16 and these two inputs are compared in the comparator 16, and when both are not equal, Comparator 16
The output channel switching signal 104 is output as “1” level and input to the AND circuit 18. At the same time, in the comparator 17, the contents of the transfer byte storage register 2 at that time and the decoded output of the mode register 7 are input to the constant generation block 9, and the remaining output from the constant generation block 9 is performed. The value of the number of transfer bytes is compared, and the comparison output is also the AN.
It is input to the D circuit 18. In this case, when the value of the content of the transfer byte storage register 2 is equal to or less than the output value from the constant generation block 9 in the comparator 17, the "0" level is output from the comparator 17 concerned. It When the output to the comparator 17 is at "0" level,
In the AND circuit 18, the output of the comparator 16 is masked. This makes it possible to suppress the level of the channel switching signal 104, and control so that the channel switching operation is not performed when there are few remaining transfer bytes.

3 (a), (b), (c), (d),
(E), (f), (g), (h), (i) and (j)
Shown by way of example is a timing chart showing the operation when a DMA transfer request for channel 0 is entered during DMA transfer on channel 1 in the present embodiment. Figure 3
First, the channel 1 DMA request signal 101 is
When it becomes active at time T ₁ (active level means “0” level in FIG. 3), the bus release request signal 108 output from the bus cycle sequencer block 19 becomes active, and the external bus master. A bus release request is issued to. When the bus is released by the bus release request signal 108, the bus release signal 107 externally input to the bus cycle sequencer block 19 becomes active. As a result, the DMA transfer permission signal 109 corresponding to channel 1 becomes active, and D corresponding to the channel 1 transfer request is sent.
The start of MA transfer is transmitted to the request source. And
As shown in FIG. 3, upon receiving the DMA transfer permission signal 109 corresponding to channel 1 (see FIG. 3E), the DMA transfer of channel 1 is started (see FIGS. 3B and 3C). ).

In this way, DM in channel 1
In the middle of the A transfer being executed, FIG.
, DM of channel 0 at time T ₂
When the A request signal 101 becomes active, although channel 0 has a higher priority than channel 1,
Since the number of remaining transfers in the DMA transfer of the channel 1 at this point is one, the channel switching signal 104 (see FIG. 3 (j)) is suppressed to the “0” level and the channel 1 is transferred as described above. DMA for channel 1
Transfer switching does not occur. And channel 1 DMA
After the transfer is completed, the bus release request signal 108 becomes active, the bus release signal 107 becomes active, and the DMA transfer permission signal 109 becomes active at time T ₃ for the DMA transfer of the channel 0. DMA transfer is started (FIGS. 3B and 3C).
reference). In the operation state shown in FIG. 3, the transfer time of 11 clocks is shortened as the time required to complete the DMA transfer of both channels 0 and 1 by the present embodiment as compared with the case of the conventional example. It is possible to do.

Next, FIG. 2 shows the second embodiment of the present invention.
It is a block diagram showing an example of. As shown in FIG. 1, in this embodiment, a transfer count block 1 including a transfer byte storage register 2, input buffers 3 and 4, and an adder / subtractor 5 is provided.
A transfer mode block 6 including a mode register 7 and a decoder 8, a constant generation block 9 including a register 20 therein, a DMA request acceptance block 12, a priority encoder 13, an OR circuit 14, a D flip-flop 15, Comparators 16 and 17 and AND circuit 1
DMA receiving block 11 including 8 bus cycles
A sequencer block 19 is provided. Figure 1
As can be seen by comparing FIG. 2 with FIG. 2, the difference from the first embodiment of the present embodiment is that a register is used instead of the ROM as the constant storage unit in the constant generation block 9. is there. Regarding the operation of this embodiment, D
The general operation other than the setting of a predetermined constant value in the register 20 inside the constant generation block 9 before the MA transfer is started is exactly the same as in the case of the first embodiment. , The description is omitted.

[0022]

As described above, according to the present invention, in the DMA transfer process of the low priority channel, even if the DMA transfer request of the high priority channel is issued, the low priority channel is processed in the low priority channel. When the remaining transfer count is small, the remaining transfer count value is determined, so that the DMA transfer time of each channel can be shortened as a whole without performing channel switching to a channel having a higher priority. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a timing diagram showing the operation of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a timing chart showing an operation in a conventional example.

[Explanation of symbols]

 1 Transfer Count Block 2 Transfer Byte Storage Register 3, 4 Input Buffer 5 Adder / Subtractor 6 Transfer Mode Block 7 Mode Register 8 Decoder 9 Constant Generation Block 10 ROM 11 DMA Accepting Block 12 DMA Request Accepting Block 13 Priority Encoder 14 OR Circuit 15 D flip-flop 16, 17 comparator 18 AND circuit 19 bus cycle sequencer block 20 register

Claims (3)

[Claims] 1. Upon receiving a data transfer request from the outside, D
In a DMA controller that performs MA data transfer, the transfer byte number of the DMA data is set in advance, and the transfer byte storage register in which the remaining byte number is updated with the start of transfer, and the storage content of the transfer byte storage register And adder / subtractor for updating the I / O
A mode register that specifies a port width and a bus width, a decoder that decodes the contents of the mode register, and a DMA data transfer that receives the output of the decoder,
A constant generation block that outputs a predetermined constant stored in advance; a DMA request reception block that receives an external data transfer request signal for each channel and outputs a DMA request for each channel and a DMA transfer start signal; A priority encoder that encodes the output of the DMA request acceptance block, and a specific level signal that is set by receiving on the S terminal, the output of the priority encoder is input to the D terminal, and an external clock signal is input to the CLK terminal. A first comparator that compares the output of the priority encoder and the output of the D flip-flop, and outputs a "1" level when these outputs are not equal. The output of the transfer byte storage register and the constant generation block. By comparing the output and the output of the transfer byte storage register is equal to the output of the constant generator block,
A second comparator which outputs a "0" level when it is less than or equal to it, and outputs a "1" level when the output of the transfer byte storage register is larger than the output of the constant generation block. And an AND circuit for taking the logical product of the outputs of the first and second comparators and outputting it as a channel switching signal, a DMA transfer start signal output from the DMA request acceptance block, and an output from the AND circuit. In response to the input of the channel switching signal, the bus release request signal is output, the external bus release signal is received, the DMA transfer permission signal is output to the outside, and the A bus cycle sequencer block that outputs a transfer start state signal or a transfer suspend state signal, ORs the transfer interrupt state signal, said a particular level signals, DMA controller, characterized in that it comprises an OR circuit for outputting the S terminal of the D flip-flop. 2. The storage means of the constant generation block is R
The DMA controller according to claim 1, which is configured by an OM. 3. The DMA controller according to claim 1, wherein the storage means of the constant generation block is composed of a register.