JP2017102524A - Semiconductor device, data processing system, and control method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of more appropriately performing compression and expansion.SOLUTION: A semiconductor device 100 includes an arithmetic module 110 and a memory control module 120. The arithmetic module 110 includes: an arithmetic unit 111 that executes arithmetic processing; and a compression circuit 11 that compresses data of an arithmetic processing result. The memory control module 120 includes: an access circuit 121 that writes compressed data to a memory and reads the written data from the memory; and an expansion circuit 21 that expands the data read from the memory and outputs the expanded data to the arithmetic module 110.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor device, a data processing system, and a semiconductor device control method, and more particularly, to a semiconductor device that performs arithmetic processing, a data processing system, and a semiconductor device control method.

  In recent years, semiconductor devices that perform various arithmetic processes such as image processing have been widely used. In such a semiconductor device, when data such as an image is written into and read from a memory, encoding and decoding according to a predetermined standard, compression and expansion, and the like are performed.

  As a technique related to compression and expansion, for example, Patent Document 1 is known. In Patent Document 1, in a data processing system in which an arithmetic unit and a storage device are connected via a bus, a compression circuit and an expansion circuit are provided between the bus and the arithmetic unit. The compression circuit compresses the processing result data of the computing unit and stores the compressed data in the storage device. The decompression circuit decompresses the compressed data read from the storage device, and processes the decompressed data with an arithmetic unit.

JP-A-10-27127

  In a semiconductor device that performs various arithmetic processes, it is desired to perform compression and expansion with an optimum configuration corresponding to the arithmetic processes. For this reason, in one embodiment, it is an object to perform compression and expansion more appropriately.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes an arithmetic module and a memory control module. The arithmetic module includes an arithmetic processing unit and a compression unit, and the memory control module includes an access unit and an expansion unit. In the arithmetic module, the arithmetic processing unit executes the arithmetic processing, and the compression unit compresses the data of the arithmetic processing result. In the memory control module, the access unit writes the compressed data to the memory, the written data is read from the memory, the decompression unit decompresses the data read from the memory, and the decompressed data is sent to the arithmetic module. Output.

  According to the one embodiment, it is possible to perform compression and expansion more appropriately.

1 is a configuration diagram illustrating a configuration example of a data processing system according to a basic example 1. FIG. It is a block diagram which shows the structural example of the data processing system which concerns on the basic example 2. FIG. 10 is a configuration diagram illustrating a configuration example of a data processing system according to a basic example 3. FIG. 1 is a configuration diagram illustrating a schematic configuration of a data processing system according to a first embodiment. 1 is a configuration diagram illustrating a schematic configuration of a data processing system according to a first embodiment. 1 is a configuration diagram illustrating a configuration example of a data processing system according to a first embodiment. FIG. 4 is a diagram for explaining output data of a computing unit according to the first embodiment. FIG. 4 is a diagram for explaining output data of a computing unit according to the first embodiment. 4 is a configuration diagram illustrating a configuration example of a buffer according to Embodiment 1. FIG. 7 is a diagram for explaining an input / output operation of a buffer according to Embodiment 1. FIG. 7 is a diagram for explaining an input / output operation of a buffer according to Embodiment 1. FIG. 7 is a diagram for explaining an input / output operation of a buffer according to Embodiment 1. FIG. 7 is a diagram for explaining an input / output operation of a buffer according to Embodiment 1. FIG. 7 is a diagram for explaining an input / output operation of a buffer according to Embodiment 1. FIG. It is a graph which shows the relationship between data length and memory access efficiency. 10 is a diagram for explaining compressed data according to Embodiment 2. FIG. FIG. 10 is a configuration diagram illustrating a configuration example of a memory control module according to a third embodiment. FIG. 10 is a diagram for explaining a memory access operation according to the third embodiment. FIG. 10 is a diagram for explaining compressed data according to a fourth embodiment. FIG. 10 is a diagram for explaining a memory access operation according to the fourth embodiment.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

(Basic examples 1 to 3)
First, basic examples 1 to 3 serving as the basis of the embodiment will be described. 1 to 3 show the configurations of data processing systems according to basic examples 1 to 3, respectively.

  As shown in FIGS. 1 to 3, data processing systems 91 to 93 according to basic examples 1 to 3 each include a semiconductor device (LSI) 901 to 903 and an SDRAM 200 that stores data of the semiconductor device. Each of the semiconductor devices 901 to 903 includes a plurality of arithmetic modules 110 (for example, 110_A to 110_C) and a memory control module 120. The arithmetic module 110 and the memory control module 120 are connected via a data bus 130, for example.

  The plurality of arithmetic modules 110 are arithmetic units that perform arithmetic processing, and are each provided with arithmetic units 111 (111_A to 111_C) in order to realize their functions. The memory control module 120 is a control unit that controls writing / reading of the SDRAM 200 in accordance with a request from the arithmetic module 110, and includes an access circuit 121 for realizing its function. The plurality of arithmetic units 111 store data in the SDRAM 200 and read data from the SDRAM 200 via the data bus 130 and the memory control module 120. The SDRAM 200 is an example of a memory that stores data of a semiconductor device, and may be another storage device.

  The semiconductor devices 901 to 903 further include a compression circuit 11 that compresses the data of the operation result, and a decompression circuit 21 that decompresses the compressed data. The semiconductor devices 901 to 903 are examples in which the arrangement of the compression circuit 11 and the expansion circuit 21 is different.

  As shown in FIG. 1, in the semiconductor device 901 of the basic example 1, the compression circuit 11 and the expansion circuit 21 are provided between the arithmetic module 110 and the data bus 130, and the compression circuit 11 and the expansion circuit 21 and the data bus are provided. 130 has a one-to-one relationship. As shown in FIG. 2, in the semiconductor device 902 of the basic example 2, the compression circuit 11 and the expansion circuit 21 are provided in the memory control module 120, and the compression circuit 11, the expansion circuit 21, and the memory control module 120 are provided. There is a one-to-one relationship.

  Each arithmetic unit 111 outputs output data corresponding to the characteristics of the arithmetic processing. In other words, the output data transfer start address position, the transfer length, and the data format (continuous or discrete) differ for each computing unit. When the compression circuit 11 and the expansion circuit 21 have a one-to-one relationship with the data bus 130 and the memory control module 120 as in the basic example 1 and the basic example 2, the compression circuit 11 outputs the outputs of all the arithmetic units 111. It needs to be compressed. If it does so, compression efficiency cannot be made high. In other words, since compression is performed by the same compression circuit regardless of the output characteristics of each computing unit, there is a problem that compression cannot be performed with a data structure suitable for compression, and compression efficiency is lowered.

  As shown in FIG. 3, in the semiconductor device 903 of Basic Example 3, the compression circuit 11 and the expansion circuit 21 are provided in each arithmetic module 110, and the compression circuit 11 and the expansion circuit 21, the arithmetic unit 111, Are in a one-to-one relationship. Even when the compression circuit 11 and the decompression circuit 21 are in one-to-one correspondence with each computing unit 111 as in the basic example 3, the compression efficiency cannot be increased. This is because when the data of the operation result is used in another arithmetic unit, the data must be compressed with a common data structure in order to be able to be decompressed by the other arithmetic unit. Then, since it cannot compress according to the output for every arithmetic unit, the same problem as the above occurs.

  In the configuration of Basic Example 3, the arithmetic unit 111_C to which compression is not applied also requires the decompression circuit 21_C in order to read the data compressed by the other arithmetic units 111. For this reason, since an expansion circuit is required for all the arithmetic units, there is a problem that the circuit area increases.

  Further, although an SDRAM or the like can be considered as a storage device, there is a problem that it is difficult to increase the transfer efficiency of the SDRAM because a continuous data structure is not obtained depending on the characteristics of data generated by the arithmetic unit 111.

(Embodiment 1)
The first embodiment will be described below with reference to the drawings.

<Outline of Embodiment 1>
FIG. 4 shows a schematic configuration of the data processing system according to the present embodiment. As shown in FIG. 4, the data processing system 1 according to the present embodiment includes a semiconductor device 100 and an SDRAM 200. The semiconductor device 100 according to the present embodiment includes a plurality of arithmetic modules 110 (for example, 110_A-110_C) and a memory control module 120 as in the first to third examples. The arithmetic module 110 includes an arithmetic unit 111 (111_A to 111_C). Further, some arithmetic modules 110 include a compression circuit 11 (for example, 11_A and 11_B). The memory control module 120 includes an access circuit 121, and further includes a decompression circuit 21. Note that, as shown in FIG. 5, the semiconductor device 100 according to the present embodiment may include at least the arithmetic module 110 and the memory control module 120 in the configuration of FIG. That is, at least the arithmetic module 110 includes an arithmetic unit (arithmetic processing unit) 111 that performs arithmetic processing, and a compression circuit (compressing unit) 11 that compresses data of the arithmetic processing result, and the memory control module 120 includes compressed data Is read into the SRDAM (memory) 200, the written data is read from the SDRAM 200, an access circuit (access unit) 121, the data read from the SDRAM 200 is decompressed, and the decompression circuit (output unit) outputs the decompressed data to the arithmetic module 110. (Extension part) 21 is provided.

  As described above, in the present embodiment, in the data processing system including the calculation unit (calculation module) and the memory control unit (memory control module), the calculation unit includes a compression circuit that performs compression at the time of data output, One feature of the memory control unit is that it has a decompression circuit that decompresses data read from the memory (expands when the data is compressed data). By providing the calculation unit with a compression circuit, compression can be performed in accordance with the data of the calculator. Since the decompression circuit of the memory control unit decompresses the compressed data and transmits the decompressed data to each computation unit, all computation units can use both compressed data and uncompressed data stored in the memory. Since it is not necessary to provide a decompression circuit in every arithmetic unit, an increase in circuit area can be suppressed.

<Configuration of Embodiment 1>
FIG. 6 shows a more specific configuration example of the data processing system according to the present embodiment. As shown in FIG. 6, the semiconductor device 100 according to the present embodiment further includes buffers 112 in some arithmetic modules 110 in addition to the schematic configuration of FIG. 4.

  The semiconductor device 100 includes an arithmetic unit 111, a buffer 112, and a compression circuit 11 on each arithmetic module 110 side. The buffer 112 is a conversion unit that converts the data of the arithmetic processing result into data of a compression processing unit, and holds the output data that is the arithmetic result from the arithmetic unit 111 so as to have a compressed data structure suitable for compression. The compressed data structure data is transferred to the compression circuit 11. The compression circuit 11 compresses the input data and transfers it to the memory control module 120 through the data bus 130. The memory control module 120 stores the transferred compressed data 201 in the external SDRAM 200. The decompression circuit 21 is arranged in the memory control module 120, and when the data read from the SDRAM 200 is the compressed data 201, the decompression circuit 21 is decompressed and sent to the data bus 130. A control signal indicating whether the data is compressed or not is sent from the calculation module 110 that is the read request source to the memory control module 120.

  In the example of FIG. 6, the semiconductor device 100 includes arithmetic modules 110_A to 110_D. For example, the arithmetic modules 110_A and 110_B include arithmetic units 111_A and 111B, buffers 112_A and 112_B, and compression circuits 11_A and 11B, respectively, and the arithmetic modules 110_C and 110_D include arithmetic units 111_C and 111D, respectively.

  For example, the arithmetic module 110_A (arithmetic unit 111_A) is a decoder that decodes image data (video data). The arithmetic module 110_A, after decoding, compresses the decoded data and stores it as compressed data 201 in the SDRAM 200.

  The arithmetic module 110_B (arithmetic unit 111_B) is an image processing device (GPU) that performs image processing (video processing) such as enlargement / reduction on the image data decoded by the arithmetic module 110_A. The arithmetic module 110_B acquires the compressed data 201 after decoding from the SDRAM 200 via the decompression circuit 21, performs image processing, compresses the data subjected to image processing, and stores the compressed data 201 in the SDRAM 200.

  The arithmetic module 110_C (calculator 111_C) adds a GUI such as a menu using the data that the arithmetic module 110_B has performed image processing, and generates display screen data. The arithmetic module 110_C acquires the compressed data 201 after image processing from the SDRAM 200 via the decompression circuit 21, generates display screen data, and stores the display screen data in the SDRAM 200 as uncompressed data 202.

  The arithmetic module 110_D (arithmetic unit 111_D) is a CPU that executes application processing using the operation control of the arithmetic modules 110_A to 110_C and the calculation result. The arithmetic module 110_C acquires uncompressed data 202 such as display screen data from the SDRAM 200, executes application processing, and stores the uncompressed data 202 in the SDRAM 200 as uncompressed data 202.

<Operation of Embodiment 1>
First, the operation of the arithmetic module 110 (for example, the arithmetic module 110_A) according to this embodiment will be described.

  The compression circuit 11 compresses data by using the redundancy of the data and reduces the data amount. For example, in the compression of image data, since the compression is performed using the difference between the target pixel and the reference pixel, the neighboring pixel group tends to have a small difference and a high compression rate. Therefore, in order to efficiently reduce the amount of data by compression, it is desirable to execute compression in units of continuous data (data having continuous addresses, block data) having a certain length.

  However, the data output from the computing unit 111 does not necessarily have a structure suitable for data compression. In other words, the order of data output from the computing unit 111 may not match the address order of the buffers in the SDRAM 200 depending on the processing convenience of the computing unit 111 and data characteristics. In this case, since the data is fragmented at locations where the addresses are discontinuous, it cannot be efficiently compressed. Therefore, in this embodiment, the output of the arithmetic unit 111 is not directly compressed, but once stored in the buffer 112 and converted into a structure suitable for compression (a structure in which addresses are continuous with a fixed length). The compression circuit 11 performs compression.

  In the following example, the computing unit 111 (for example, the computing unit 111_A) is connected to an H.264 which is a moving image compression standard. An example will be described in which a decoder having a deblocking filter adopted in H.265 is used, and the output of this decoder is converted into a compressed data structure of continuous 256-byte data of horizontal 64 pixels × vertical 4 lines.

  H. of the video compression standard. In H.265, the moving image is compressed in units of each image (picture). There are three types of compressed pictures: I / P / B.

  An I picture is compressed only with the data of the picture itself, and can be decoded (decoded) by itself. The P / B picture is compressed by taking the difference between the picture and the result of decoding before that (decoded image). For this reason, the data size after compression of the P / B picture can be made smaller than that of the I picture. When generating difference data in a P / B picture, data at an arbitrary position can be selected from a decoded image to be referenced. For example, data at a position that minimizes the amount of data after compression is selected.

  H. In the H.265 standard, a deblocking filter is employed in order to improve the compression efficiency of a moving image and subjective moving image quality, and the computing unit 111 includes the deblocking filter DF. The deblocking filter (deblocking filter) DF is a filter for reducing block distortion that occurs during image decoding.

  For example, the computing unit 111 performs decoding by entropy decoding, inverse quantization / inverse transformation, and the deblock filter DF is used at the end of decoding as an in-loop filter. For this reason, the H.D. The decoded image 265 becomes data after the deblocking filter processing. That is, the data can be stored in the buffer on the SDARM in order from the data after the deblocking filter processing. The order of positions on the image processed by the deblocking filter DF is H.264. As a result, the order in which the calculator 111 outputs data changes depending on the processing position in the image.

  H. In H.265, encoding processing and decoding processing are performed in units of square pixel blocks called CTB (Coding Tree Block). The CTB size can be selected and may be 16 × 16, 32 × 32, or 64 × 64 pixels. Hereinafter, a case where the CTB size is 64 × 64 pixels will be described as an example.

  FIG. 7 shows the output order of luminance data when the CTB size is 64 × 64 pixels, and FIG. 8 is an enlarged view of a part of FIG. As shown in FIG. 7, the arithmetic unit 111 outputs the data continuously in the vertical direction of 8/12/16 pixels depending on the position of the image to be processed, with the data of 16 × 1 pixels in the horizontal direction as one unit. To do. That is, 16 × 8 pixels, 16 × 12 pixels, and 16 × 16 face output blocks OB are output in the order of the arrows in FIGS.

  H. In 265, the CTB is further divided into blocks, and the encoding process and the decoding process are performed. For example, the CTB is divided into a plurality of CBs (Coding Blocks), and the CB is further divided into a plurality of PBs (Prediction Blocks) and TBs (Transform Blocks). The CB is a unit for performing a series of encoding / decoding such as intra / inter prediction, transformation / quantization processing / inverse quantization / inverse transformation processing, entropy encoding / decoding processing, and the like. PB is a unit for performing intra / inter prediction processing, and TB is a unit for performing transform / quantization processing / inverse quantization / inverse transform processing. The deblocking filter DF performs a filtering process in units of PB and TB. The output block OB is a processing unit block of the deblocking filter DF, and is, for example, PB or TB.

  Since the deblocking filter DF performs the filtering process with reference to the boundary pixels adjacent to the block, the filtering process of the next adjacent block (the block adjacent in the horizontal direction or the vertical direction) is not completed, Data cannot be output. For this reason, data is output not in the CTB size unit but in a unit shifted from the CTB.

  In the example of FIG. 7, the data output from the computing unit 111 is shifted 16 pixels to the left in the horizontal direction and 4 pixels upward in the vertical direction from the position of the 64 × 64 pixel unit of the image. That is, it is not the same as the CTB processing unit, and the left end is 48 pixels in the horizontal direction, the middle is 64 pixels, the right end is 80 pixels, the upper end is 60 pixels in the vertical direction, the middle is 64 pixels, and the lower end is 68 pixels. Data will be output.

  That is, first, the output block group OBU1 of 48 × 60 pixels is output, and then the output block group OBU2 of 64 × 60 pixels is output continuously in the horizontal direction, and then the output block group OBU of 80 × 60 pixels is finally output in the horizontal direction. The output block group OBU3 is output. As the next horizontal data, an output block group of 48 × 64 pixels, an output block group of 64 × 64 pixels,..., An output block group OBU6 of 80 × 64 pixels are sequentially output. After the output block groups OBU4 to OBU6 are output in succession in the vertical direction, the output block group OBU7 of 48 × 68 pixels is output at the end in the vertical direction, and then the output block of 64 × 68 pixels continuously in the horizontal direction. After the group OBU8 is output, the output block group OBU9 of 80 × 68 pixels is output at the end in the horizontal direction.

  Looking at an example of the output order in the output block group OBU, for example, as shown in FIG. 8, in the first output block group OBU1, (output block) OB1, OB11 below it, OB2 on the upper right, OB3 on the right Are output in the order of the lower left OB12, the right OB13, and so on. In the next output block group OBU2, the (output block) OB4, the right OB5, the lower left OB14, the right OB15,. Output in order.

  As described above, since the data is output from the arithmetic unit 111 in the order as shown by the arrows in FIGS. 7 and 8, the original image positional relationship is different in the order as it is. That is, as shown in FIG. 8, the original image is an image that is continuous with OB1, OB2, OB3, OB4,... In the horizontal direction (output block). Block) OB1, OB11, OB2, OB3.

  In this embodiment, the output data as shown in FIGS. 7 and 8 is converted into a continuous data structure of 64 × 4 units of the image by the buffer 112. FIG. 9 shows a configuration example for realizing such a buffer 112. Note that the buffer according to the present embodiment only needs to have such a data structure, and therefore, any configuration may be used for data input / output. The buffer control unit in the buffer 112 may control the input order / output order of the data in the buffer 112, the arithmetic unit controls the input order of the data to the buffer 112, and the compression circuit receives the data from the buffer 112. The output order may be controlled.

  As shown in FIG. 9, the buffer 112 includes two banks, and includes a bank BK0 and a bank BK1. The banks BK0 and BK1 do not need to be physically divided into two, and the first half / second half of one physical buffer may be used as the banks BK0 and BK1, respectively. The banks BK0 and BK1 have the same size, and can store data of up to 64 × 68 pixels per bank.

  The banks BK0 and BK1 have four regions of 16 pixels in the horizontal direction and two regions of 32 rows and 36 rows in the vertical direction. That is, the bank BK0 includes areas AR01 to AR04 for 16 × 32 pixels and areas AR05 to AR08 for 16 × 36 pixels, and the bank BK1 includes areas AR11 to AR14 and 16 × 36 for 16 × 32 pixels. It has pixel areas AR15 to AR18.

  The 16 pixels in the horizontal region are the same size as each output block OB, and the 64 pixels in the bank in the horizontal direction are the same size as the output block groups OBU2, OBU5, OBU8 (or CTB). The 32 and 36 rows in the vertical region have the same size as the upper two blocks and the lower three blocks of the output block group OBU7, OBU8, and OBU9.

  Hereinafter, the storing operation of the buffer 112 when the computing unit 111 starts data output from the upper left of the image will be described in detail with reference to FIGS.

  First, the output data (OBU1) corresponding to the first CTB is 48 × 60 pixels. As shown in FIG. 10, the data of the output block group OBU1 is stored in the bank BK0 of the buffer 112 in the order of the arrows. Since the blocks of the output block group OBU1 are output in the order shown in FIGS. 7 and 8, the buffer 112 stores the output blocks OB1 and OB11 in the area AR01 in the order, and stores the output block OB2 in the area AR02. OB3 is stored in area AR03, output block OB12 is stored after OB2 in area AR02, and output block OB13 is stored after OB3 in area AR03. Thereafter, data is stored in the order of the areas AR05 to AR07, and the output block group OBU1 is stored in the bank BK0. At this stage, the area AR04 and the area AR08 of the bank BK0 are empty, and the data of the compression unit 64 × 4 is not yet ready, so no data is output from the buffer.

  Next, the output data (OBU2) corresponding to the second CTB is 64 × 60 pixels. As shown in FIG. 11, the data of the output block group OBU2 is stored in the banks BK0 and BK1 of the buffer 112 in the order of the arrows. At this time, since the data of the output block group OBU1 is stored in the areas AR01 to AR03 and AR05 to AR07 of the bank BK0, the empty areas (AR04 and AR08) of the bank BK0 and the area of the bank BK1 are used. Since each block of the output block group OBU2 is output in the order shown in FIGS. 7 and 8, the buffer 112 stores the output block OB4 in the area AR04, stores the output block OB5 in the area AR11, and stores the output block OB14 in the area. The data is stored after OB4 of AR04, and the output block OB15 is stored after OB5 of area AR11. Thereafter, data is stored in the order of the areas AR12 to AR14, AR08, AR15 to AR18.

  When the output data (OBU2) corresponding to the second CTB is stored in the buffer 112, as shown in FIG. 12, a large number of 64 × 4 unit (compression unit) continuous data OL are arranged in the bank BK0. These continuous data OL are read from the buffer 112 and sent to the compression circuit 11.

  The compression circuit 11 compresses the continuous data OL received from the buffer 112. The compression of the compression circuit 11 may be any method as long as it can be expanded by the expansion circuit 21. For example, DPCM (differential pulse code modulation), lossless compression, and lossy compression may be used. The compression circuit 11 sends the compressed data to the memory control module 120 via the data bus 130 after data compression. The memory control module 120 stores the received compressed data in a buffer on the SDRAM 200.

  After the continuous data OL in units of 64 × 4 is read from the bank BK0, the bank BK0 becomes empty as shown in FIG. 13, so that data can be stored. Next, as shown in FIG. 14, the output data corresponding to the next CTB is stored using the empty areas (AR14 and AR18) of the bank BK1 and the empty bank BK0. Thereafter, the bank BK0 and the bank BK1 are alternately used to repeat the data storage from the arithmetic unit 111 and the reading of 64 × 4 units.

  In this example, in order to simplify the explanation, it is assumed that 64 × 4 units of data are read after all the data corresponding to the CTB is stored. However, the present invention is not limited to this. That is, it can be read out when 64 × 4 units of data are available.

  Next, the operation of the memory control module 120 according to this embodiment will be described. Since this embodiment is mainly characterized by a memory read operation, the read operation will be described.

  As shown in FIG. 6, the memory control module 120 is provided with a decompression circuit 21 that decompresses compressed data. In addition to the read command, the calculation module 110 that is the read request source also sends a flag indicating whether the data to be read from now on is compressed, in addition to the read command. The memory control module 120 (access circuit 121) reads data from the SDRAM 200 in accordance with the read command, refers to the flag of the command, and if not compressed data, sends the read data from the SDRAM 200 to the arithmetic module 110 as it is. . If the data is compressed data according to the command flag, the read data is sent to the decompression circuit 21 in the memory control module 120, and the decompressed data is sent to the arithmetic module 110. The arithmetic module 110 (arithmetic unit) designates the flag, so that the compressed data 201 or the uncompressed data 202 can be read according to the control of the arithmetic module 110 (arithmetic unit).

<Effect of Embodiment 1>
As described above, in this embodiment, a buffer that receives the output of the arithmetic unit is installed in the arithmetic module, and after the data is buffered, the compression process is performed. Thereby, it can convert into the data structure suitable for compression, and a compression rate can be made high.

  Further, by increasing the data length before compression, it is possible to obtain a compressed data length that can realize high transfer efficiency between the semiconductor device and the SDRAM even after compression. The graph of FIG. 15 shows the transfer efficiency (access efficiency) of the SDRAM for one data transfer length.

  For example, it is assumed that the data length before compression is 128 bytes and that after compression is half of 64 bytes. When the data length is 128 bytes, the transfer efficiency is nearly 100%, but when the data length is 64 bytes, the efficiency is about 50%. At an efficiency of 50%, there is a period during which data cannot be transferred once every two times, which is equivalent to a transfer of substantially 128 bytes. That is, the transfer amount between the semiconductor device and the SDRAM is not substantially reduced. Therefore, it is desirable to set the data length so that efficient transfer can be realized even after data compression. For example, the compressed data length is preferably close to the data transfer length (transfer rate) of 128 bytes, for example, 256 bytes are compressed to 128 bytes.

  Further, by providing a decompression circuit in the memory control module, the compressed data can be decompressed and sent to each arithmetic module. Therefore, even a module that does not have a decompression circuit on the arithmetic module side can use both compressed data and non-compressed data in the SDRAM by indicating that the object to be accessed is compressed data.

(Embodiment 2)
The second embodiment will be described below with reference to the drawings. This embodiment can be applied to the basic examples 1 to 3 or the first embodiment, and is different from the basic examples 1 to 3 or the first embodiment only in the compressed data storage method.

  FIG. 16 shows a storage image of compressed data in the present embodiment. 1 to 6, the data is compressed as shown in FIG. 16 and stored in the SDRAM.

  For example, the compression circuit 11 compresses the data output from the computing unit 111 in units of 256 bytes. Since the compressed data has a short data length, when the compressed data is continuously stored in the SDRAM, the data addresses are shifted. In this case, in order to directly access data whose addresses are shifted, it is necessary to store the addresses before and after the change in association with each other.

  Therefore, in the present embodiment, as shown in FIG. 16, the compression circuit 11 stores the compressed data from the same 256-byte head address as that of the uncompressed (before compression). That is, when the compressed data is stored in the SDRAM 200, only the compressed data is stored without changing the head address in 256-byte units, which is the compression unit.

  As described above, in the present embodiment, the address where the compressed data is stored is the same as the address at the time of non-compression in units of 256 bytes. This eliminates the need to hold an address before compression, for example, the head address of the buffer. It is also possible to access arbitrary data after compression in random order (random access).

(Embodiment 3)
The third embodiment will be described below with reference to the drawings. This embodiment can be applied to the first or second embodiment, and is different from the first or second embodiment only in the configuration of the memory control module.

  FIG. 17 shows a configuration example of the memory control module 120 according to the present embodiment, and FIG. 18 shows an example of data read operation in the present embodiment.

  As shown in FIG. 17, the memory control module 120 of the first or second embodiment further includes an address converter 122 and an MMU (memory management unit) 123. The address converter 122 converts the logical address specified by the command from the arithmetic module 110 into a (different) converted logical address. The MMU 123 converts the converted logical address into a physical address on the SDRAM. The access circuit 121 accesses the SDRAM 200 with a physical address. Further, the address converter 122 (or the decompression circuit 21) determines whether data is compressed based on the converted logical address. For example, the decompression circuit 21 decompresses the read data when the requested address is included in the first address area, and does not decompress the read data when the requested address is included in the second address area. . For example, the memory can be effectively used by making the address area after conversion of the first address area and the address area after conversion of the second address area the same address area on the SDRAM.

  In the present embodiment, the logical address area (area A) in which the compressed data is stored is remapped to another logical address area (area B), and an access to the area B is performed by the address converter 122. A is converted to the logical address of A. For example, the address converter 122 has a mapping table that maps a logical address before conversion and a logical address after conversion (and presence / absence of compression). That is, the address converter 122 performs address conversion / inverse conversion by referring to the mapping table, and determines compressed data / uncompressed data.

  As shown in FIG. 18, since the read data for access to the area A is determined to be uncompressed data read from the area A by the address converter, the read data for the area A of the SDRAM 200 is directly sent to the arithmetic module 110. Output. Since the read data for access to the area B is determined to be compressed data read from the area A by the address converter, the read data of the area A of the SDRAM 200 is expanded by the expansion circuit 21, and the expanded data is expanded to the area. B data is output to the arithmetic module 110.

  According to the present embodiment, switching between uncompressed data and compressed data can be specified in the address area when reading. That is, when reading from the memory, whether to decompress the compressed data can be switched depending on the address area to be read. Thereby, the flag indicating whether or not the data output from the arithmetic module is compressed can be deleted. Further, it is possible to have a plurality of areas to be remapped, and the type of switching between compression and non-compression can be changed for each area.

(Embodiment 4)
The fourth embodiment will be described below with reference to the drawings. This embodiment is applicable to the second or third embodiment, and differs from the second or third embodiment only in the mapping of compressed data.

  FIG. 19 shows an image of storing compressed data in the present embodiment, and FIG. 20 shows an example of data read operation in the present embodiment.

  As shown in FIG. 19, using the fixed-length compression method from 256 bytes to 128 bytes in the second embodiment, compression of different mappings (areas) in the first 128 bytes and the latter 128 bytes of 256 bytes of the compression unit. Store the data. In the third embodiment, the area A and the area B are defined, but in the present embodiment, a third remapped area C is further defined. For example, the area B is mapped to the first half 128 bytes of 256 bytes, and the area C is mapped to the second half 128 bytes of 256 bytes. That is, the access to the area B decompresses the compressed data of the first half 128 bytes of 256 bytes, and the access to the area C decompresses the compressed data of the second half 128 bytes. In this example, two pieces of data are stored in the first half and the second half of 256 bytes of the compression unit. However, the present invention is not limited to this, and a plurality of pieces of data may be stored.

  As shown in FIG. 20, since the read data for access to the area A is determined to be passing data read from the area A (data that does not expand like uncompressed data), the read data for the area A of the SDRAM 200 is read. Is output to the arithmetic module 110 as it is. Since the read data for access to the area B is determined to be compressed data read from the first 128 bytes of 256 bytes in the area A, the first 128 bytes of read data (0 to 256 bytes in the area A of the SDRAM 200). 125, 256 to 384, 512 to 640, and 768 to 896) are decompressed by the decompression circuit 21, and the decompressed data is output to the arithmetic module 110 as region B data (1024 to 2048 data). Since the read data for access to the area C is determined to be compressed data read from the latter 128 bytes of 256 bytes in the area A, the read data (128 to 256 bytes) of the latter 256 bytes in the area A of the SDRAM 200 is determined. 256, 384 to 512, 640 to 768, and 896 to 1024) are decompressed by the decompression circuit 21, and the decompressed data is output to the arithmetic module 110 as data in region C (data from 2048 to 3072).

  According to the present embodiment, since the compressed data of a plurality of areas is stored in one area of the SDRAM, the buffer size can be doubled with the data size after expansion. Further, the random access is possible as in the second embodiment, and the flag indicating whether the data output from the arithmetic module is compressed as in the third embodiment can be deleted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Data processing system 11 Compression circuit 21 Expansion circuit 91-93 Data processing system 100 Semiconductor device 110 Arithmetic module 111 Arithmetic unit 112 Buffer 120 Memory control module 121 Access circuit 122 Address converter 130 Data bus 200 SDRAM
201 Compressed data 202 Uncompressed data 901 to 903 Semiconductor device DF Deblock filter

Claims (15)

Comprising an arithmetic module and a memory control module,
The arithmetic module is
An arithmetic processing unit for executing arithmetic processing;
A compression unit for compressing the data of the arithmetic processing result;
With
The memory control module is
An access unit for writing the compressed data to a memory and reading the written data from the memory;
A decompression unit for decompressing data read from the memory and outputting the decompressed data to the arithmetic module;
A semiconductor device comprising: A conversion unit that converts the data of the arithmetic processing result into data of a compression processing unit;
The compression unit compresses the data of the compression processing unit;
The semiconductor device according to claim 1. The conversion unit converts the data of the operation processing result into data having a structure in which addresses are continuous with a predetermined length.
The semiconductor device according to claim 2. The conversion unit is a buffer that stores data of the calculation processing result in the compression processing unit.
The semiconductor device according to claim 2. The arithmetic processing unit outputs data with discontinuous addresses in the order of processing units of the arithmetic processing,
The buffer stores the data so that the addresses of the output data are continuous.
The semiconductor device according to claim 4. The decompression unit decompresses the data when the data read from the memory is compressed;
The semiconductor device according to claim 1. The arithmetic processing unit, when reading data from the memory, outputs a flag indicating compression or non-compression of data together with a memory read command,
The decompression unit decompresses the data based on the flag when the data read from the memory is compressed;
The semiconductor device according to claim 6. The compression unit compresses data in a predetermined compression unit, and writes the compressed data to the memory with the start address of the compression unit as the same address as before compression.
The semiconductor device according to claim 1. The memory control module includes an address conversion unit that converts an address requested from the arithmetic module;
The access unit accesses the memory with the converted address.
The semiconductor device according to claim 1. The decompression unit decompresses the data when the requested address is included in a first address area, and does not decompress the data when the requested address is included in a second address area. ,
The semiconductor device according to claim 9. The converted address area of the first address area and the converted address area of the second address area are included in the same address area on the memory.
The semiconductor device according to claim 10. The compression unit compresses data in a predetermined compression unit, requests to write the data in the compression unit to the memory,
The address conversion unit converts the address so that a plurality of data of the compression unit is included in the same address area on the memory.
The semiconductor device according to claim 9. The decompression unit decompresses data in a first memory area in the address area on the memory when the requested address is included in a first address area, and the requested address is a second address. Decompressing data in the second memory area of the address area on the memory when included in the area;
The semiconductor device according to claim 12. A data processing system comprising a semiconductor device and a memory for storing data of the semiconductor device,
The semiconductor device includes an arithmetic module and a memory control module,
The arithmetic module is
An arithmetic processing unit for executing arithmetic processing;
A compression unit for compressing the data of the arithmetic processing result;
With
The memory control module is
An access unit for writing the compressed data to the memory and reading the written data from the memory;
A decompression unit for decompressing data read from the memory and outputting the decompressed data to the arithmetic module;
A data processing system comprising: A method for controlling a semiconductor device comprising an arithmetic module and a memory control module,
The arithmetic module is
Execute arithmetic processing,
Compress the data of the arithmetic processing result,
The memory control module is
Writing the compressed data to a memory, reading the written data from the memory,
Decompressing the data read from the memory and outputting the decompressed data to the arithmetic module;
A method for controlling a semiconductor device.

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