JP2009130599A - Moving picture decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a moving picture decoder which reduces the number of times of accessing a frame buffer during decoding and range mapping processing. <P>SOLUTION: A decoding part 1 reads reference picture data from a frame buffer 61 arranged in an SDRAM 6 through a DMAC (Direct Memory Accessing Controller) 10 and performs decoding of a macro block unit when a reference picture is necessary while decoding compressively encoded picture data. A loop filter 2 performs deblocking processing of the decoded picture data and stores the result in a pixel buffer 3. A range mapping processing part 4 is pipeline connected to the decoding part 1, sequentially reads the picture data stored in the pixel buffer 3 to perform range mapping processing, and stores the result in a range mapping buffer 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a moving picture decoding apparatus.

  VC-1 is one of high-efficiency encoding methods for moving images. VC-1 also compresses the amount of information by reducing redundancy in the time direction and space direction, similar to MPEG-2 and the like. Inter-frame predictive coding is used to reduce redundancy in the temporal direction, and motion prediction and prediction images are created in units of blocks with reference to the front or rear picture. Encoding is performed on the difference value.

  Here, a picture is a term representing one screen, and three types of pictures called an I picture, a P picture, and a B picture are used in the inter-screen predictive coding method.

  The I picture performs intra prediction encoding without a reference image, the P picture performs inter prediction encoding with reference to only one picture, and the B picture refers to two pictures at the same time Thus, inter prediction encoding is performed. B pictures can refer to two pictures as an arbitrary combination of display times from the front or rear.

  In VC-1, the data amount is compressed by changing the dynamic range of encoding according to the change of image data. Therefore, when playing back an image, it is standardized to perform range mapping processing that restores the compressed dynamic range after decoding the image data based on the input I picture, P picture, and B picture. (For example, refer nonpatent literature 1.).

  Therefore, a decoding unit that performs decoding processing sequentially stores decoded images in a frame buffer, and a range mapping processing unit reads out the decoded images from the frame buffer in display order and performs range mapping processing with a delay of one frame. .

  The data after the range mapping process is also stored in the frame buffer, and the stored data is sequentially read and sent to the display unit. That is, at the time of the range mapping process, the range mapping processing unit reads one frame of data from the frame buffer and writes one frame of data to the frame buffer for each frame decoding.

  As a frame buffer for storing the decoded image and the data after the range mapping process, an SDRAM that can be commonly accessed from the decoding unit and the range mapping processing unit is used.

  In that case, the memory area of one SDRAM is divided and allocated to a frame buffer used by the decoding unit and a frame buffer used by the range mapping processing unit.

  At that time, a plurality of (for example, about four) frame buffers are supplied to the decoding unit so that decoding processing referring to other pictures does not fail and data read by the range mapping processing unit is not destroyed. Assign. In addition, two frame buffers are allocated to the range mapping processing unit so that the next range mapping processed data can be written during reading of the range mapping processing data by the display unit.

  As described above, when an SDRAM is used as a frame buffer, a large-capacity SDRAM is required to process an image having a large number of pixels such as an HD (high definition) image.

Since a large-capacity SDRAM takes time to transfer data, it is important to reduce the number of accesses to the SDRAM as much as possible in order to improve the processing efficiency of the range mapping process.
SMPTE 421M-2006, “VC-1 Compressed Video Bit Stream Format and Decoding Process”

  Accordingly, an object of the present invention is to provide a moving picture decoding apparatus capable of reducing the number of accesses to a frame buffer during decoding and range mapping processing.

  According to an aspect of the present invention, when decoding compressed and encoded image data, when a reference image is necessary, the decoding unit reads out the reference image data from the first frame buffer and performs decoding in units of macroblocks. A loop filter that performs deblocking processing of the decoded image data, a pixel buffer that stores the deblocked image data, and an image that is pipeline-connected to the decoding unit and stored in the pixel buffer And a range mapping processing unit that sequentially reads data and performs range mapping processing.

  According to the present invention, the number of accesses to the frame buffer during decoding and range mapping processing can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a configuration of a video decoding device according to an embodiment of the present invention.

  The moving picture decoding apparatus according to the present embodiment decodes a DMAC (direct memory access controller) from a frame buffer 61 arranged in the SDRAM 6 when a reference picture is necessary when decoding compressed and encoded picture data. ) Decoding unit 1 that reads the reference image data via 10 and decodes in macroblock units, loop filter 2 that performs deblocking processing of the decoded image data, and image data that has been deblocked by loop filter 2 A pixel buffer 3 for storing image data, a range mapping processing unit 4 that is pipeline-connected to the decoding unit 1, sequentially reads out image data stored in the pixel buffer 3 and performs range mapping processing, and range mapping processing unit 4 performs range mapping Range map to store the processed data It comprises a ring buffer 5, a.

  When data is stored in the pixel buffer 3 or the range mapping buffer 5, the DMAC 10 requests the CPU 20 to release the bus. When the bus is released, the data stored in the pixel buffer 3 or the range mapping buffer 5 is stored in the SDRAM 6. Transfer to the arranged frame buffer 61.

  Here, the feature of the processing in the moving picture decoding apparatus of the present embodiment is that the decoding processing in the decoding unit 1, the deblocking processing by the loop filter 2, and the range mapping processing by the range mapping processing unit 4 are simultaneously performed by pipeline processing. To be done in parallel.

  FIG. 2 shows how pipeline processing is performed by the decoding unit 1, the loop filter 2 and the range mapping processing unit 4.

  In the decoding unit 1, a variable length decoding process VLD, an inverse quantization / inverse orthogonal transform process IQ / IT, an interpolation process IP, and a motion compensation process MC are sequentially executed. Subsequent to the processing in the decoding unit 1, deblocking processing (LF) by the loop filter 2 and range mapping processing (RM) by the range mapping processing unit 4 are executed.

  Each process is executed in units of macroblocks (for example, 16 pixels × 16 pixels) of the frame image.

  That is, as shown in FIG. 2, the respective processes for the data of the macroblocks (0, 1, 2, 3, 4,...) That are continuously input are continuously executed, and the processed data is It is handed over to the next process.

  When performing the pipeline processing, the range mapping processing unit 4 reads the deblocked data from the pixel buffer 3 and performs the range mapping processing.

  On the other hand, in the conventional process in which the decoding process and the range mapping process are performed independently, the deblocking data for one picture is once written in the frame buffer, and then the deblocking data is read from the frame buffer. The range mapping process was performed.

  In contrast, in this embodiment, it is not necessary to read the deblocked data from the frame buffer during the range mapping process.

  Conventionally, since the range mapping process is performed on the data read from the frame buffer, it is necessary to transfer all the deblocked data to the frame buffer. That is, it is necessary to transfer the B picture after the deblocking process that is not referred to in the subsequent decoding process to the frame buffer.

  On the other hand, in the present embodiment, since the deblocking data is read from the pixel buffer 3 and the range mapping process is performed, the picture data after the deblocking process transferred to the frame buffer 61 is subjected to a subsequent decoding process. Only the I picture and the P picture used as the reference screen in FIG.

  That is, in this embodiment, it is not necessary to transfer a B picture that is not referred to in subsequent decoding processing to the frame buffer 61. Accordingly, the amount of data transferred to the frame buffer 61 is reduced accordingly.

  Next, management of data writing to the frame buffer 61 in the present embodiment will be described by taking the arrangement of images shown in FIG. 3 as an example.

  FIG. 3 is a diagram illustrating an example of a sequence of compression-encoded image data input to the video decoding device according to the present embodiment.

  Here, I0 is an I picture, P4, P5, P6, and P9 are P pictures, and B1, B2, B3, B7, and B8 are B pictures. A hatched picture indicates that it is referenced from another picture.

  FIG. 4 is a diagram showing a writing state with respect to the time axis of data transferred from the pixel buffer 3 and the range mapping buffer 5 to the frame buffer 61 during the processing of the image data shown in FIG.

  Here, the frame buffer 61 is divided into six areas, buffer 0 to buffer 5, and data written to the frame buffer 61 is managed in units of these areas.

  The data transferred from the pixel buffer 3 needs to be stored in the frame buffer 61 until it is referred to by another picture. Therefore, until the data transferred from the pixel buffer 3 is referred to by another picture, the area needs to be write-protected.

  Further, the data transferred from the range mapping buffer 5 needs to be stored in the frame buffer 61 until it is read as display processing data. In other words, it is necessary to write-protect the area until it is read as display processing data.

  Such a period in which writing must be prohibited during decoding processing and range mapping processing is indicated by hatching in FIG.

  Therefore, new data is written to the frame buffer 61 in an area where writing is not prohibited. Note that writing may be performed in any area as long as the area is not write-protected.

  That is, in this embodiment, the frame buffer arrangement area is not fixed, such as the buffer area dedicated to the pixel buffer 3 and the buffer area dedicated to the range mapping buffer 5. The arrangement of the buffer areas for the pixel buffer 3 and for the range mapping buffer 5 dynamically changes during execution of processing in the six areas of the buffers 0 to 5.

  FIG. 5 shows a frame buffer writing example in a conventional process in which the decoding process and the range mapping process are performed independently as a reference example for comparison with the present embodiment.

  In this example, it is assumed that buffers 0 to 3 are fixedly allocated as decoder unit frame buffers, and buffers 4 and 5 are fixedly allocated as range mapping frame buffers.

  In addition to the I picture and P picture, a B picture that is a non-reference picture is also written in the decoder unit frame buffer.

  The writing to the range mapping frame buffer is performed after the data in the decoder unit frame buffer is read and the range mapping process is performed.

  Compared with the conventional method shown in FIG. 5, the present embodiment shown in FIG. 4 does not write a B picture, which is a non-reference picture, and therefore the number of writes to the frame buffer 61 is reduced.

  Further, in the present embodiment, since reading of the frame buffer 61 is unnecessary for the range mapping process, the writing of the data after the range mapping process to the frame buffer 61 is one cycle faster than the conventional method shown in FIG. .

  According to the present embodiment, since the range mapping process is performed in succession to the decoding process and the deblocking process by the pipeline process, it is not necessary to write the non-reference picture to the frame buffer. The number of writes can be reduced.

  In addition, since the frame buffer is not read during the range mapping process, the number of times the frame buffer is read can be reduced.

  In addition, since the deblocking process and the range mapping process are performed in parallel, the timing for writing the range mapping process result to the frame buffer is accelerated, and as a result, the timing for reading the range mapping process result from the frame buffer as display processing data is also accelerated. can do.

The block diagram which shows the example of a structure of the moving image decoding apparatus which concerns on the Example of this invention. The figure for demonstrating the pipeline process in the moving image decoding apparatus which concerns on the Example of this invention. The figure which shows the example of the arrangement | sequence of the image data by which the compression encoding was carried out. The figure which shows the example of a data storage to the frame buffer of the moving image decoding apparatus which concerns on the Example of this invention. FIG. 5 is a reference diagram showing an example of use of a general frame buffer for comparison with the data storage example shown in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Decoding part 2 Loop filter 3 Pixel buffer 4 Range mapping process part 5 Range mapping buffer 6 SDRAM
61 Frame buffer 10 DMAC
20 CPU

Claims (5)

When decoding the compression-encoded image data, when a reference image is necessary, a decoding unit that reads the reference image data from the first frame buffer and performs decoding in units of macroblocks;
A loop filter for performing deblocking processing of the decoded image data;
A pixel buffer for storing the deblocked image data;
A range mapping processing unit that is pipeline-connected to the decoding unit and sequentially reads out the image data stored in the pixel buffer and performs a range mapping process;
A moving picture decoding apparatus comprising: The moving picture decoding apparatus according to claim 1, wherein the processing of the decoding unit and the processing of the range mapping processing unit are pipeline-processed in parallel in units of macroblocks. 3. The moving image according to claim 1, wherein, of the image data stored in the pixel buffer, only an I picture and a P picture that are reference images in subsequent decoding are stored in the first frame buffer. Image decoding device. The video decoding device according to claim 3, wherein the image data for which the range mapping processing by the range mapping processing unit has been completed is stored in a second frame buffer. The first frame buffer and the second frame buffer are arranged in one memory device, and the arrangement position thereof dynamically changes during the decoding and the range mapping process. The moving picture decoding apparatus according to claim 4.

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