JP5731816B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to a technique for encoding and storing an image.

  In a general moving image processing apparatus, an image for one frame is stored in a memory, and then this image is read while scanning in the line direction and transmitted to an image processing module. The image processing module performs pixel processing and filter processing in units of one line or in units of several lines, and writes and outputs again to the frame buffer.

  With the recent increase in image resolution such as 4K2K and 8K4K, conventional line processing can increase the line buffer capacity and memory bandwidth required for image processing. Therefore, there has been a problem that the memory cost is increased. In order to reduce memory costs, an architecture has been proposed in which pixels are compressed and expanded in real time when an image is written to or read from a memory.

  Patent Document 1 discloses that an image is divided into a plurality of rectangular blocks, compressed in units of rectangular blocks, and the compressed rectangular blocks are stored at predetermined addresses of a predetermined size in a compression memory. A variable length conversion algorithm such as JPEG is used as the compression algorithm. A memory allocation address table is set when compressed data is written, and is used for reading compressed data. In the above configuration, since compression is performed in units of rectangular blocks, when performing image processing, rectangular blocks obtained after decompressing the compressed rectangular blocks are processed.

JP 2006-129471 A

  When image processing such as filter processing is performed in units of rectangular blocks, pixels around the boundary pixel that are pixels near the division boundary may not exist in the rectangular block to which the boundary pixel belongs. For boundary pixels, image processing with reference to surrounding pixels cannot be performed. In this case, it is possible to perform processing by duplicating the boundary pixel. However, since the image quality of the division boundary deteriorates, it is desirable to refer to a pixel corresponding to a peripheral pixel from an adjacent rectangular block. In order to refer to the pixels in the adjacent rectangular block, it is necessary to read out all the rectangular blocks adjacent to the rectangular block to be processed.

  When a rectangular block is configured with a predetermined number of pixels as in Patent Document 1, if the size of the rectangular block is larger than the number of reference pixels, the ratio of reading out unnecessary pixels increases, so the memory bandwidth is effectively used. There is a problem that you can not. In addition, when the size of the rectangular block is made equal to that of the reference pixel in order to reduce the reading amount of unnecessary pixels, there is a problem that the memory bandwidth is compressed due to an increase in additional information such as the arrangement address information of the compressed data. There is.

  In JPEG and the like, in general, the larger the compression unit, the more efficient the compression. Therefore, if the rectangular block is set to be small, the effect of reducing the memory bandwidth is reduced. Further, in the image processing circuit, a configuration is assumed in which a filter processing circuit that requires a reference pixel is divided into a front stage and a rear stage with a frame memory interposed therebetween. In this case, when the number of reference pixels in the subsequent stage is smaller than that in the previous stage, if the size of the rectangular block is created in accordance with the initial number of reference pixels, reading of unnecessary pixels increases in the subsequent stage. In addition, if the size of the rectangular block is created in accordance with the subsequent stage, the number of rectangular blocks to be read must be changed between the previous stage and the subsequent stage, which complicates the processing.

  The present invention has been made in view of the above problems, and even when image processing using pixels in adjacent pixel blocks is performed, access to a memory storing pixel block groups is further reduced. It aims at providing the technique for.

In order to achieve the object of the present invention, for example, an image processing apparatus of the present invention comprises the following arrangement. That is, adjacent pixel blocks composed of a plurality of pixels, the first portion pixel block including the pixels in the pixel block to be referenced by the image processing for the left pixel block adjacent to the left side of the pixel block, the right side of the pixel block the remaining portion of omitting the second part pixel block including the pixels in the pixel block to be referenced in the image processing, the first portion pixel block and the second partial pixel block from the pixel block for the right pixel block Means for dividing into three partial pixel blocks of a third partial pixel block which is a pixel block;
The first partial pixel block, the second partial pixel block, and the third partial pixel block are individually encoded to obtain a first encoded partial pixel block, a second encoded partial pixel block, Encoding means for generating a third encoded partial pixel block and storing it in a memory.

  According to the configuration of the present invention, it is possible to further reduce access to the memory storing the pixel block group even when image processing using pixels in adjacent pixel blocks is performed.

The figure which shows the map on the memory. The figure which shows a vertical division image, a pixel block, a shared area, a non-shared area, and an encoding unit. FIG. 3 is a block diagram illustrating an example of a functional configuration of the image processing apparatus. 6 is a flowchart of processing performed by the image processing apparatus. FIG. 3 is a block diagram illustrating an example of a functional configuration of the image processing apparatus. 6 is a flowchart of processing performed by the image processing apparatus.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. The embodiment described below shows an example when the present invention is specifically implemented, and is one of the specific examples of the configurations described in the claims.

[First Embodiment]
In the present embodiment, a single image is divided in the vertical direction to generate a plurality of vertically divided images. Of course, the number of divisions for generating a vertically divided image is two or more. In FIG. 2C, as an example, one image 220 is divided into three vertically divided images B0, B1, and B3.

  Then, in order to encode (compress) each vertically divided image, each vertically divided image is further divided into pixel blocks (image blocks) including a plurality of pixels. Then, image processing is performed for each vertically divided image. When image processing is performed on one vertically divided image, the image processing is performed while referring to pixels in the vertically divided image in the raster scan order. That is, in the case of FIG. 2C, the first line of the vertically divided image B0 is processed first, and then the second line of the vertically divided image B0 is processed. When all the lines of the vertically divided image B0 are processed in this way, the first line of the vertically divided image B1 is then processed. However, in the image processing for the pixels located at the left and right ends of the target vertically divided image, it is necessary to refer to the pixels in the vertically divided images adjacent to the left and right of the target vertically divided image. Therefore, in the vertically divided images adjacent to the left and right, the vicinity of the boundary with the focused vertical divided image is a shared area with the focused vertically divided image. That is, as shown in FIG. 2B, when image processing is performed on a pixel located in the vicinity of the boundary 221 with the vertically divided image B1 in the pixel group in the vertically divided image B0, the pixels in the vertically divided image B1. It is necessary to refer to a pixel located in the vicinity of the boundary 229 with the vertically divided image B0 in the group. Similarly, when image processing is performed on a pixel located in the vicinity of the boundary 229 with the vertical division image B0 in the pixel group in the vertical division image B1, the vertical division image B1 in the pixel group in the vertical division image B0. It is necessary to refer to a pixel located in the vicinity 221 of the boundary. Therefore, the boundary vicinity 221 and the boundary vicinity 229 are shared areas of the vertically divided image B0 and the vertically divided image B1. In addition, when image processing is performed on a pixel located in the vicinity of the boundary 222 with the vertical division image B1 among the pixel group in the vertical division image B3, the pixel group with the vertical division image B3 in the pixel group in the vertical division image B1 It is necessary to refer to a pixel located near the boundary 228. Similarly, when image processing is performed on a pixel located in the vicinity of the boundary 228 with the vertically divided image B3 in the pixel group in the vertically divided image B1, the vertical divided image B1 in the pixel group in the vertically divided image B3 It is necessary to refer to a pixel located in the vicinity of the boundary 222. Therefore, the vicinity of the boundary 222 and the vicinity of the boundary 228 are shared areas of the vertically divided image B0 and the vertically divided image B3.

  From the above, for example, when image processing is performed on the vertically divided image B1, not only the pixels in the vertically divided image B0 but also the pixels in the shared areas 221 and 222 are required. However, when image processing is performed on the vertically divided image B1, in addition to the pixels in the vertically divided image B1, the pixels in the shared areas 221 and 222 are also read. One shared area exists on the right or left side of the vertically divided image at the edge of the image, and one shared area exists on the left and right sides of the other vertically divided images.

  A detailed configuration for each pixel block is shown in FIG. The pixel block 202 is one pixel block when the vertically divided image 200 is divided for each pixel block. The pixel block 202 includes a shared area LB10 (left shared area) with the pixel block 201, a shared area RB10 (right shared area) with the pixel block 203, and a pixel group area B10 (non-shared area) that is not referred to by any pixel block. Consists of. The pixel block 201 is one pixel block when the vertically divided image is divided for each pixel block. The pixel block 201 includes a shared area RB00 with the pixel block 202, a left end area LB00, and a pixel group area B00 that is not referred to by any pixel block. Become. The pixel block 203 is one pixel block when the vertically divided image is divided for each pixel block. The pixel block 203 is referred to from any pixel block, the shared area LB20 with the pixel block 202, the shared area RB20 with the adjacent pixel block. It consists of a region B20 of the pixel group that is not to be processed.

  The shared region RB00 is a region to which pixels referred to when image processing is performed on the pixels in the region LB10, and the shared region LB10 belongs to pixels referred to when image processing is performed on the pixels in the region RB00. It is an area. The shared region RB10 is a region to which a pixel referred to when image processing is performed on the pixels in the region LB20, and the shared region LB20 is a pixel referred to when image processing is performed on the pixels in the region RB10. Is the area to which In this way, each pixel block has a shared area between adjacent pixel blocks on the image. The width of the pixel block in the X direction (the horizontal direction in the figure) is the number of pixels to be subjected to image processing. For example, the width of the pixel block 202 in the X direction is the sum of the width 204 of the shared region LB10, the width 205 of the non-shared region B10, and the width 206 of the shared region RB10. The width in the Y direction is in accordance with the encoding unit. For example, when JPEG encoding is performed, the encoding unit is 8 pixels × 8 lines, so it may be 8 lines, as shown in FIG. As shown, it may be N times the number of lines in the encoding unit 210.

  In this embodiment, when one pixel block is encoded, each of the left shared area, the right shared area, and the non-shared area in the pixel block is separately encoded and managed on the memory. Address information on the memory of the encoded data is generated. FIG. 1A shows a map on the memory when the encoded data of each pixel block is stored on the memory.

  The encoded data (Block 00, 10, 20, 01, 11, 21) of each pixel block is encoded data LD in the left shared area, encoded data D in the non-shared area, encoded data RD in the right shared area, It is composed of Thus, the encoded data LD of the left shared area, the encoded data D of the non-shared area, and the encoded data RD of the right shared area are stored in the continuous memory area on the memory, and these encoded data LD, D, and RD constitute encoded data of one pixel block. If these encoded data LD, D, and RD can be managed collectively as encoded data of one pixel block, the arrangement order of the encoded data of each pixel block on the memory is particularly It is not limited. In the present embodiment, since the pixel block is variable-length encoded according to the JPEG encoding method, variable-length encoded data is obtained for each pixel block.

  Next, FIG. 1B shows a configuration example of an address table for specifying each encoded data on the memory. Address 00 is address information corresponding to the encoded data Block 00 of the pixel block 00, and Address 10 is address information corresponding to the encoded data Block 10 of the pixel block 10. As described above, an address table including address information for each encoded data of the pixel block is stored on the memory. The address information for the encoded data of one pixel block includes the encoded data of the pixel block, the encoded data of the left shared area, the encoded data of the right shared area, and the encoded data of the left shared area on the memory. The start address and the data size are described.

  For example, BA in Address 00 indicates the start address on the memory of the encoded data Block 00 of the pixel block 00, and BS indicates the data size of the encoded data Block 00 of the pixel block 00. LA is the top address on the memory of the encoded data LD in the left shared area of the pixel block 00, and LS is the data size of the encoded data LD in the left shared area of the pixel block 00. RA is the start address on the memory of the encoded data RD in the right shared area of the pixel block 00, and RS is the data size of the encoded data RD in the right shared area of the pixel block 00.

  Note that in order to reduce the data size of the address table, the start address BA and the start address LA match, so one of them may be deleted. Each head address may be expressed by an offset address from the head address LA or the head address BA. Thus, the configuration example of the address table is not particularly limited. In this embodiment, each address information has a fixed length and is sequentially arranged in a fixed area on the memory. When the arrangement position of each address information is always fixed, the address information may be compressed or may not be arranged continuously.

  3 is a functional block diagram of the image processing apparatus according to the present embodiment, and FIG. 4 is a flowchart of processing performed by the image processing apparatus according to the present embodiment. An image processing method performed by the image processing apparatus will be described.

  The input unit 300 receives a still image or an image of each frame constituting a moving image. The input unit 300 divides the input image (still image or image for one frame) into several vertically divided images as described above, and sequentially sends the divided vertically divided images to the block conversion unit 301 at the subsequent stage. . Since the processing after step S400 is processing for one vertically divided image, the processing according to the flowchart of FIG. 4A is performed for each vertically divided image.

  In step S400, when the line data for each line is input from the input unit 300, the block conversion unit 301 stores it in the line buffer managed by itself. Then, when the line data for the specified number of lines is stored in the line buffer, the block conversion unit 301 divides the line data for the specified number of lines for each encoding unit by the compressor 302, and each of the divided encoding units Are sequentially sent to the compressor 302. In the present embodiment, since the compressor 302 is described as a JPEG encoder, the compressor 302 performs encoding in units of 8 pixels × 8 lines. However, when the block conversion unit 301 detects that the line data for 8 lines has been stored in the line buffer, the block conversion unit 301 divides the line data for 8 lines into pixel blocks of 8 pixels × 8 lines. The pixel blocks are sequentially sent to the compressor 302.

  At that time, the block conversion unit 301 sets a flag value for each pixel in the pixel block to be transmitted. This flag value takes a value indicating any one of “pixels belonging to the left shared area”, “pixels belonging to the non-shared area”, and “pixels belonging to the right shared area”. The block conversion unit 301 identifies the position of the transmitted pixel in the pixel block by counting each time the pixel in the pixel block is transmitted, and the transmitted pixel is a non-shared area, a left shared area, It is determined to which of the right shared area it belongs. If the transmitted pixel is a pixel belonging to the left shared area, a flag value “0” indicating “a pixel belonging to the left shared area” is set for this pixel. If the transmitted pixel is a pixel belonging to the non-shared area, a flag value “1” indicating “a pixel belonging to the non-shared area” is set for this pixel. If the transmitted pixel is a pixel belonging to the right shared area, a flag value “2” indicating “a pixel belonging to the right shared area” is set for this pixel. Then, the block conversion unit 301 sends the flag value for this pixel to the compressor 302 in association with the sent pixel.

  Thereby, the compressor 302 refers to the flag value of each pixel in the pixel block, whether each pixel in the pixel block belongs to the left shared area, the non-shared area, or the right shared area. Can be determined. That is, this flag value excludes the pixel block from the first rectangular pixel block including the leftmost vertical line, the second rectangular pixel block including the rightmost vertical line, and the first and second rectangular pixel blocks. The remaining third rectangular pixel block is divided into three.

  Since the input to the compressor 302 is in the line direction, the pixel block usually has necessary pixels in the order of the left shared area, the non-shared area, and the right shared area. However, in step S401, the compressor 302 refers to the flag value for each pixel, forms a first rectangular pixel block composed of pixels belonging to the left shared area, and performs JPEG encoding with this first rectangular pixel block as one MCU. By doing so, a first encoded rectangular pixel block is generated. Then, the compressor 302 sends the generated first encoded rectangular pixel block to the subsequent WDMAC 303.

  Next, in step S402, the compressor 302 refers to the flag value for each pixel, configures a third rectangular pixel block including pixels belonging to the non-shared area, and uses the third rectangular pixel block as one MCU to perform JPEG encoding. To generate a third encoded rectangular pixel block. Then, the compressor 302 sends the generated third encoded rectangular pixel block to the subsequent WDMAC 303.

  Next, in step S403, the compressor 302 refers to the flag value for each pixel, configures a second rectangular pixel block composed of pixels belonging to the right shared area, and uses the second rectangular pixel block as 1 MCU to perform JPEG encoding. To generate a second encoded rectangular pixel block. Then, the compressor 302 sends the generated second encoded rectangular pixel block to the subsequent WDMAC 303.

  In step S404, the WDMAC 303 receives the encoded data for one pixel block, that is, the first to third encoded rectangular pixel blocks transmitted in steps S401 to S403. Is stored in the memory 304. The arrangement example of the encoded data for one pixel block on the memory 304 is as described above with reference to FIG. In addition, when each of the pixel blocks 201, 202, and 203 is encoded to generate encoded data Blocks 00, 10, and 20, the respective encoded data are stored side by side on the memory 304 as shown in FIG. To do. Thus, the pixel blocks to be written are stored successively in the line scanning direction.

  In step S404, the WDMAC 303 further obtains the data size (number of bytes) of each encoded rectangular pixel block and the head address of each encoded rectangular pixel block on the memory 304, and generates address information. Thereby, address information for encoded data for one pixel block can be generated.

  In step S405, the WDMAC 303 stores the address information generated in step S404 in the memory 304. An arrangement example of the address information for the encoded data for one pixel block on the memory 304 is as described above with reference to FIG. When the address information corresponding to each of the pixel blocks 201, 202, and 203 is Address 00, 10, and 20, as shown in FIG. 1 (b), the respective address information is stored in the memory 304 with the respective encoded data. Store side by side. As described above, the address information to be written is continuously stored in the order of the line scanning direction.

  Then, if the processes in steps S400 to S405 have been performed for all the pixel blocks constituting the vertically divided image, the process according to the flowchart of FIG. On the other hand, if there remains a pixel block that has not been subjected to the processes in steps S400 to S405, the processes in and after step S400 are performed on this pixel block.

  The RDMAC 305 operates when encoded data of two or more pixel blocks is stored in the memory 304. In step S410, the RDMAC 305 obtains address information of the target pixel block, address information of the pixel block adjacent to the left of the target pixel block, and address information of the pixel block adjacent to the right of the target pixel block from the address table in the memory 304. read out. For example, the address table is as shown in FIG. 1B, and the pixel block of interest is the pixel block 00. In this case, Address 00, Address 10, Address 20 are read from the memory 304.

  In step S411, the RDMAC 305 reads the head address RA and the data size RS from the address information of the pixel block adjacent to the left of the pixel block of interest. Then, the RDMAC 305 reads data in the area corresponding to the data size RS from the head address RA in the memory 304 as encoded data RD in the right shared area of the pixel block adjacent to the left of the pixel block of interest. In the example of FIG. 2A, when the pixel block of interest is the pixel block 202, the head address RA and the data size RS in the address information Address00 of the pixel block 201 are read. Then, in the memory 304, the data in the area corresponding to the data size RS from the head address RA is read as the encoded data RD of the right shared area of the pixel block adjacent to the left of the pixel block of interest. Then, the RDMAC 305 transmits the read encoded data RD to the decompressor 306.

  In step S412, the RDMAC 305 reads the head address BA and the data size BS from the address information of the pixel block of interest. Then, the RDMAC 305 reads data in the area corresponding to the data size BS from the head address BA in the memory 304 as encoded data of the pixel block of interest. In the example of FIG. 2A, when the pixel block of interest is the pixel block 202, the head address BA and the data size BS in the address information Address10 of the pixel block 202 are read. Then, in the memory 304, the data in the area corresponding to the data size BS from the head address BA is read as the encoded data Block10 of the pixel block 202. Then, the RDMAC 305 sends the read encoded data to the decompressor 306.

  In step S413, the RDMAC 305 reads the head address LA and the data size LS from the address information of the pixel block adjacent to the right of the pixel block of interest. Then, the RDMAC 305 reads data in the area corresponding to the data size LS from the head address LA in the memory 304 as encoded data LD in the left shared area of the pixel block adjacent to the right of the pixel block of interest. In the example of FIG. 2A, when the pixel block of interest is the pixel block 202, the head address LA and the data size LS in the address information Address20 of the pixel block 203 are read. Then, in the memory 304, data in the area corresponding to the data size LS from the head address LA is read as encoded data LD in the left shared area of the pixel block adjacent to the right of the pixel block of interest. Then, the RDMAC 305 transmits the read encoded data RD to the decompressor 306.

  In step S414, the decompressor 306 decompresses each encoded data transmitted from the RDMAC 305 in steps S411 to S413, and generates line data. That is, the encoded data in the right shared area of the pixel block adjacent to the left of the pixel block of interest is expanded (second expansion) to generate line data of the right shared area of the pixel block adjacent to the left of the pixel block of interest. To do. Also, the encoded data of the pixel block of interest is expanded (first expansion) to generate line data of the pixel block of interest. Also, the encoded data of the left shared region of the pixel block adjacent to the right of the pixel block of interest is expanded (third expansion) to generate line data of the left shared region of the pixel block adjacent to the right of the pixel block of interest. To do. Each line data generated in this way is stored in a line buffer in the line conversion unit 307. In the example of FIG. 2A, when the target pixel block is the pixel block 202, line data of the right shared region RB00, the left shared region LB10, the non-shared region B10, the right shared region RB10, and the left shared region LB20 is generated. And stored in the line buffer.

  In step S415, the line conversion unit 307 stores the line data obtained by decompressing the respective encoded data received by the decompressor 306 in steps S411 to S413 in the line buffer, and transfers the stored line data to the image processing unit 308. To do. In the example of FIG. 2A, when the pixel block of interest is the pixel block 202, each line data of the right shared region RB00, the left shared region LB10, the non-shared region B10, the right shared region RB10, and the left shared region LB20 is an image. Transferred to the processing unit 308.

  Then, if the processing of steps S410 to S415 has been performed for all the pixel blocks constituting the vertically divided image, the processing according to the flowchart of FIG. On the other hand, if there remains a pixel block that has not yet been subjected to the processing of steps S410 to S415, the processing after step S410 is performed on this pixel block.

  Thus, for example, when performing image processing on a certain line in the pixel block 202, the image processing unit 308 requires a pixel in the right shared area RB00 to refer to a pixel in the right shared area RB00. The line data may be referred to. Further, when image processing is performed for a certain line in the pixel block 202, the line data in the left shared area LB20 may be referred to for a pixel that needs to refer to a pixel in the left shared area LB20 in this line. .

  When the image processing for one line is completed, the image processing unit 308 stores the image-processed line data in a line buffer included in the block conversion unit 301 '. The block converter 301 ′ performs the same operation as the block converter 301, the compressor 302 ′ performs the same operation as the compressor 302, and the WDMAC 303 ′ performs the same operation as the WDMAC 303. As a result, the encoded data for each pixel block that has undergone image processing is stored in the memory 304. Note that the block conversion unit 301 ′ does not need to set the flag value as described above again when image processing using peripheral pixels is not performed thereafter.

  In step S420, the RDMAC 310 reads address information for the pixel block (target pixel block) to be read from the memory 304. In step S421, the RDMAC 310 refers to the head address BA and the data size BS in the read address information, and reads data for the data size BS from the head address BA in the memory 304 as encoded data of the target pixel block. Then, the RDMAC 310 sends the encoded data of the read target pixel block to the decompressor 306 '.

  In step S422, the decompressor 306 'decompresses the encoded data of the target pixel block sent from the RDMAC 310 to generate the target pixel block, and sends the generated target pixel block to the line conversion unit 307'. The line conversion unit 307 ′ forms the entire image in units of pixel blocks by arranging the pixel block received from the decompressor 306 ′ this time adjacent to the already decompressed pixel block in the memory managed by the line converter 307 ′. . However, if the RDMAC 310 has read the encoded data of all the pixel blocks, that is, if all the pixel blocks have been expanded and placed in the line conversion unit 307 ', the process proceeds to step S424. On the other hand, when the encoded data of the pixel block that RDMAC 310 has not yet read out remains in memory 304, the process returns to step S420. And the process after step S420 is performed about the coding data of the pixel block which has not been read from the memory 304 yet.

  In step S424, the line conversion unit 307 'sends the completed image to the output unit 309. The sending unit is not particularly limited, and may be sent for each line data, or the entire image may be sent at once. The output unit 309 outputs this image to a display device, a storage device, a printing device, or the like. Of course, the output destination is not particularly limited.

  If it is necessary to repeat the above processing, for example, if it is necessary to repeat the above processing for the image of the next frame, the processing returns to step S420, and the processing after step S420 is performed for the next image. .

  Note that the image processing apparatus having the configuration shown in FIG. 3 may be configured by one apparatus or a plurality of apparatuses. For example, the input unit 300, the block conversion unit 301, the compressor 302, the WDMAC 303, and the memory 304 may be configured by a single encoding device. In addition, the memory 304, the RDMAC 305, the decompressor 306, the line converter 307, the image processor 308, the block converter 301 ', the compressor 302', and the WDMAC 303 'may be configured by one image processing apparatus. Further, the memory 304, the RDMAC 310, the decompressor 306 ', the line conversion unit 307', and the output unit 309 may be configured by one decoding device. The same applies to the following embodiments.

  As described above, according to the present embodiment, when processing a pixel block, only the compressed data of the shared pixel can be accessed from the adjacent block, so that unnecessary pixel reading is eliminated and the memory bandwidth is reduced. Can do.

[Second Embodiment]
A configuration example of the image processing apparatus according to the present embodiment will be described with reference to the block diagram of FIG. In FIG. 5, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The image processing unit A 510 performs the same processing as the image processing unit 308, and when the image processing for one line is completed, the image processed line data is stored in a line buffer included in the block conversion unit 512.

  Similarly to the block conversion unit 301, the block conversion unit 512 outputs a pixel block and sets and outputs a flag value for each pixel in the pixel block. Is changed to the size for the image processing unit B511. For example, the size (number of pixels) in the X direction of the shared area is changed from 16 pixels to 32 pixels.

  The block conversion unit 512, the compressor 302 ″, and the WDMAC 303 ′ perform processing in accordance with the flowchart of FIG. 6. In the flowchart of FIG. 6, the same steps as those shown in FIG. They are numbered and will not be described.

  In step S600, the block conversion unit 512 changes (updates) the size of the shared area. That is, after the line data group sent from the image processing unit A 510 is divided for each pixel block, each pixel block has a shared area of this updated size. Reset the flag value.

  In FIG. 5, the image processing unit B <b> 511 performs image processing using the pixel block received from the line conversion unit 307 ′ to perform processing on the pixel of interest using its surrounding pixels. Then, when the image processing for one line is completed, the image processing unit B511 stores the image-processed line data in the line buffer included in the block conversion unit 301 ″.

  The block conversion unit 301 ″ performs the same operation as the block conversion unit 301, the compressor 302 ″ performs the same operation as the compressor 302, the WDMAC 303 ″ performs the same operation as the WDMAC 303, and the RDMAC 310 ″ and the RDMAC 310. The expansion unit 306 ″ performs the same operation as the expansion unit 306, and the line conversion unit 307 ″ performs the same operation as the line conversion unit 307.

  As described above, according to the present embodiment, even when the number of reference pixels is reduced in the middle of image processing, a change is made by changing the start address and data size of the encoded data in the shared area in the address information. Therefore, there is no need to change the address information read control.

[Third Embodiment]
Each unit shown in FIGS. 3 and 5 may be configured by hardware, or a part may be configured by software. For example, the input unit 300 and the output unit 309 may be configured by an I / F (input / output interface), the memory 304 may be configured by a RAM, and the other units may be implemented by a computer program. In this case, the computer program is installed in a computer having the I / F and RAM, and then the computer program is executed by the CPU of the computer. As a result, the computer executes the processes described as being performed by the image processing apparatus.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (7)

A first partial pixel block including a pixel in the pixel block referred to in image processing for a left pixel block adjacent to the left side of the pixel block; a right adjacent to the right side of the pixel block; second fractional pixel block, the remainder of the pixel block from the pixel block omitting the first portion pixel block and a second portion pixel block including the pixel in the pixel block to be referenced by the image processing for the pixel block Means for dividing the third partial pixel block of the third partial pixel block,
The first partial pixel block, the second partial pixel block, and the third partial pixel block are individually encoded to obtain a first encoded partial pixel block, a second encoded partial pixel block, An image processing apparatus comprising: encoding means for generating a third encoded partial pixel block and storing it in a memory. The encoding means individually performs variable-length encoding on each of the first partial pixel block, the second partial pixel block, and the third partial pixel block, whereby the first code The image processing apparatus according to claim 1, wherein the encoded partial pixel block, the second encoded partial pixel block, and the third encoded partial pixel block are generated. Furthermore,
First expansion means for expanding the first encoded partial pixel block, the second encoded partial pixel block, and the third encoded partial pixel block of the pixel block of interest;
Second decompressing means for decompressing said second coded portion pixel block of the pixel block adjacent to the left side of the target pixel block is read out from said memory,
A third decompression means for decompressing said first coded portion pixel block of the pixel block adjacent to the right side of the target pixel block is read out from said memory,
The image processing for the pixel block of interest obtained by the expansion by the first expansion means is performed on the second partial pixel block expanded by the second expansion means and the first expanded by the third expansion means. The image processing apparatus according to claim 1, further comprising: an image processing unit that uses one partial pixel block.   The image processing apparatus according to claim 3, wherein the image processing is JPEG encoding processing. Furthermore,
Start address and data size of the first encoded partial pixel block in the memory, start address and data size of the second encoded partial pixel block in the memory, and the third encoded partial pixel block in the memory 5. The image processing apparatus according to claim 1, further comprising a storage unit configured to store the first address and data size of the first address and the data size in the memory as address information for the pixel block. An image processing method performed by an image processing apparatus,
Said dividing means of the image processing apparatus, a pixel block including a plurality of pixels, the first portion pixel block including the pixels in the pixel block to be referenced by the image processing for the left pixel block adjacent to the left side of the pixel block, A second partial pixel block including a pixel in the pixel block referred to in image processing on the right pixel block adjacent to the right side of the pixel block, and the first and second partial pixel blocks are omitted from the pixel block; a step of dividing the remaining third part pixel block is a partial pixel block, of the three portions pixel block,
The encoding means of the image processing device individually encodes each of the first partial pixel block, the second partial pixel block, and the third partial pixel block to generate a first encoded partial pixel block And an encoding step of generating a second encoded partial pixel block and a third encoded partial pixel block and storing them in a memory. A computer program for causing a computer to function as each unit of the image processing apparatus according to any one of claims 1 to 5 .

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