JP2000215183A - Memory port arbitrating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To support different kind of processors connected to memory arrays and input/output devices by assigning priority to respective devices. SOLUTION: Each processor is equipped with a memory control unit(MCU) 50, connected to a cache control unit(CCU) 49 equipped with a data cache (D cache) 51 and an instruction cache (I cache) 52, and an input/output port 53. An MPU 50 is equipped with an interface and as switch network 54. The switch network 54 receives instructions and data requests from the CCU 49. A switch arbitration unit 58 assigns priority to the requests and passes the requests to corresponding port interfaces p0 to pN or the interface according to the addresses added to the requests.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to microprocessor architectures and, more particularly, to microprocessor architectures.
A microprocessor architecture capable of supporting multiple heterogeneous microprocessors.

[0002]

BACKGROUND OF THE INVENTION The U.S. patent applications listed below are U.S. patent applications pending and pending at the same time as the present patent application, but are disclosed in these U.S. patent applications and filed in corresponding applications. The matters disclosed in a patent application in Japan are incorporated herein by reference in their application numbers. 1. Title of invention "High performance RISC microprocessor
Architecture ”(High-Performance)
RISC Microprocessor Arch
item) SMOS-7984MCF / GB
R, US patent application Ser. No. 07 / 727,006, 1991.
Filed on July 8, 2012, filed by the inventor Le T. Nguyen et al. And Japanese Patent Application No. 5-502150 (Japanese Patent Application No.
-501122). 2. Title of the Invention "Extensible RISC Microprocessor Architecture"
Microprocessor Architect
ure) SMOS-7985MCF / GBR, U.S. patent application Ser. No. 07 / 727,058, filed Jul. 8, 1991, inventor LeT. Nguyen et al. And corresponding Japanese Patent Application No. 5-502153 (Japanese Patent Application No. 6-50112).
No. 4). 3. "RISC with isolated architectural dependencies
Microprocessor Architecture ”(RISC M
microprocessor Architecture
e with Isolated Architecture
ura Dependencies) SMOS-798
7MCF / GBR / RCC, U.S. Patent Application No. 07/72
No. 6,744, filed on Jul. 8, 1991, inventor Le
T. Nguyen et al. And corresponding Japanese Patent Application No. 5-
502152 (Japanese Unexamined Patent Publication No. 6-50203). 4. Title of Invention "R Using Multiple Register Set"
ISC Microprocessor Architecture ”(RIS
C Microprocessor Architectec
cure Implementing Multipl
e Typed Register Sets) SMOS
-7988MCF / GBR / RCC, US Patent Application No. 0
No. 7 / 726,773, filed on Jul. 8, 1991, inventor Sanjiv Garg et al., And corresponding Japanese Patent Application No. 5-502403 (Japanese Patent Application No. 6-501805). 5. Title of the Invention "RISC Microprocessor Architecture Implementing Fast Traps and Exception Conditions" (RISC Microprocessor Arc)
hittture Implementing Fa
St Trap Exception Stat
e) SMOS-7789MCF / GBR / WSW, U.S. Patent Application Serial No. 07 / 726,942, July 8, 1991.
Filed by the inventor Le T. Nguyen et al. And Japanese Patent Application No. 5-502154 corresponding thereto (Japanese Patent Application No. 6-502).
No. 035). 6. Title of Invention "Single Chip Page Printer Controller" (Single Chip Page)
Printer Controller) SMOS-
7991MCF / GBR / HKW, US Patent Application No. 07
/ 726,929, filed on July 8, 1991, inventor Derek J. et al. Lentz et al. And Japanese Patent Application No. 5-502149 corresponding thereto (Japanese Patent Application Publication No. 6-501586).

[0003] The description in this specification is based on the description in the specification of US Patent Application No. 07 / 726,893, which is a priority document of the present application. The contents of the description of the United States patent application form a part of the present specification. 2. Description of the Related Art A computer system having a microprocessor architecture that can support multiple processors,
A memory, a memory system bus including a data bus, an address bus, and a control signal bus; an input / output (I / O) bus including a data bus, an address bus, and a control signal bus; Typically, it comprises a device and a plurality of microprocessors. The input / output device is, for example, a direct memory access (DM
A) Controller processor, Ethernet (ETH)
ERNET) chip and various other input / output devices. The microprocessor includes, for example, a plurality of general-purpose processors and a special-purpose processor. These processors are connected to memory via a memory system bus and to input / output devices via an input / output bus.

[0004]

A mechanism for assigning priorities (priorities) to a processor and an input / output device when these processors access an MAU or an input / output device so as not to cause access collision. It is necessary to adopt (method). The priority scheme includes
There are a fixed priority system, a dynamic priority system in which the priority can be changed during processing (on the fly) when the system conditions change, or a combination of both systems. This type of priority scheme minimizes memory and I / O device latency while at the same time maintaining cache coherency (c
It is also important that all processors have easy access to memory and input / output devices in a manner that preserves the cache coherency. For example, using the system bus repeatedly to access a rejected semaphore can greatly reduce the bandwidth of the system bus. Without precautionary measures taken to ensure that cache coherency is not compromised, multiple processors cannot read and write the same data separately.

[0005]

In view of the above problems,
A primary object of the present invention is a microprocessor architecture capable of supporting a plurality of heterogeneous processors connected to a plurality of memory arrays and a plurality of I / O devices via one or more I / O buses. It is to provide a computer system configured.
The memory array is a memory array unit (Mem).
or Array Array-MAU)
Grouped into subsystems with interface circuits. Each of these processors includes a new memory control unit (Memory ControlI Uni).
t-MCU). Each of the MCUs comprises a switch network, the switch network comprising a switch arbitration unit, a cache interface circuit for data, a cache interface circuit for instructions,
I / O interface circuit, and one called port
It comprises one or more port interface circuits, each of which comprises a port arbitration unit.

[0006] The switch network is a master (ma
(ster) device and a slave device. When viewed from the switch side, a master device can be a D-cache, an I-cache, or an input / output controller unit (IOU), and a slave device can be a memory port or an IOU. .

The function of the switch network is to provide various instruction and data requests to a cache controller unit (CCU) (I-cache, D-cache) and I-cache.
OU. Upon receiving these requests, the switch arbitration unit in the switch network and the port arbitration unit in the port interface circuit prioritize the request and deliver the request to the appropriate memory port (this depends on the instruction address). ).
Thereafter, the port, and possibly multiple ports, generate the necessary timing signals and send and receive the necessary data to and from the MAU. When it is a write (WR) request,
In the exchange between the port and the switch, the switch pushes all the write data and the write data FIFO (W
It stops when it finishes putting into DF). If it is a read (RD) request, the exchange between the switch and the port ends only when the read data is sent back from the port via the switch to the requesting master.

[0008] The switch network consists of four sets of tri-state buses through which the cache, IOU, and memory ports are connected. The four sets of tri-state buses are SW_RE
Q, SW WD, SW RD and SW_IDBST. In an exemplary embodiment of the present invention, the bus SW REQ is composed of 29 wires,
ID and shared signal from master device to slave
Used to send to device. The ID is a tag attached to the memory request and enables the requesting device to associate the returned data with the correct memory address. The shared signal is a signal indicating that the memory access is to the shared memory. When the master device issues a request to the slave, it is not necessary to send the entire 32 bits of the address on the switch. This is because in a multiple memory configuration, the switch can decode the address and determine if the request is for memory port 0, port 1, IOU, and so on. Each port is assigned a pre-defined memory space, so SW Address 3 on REQ
There is no need to transmit all two bits.

In actuality, for example, other required attributes such as a function code and a data width attribute have a timing limitation, Not sent on REQ. If information is sent via the switch, it arrives at the port one phase later than necessary, further increasing the latency for memory requests. Thus, since this type of request attribute is sent to the port on a dedicated wire, the port can start its state machine earlier, reducing memory latency.

As shown in FIG. 8, the bus SW_WD is 32
It consists of a single wire and is used to send write data from the master device (D-cache and IOU) to the FIFO via the memory port. Clearly,
The I-cache only reads data and does not write data. This three-state bus is a "double pump"
(Doublepumped). That is, the data words are transferred in each clock phase, thus requiring fewer wires and thus saving circuit cost. WD00, WD01, WD10 and WD11
Is a data word. Because these buses are double-pumped, care must be taken to prevent bus collisions when the bus loops and switches from one master to another.

[0011] As shown in FIG. RD is 64
Consists of a book wire and is used to send return read data from the slave device (memory port and IOU) back to the master device. Data is transmitted only during phase one. This bus is not double-pumped because of timing constraints on the cache, which requires that the data be valid on the falling edge of CLK1. Data is clock 1 high
When the SW_RD bus is to be double-pumped, the earliest time the cache gets data is CLK1
Is a positive edge, not a negative edge. Bus SW_R
Since D is not double pumped, this bus is only active during phase 2 (not tri-state). When the bus switches to another master, the problem of bus driver collision does not occur.

The bus SW_IDBST is composed of four wires and is used to transmit an identification number (ID) from the master device to the slave device, and to transmit an ID and a bank start signal from the slave device to the master device.

According to an embodiment of the present invention, the ID FIFO
Has only one for each slave device. Since the data from the slave device is always returned in order,
Need not be sent to the port. ID is the F-type for each port at the interface between the switch and the master device.
The data can be stored in separate FIFOs provided with one IFO. For this reason, if there are n ports, n FIFOs are required for each interface, so that the circuit area increases as compared with this embodiment, but the number of three-state wires can be reduced by two.

A port interface is a switch
This is an interface that connects a network and an external memory (MAU). The interface comprises a port arbitration unit and means for storing requests that cause intervention and interrupted read requests. Also, a snoop address generator (snoopaddress generator)
tor). In addition, the interface also includes circuitry that acts as a signal generator to generate the correct timing signals to control the memory module.

The devices in the switch network of the present invention, for example, a content address memory (content)
Some algorithms are implemented in the addressable memory (CAM), the row match comparison circuit, and the switch / port arbitration circuit.

The architecture of the present invention incorporates a semaphore. Semaphores are used to synchronize software in a multiprocessor system with "test and set" instructions, as described below. In the architecture of the present invention, semaphores are not cached. The cache fetches a semaphore from the MCU when the CPU executes a "test and set" instruction.

Test and set bypass circuits include:
When a spin lock occurs, that is, a repetitive request
A simple algorithm has been implemented to prevent loss of memory bandwidth when accessing the AU system bus to obtain a semaphore. When a test instruction is executed on a semaphore that locks a memory area, device, or the like, the CAM stores the semaphore address. This entry in the CAM is cleared when any processor writes to a portion of memory surrounding the semaphore. If the requested semaphore is still in the CAM, there is no need to actually access memory to obtain the semaphore, since the semaphore has not been released by any processor. Instead, a logic 1 block ($ FFFF)
(Semaphore failure) is sent back to the requested cache, indicating that the semaphore is still locked.
Therefore, the semaphore is not actually accessed,
Memory width will be saved.

When a value other than "1" is written in the semaphore, the semaphore is cleared. In that case, the slave side CP
U must examine the shared memory to see if any CPU (including itself) has written to the semaphore. If any CPU is writing to a semaphore that matches an entry in the CAM,
That entry in the AM is cleared. The next time the cache tries to access the semaphore, the entry is not in the CAM, so the semaphore is actually fetched from main memory and "failed", that is,
All will be set to 1.

The function of the row match comparison circuit is to determine whether the current request has the same row address as the previous request. If so, the port cancels the RAS request (de-assert) and returns the pre-RAS charging (pr
e-charge) There is no need to incur a time penalty. Thus, the memory latency is reduced and the available bandwidth is increased. Row match is used primarily in dynamic random access memories (DRAMs), but there is no longer a need to latch the MAU to the upper bits of the new address, so static random access memories (SRAMs) and read-only Memory (ROM)
But it can be used. Thus, when there is a memory access request, the address is transmitted on the switch network address bus SW_REQ, and the row address is decoded and stored in the MUX latch. If this address is determined to be the row address of the previous request, when the cache or IOU issues a new request, the address associated with the new address is decoded and the row address is compared to the previous row address. If there is a match, then a row match has been hit, and the matching request is given priority as described below.

In the dynamic switch / port arbitration circuit, two types of arbitration are performed. One is the memory port resources,
That is, port 0. . . Port N arbitration, another one
One is the arbitration of the switch network address and write data bus resources, SW_REQ and SW_WD.

Some devices can simultaneously request data from main memory. The devices are a D cache, an I cache, and an IOU.
The priority scheme that gives each master a specific priority is:
A device with a high "importance" or "urgency" is set up to receive service as soon as possible. However, strict fixed arbitration schemes have not been used because they could lock out lower priority devices.
Instead, a dynamic arbitration scheme has been used that assigns different priorities to various devices on the fly. The following factors influence the dynamic arbitration system.

1. 1. The unique priority of the device 2. Does the requested address match the line with the previously serviced request? 3. Has the device been denied service too many times? Has the master been serviced too many times? Each request from a device has its own priority. I
OU has the highest priority, followed by I-cache and D-cache.
A cache follows. However, as described below, intervention from the D-cache (intervention-ITV)
The request is sent to the slave side processing element (processi
ng element-PE) needs to receive the updated data as soon as possible, so it has the highest priority of all.

The intrinsic priority of various devices is changed by several factors. The number of times a lower priority device is denied service is monitored, and when that number reaches a predetermined value, the lower priority device is given higher priority. In contrast, the number of times a device is given a priority is also monitored, and if only that device is “hog” the bus, the priority is rejected and a lower priority device takes over the bus. Allow access. The third factor used to change the unique priority of a request is row match
h). Line matching is important mainly in the case of I-cache. If a device requests a memory location with the same row address as a previously serviced request, the requesting device is given a higher priority. This is done by canceling the RAS request (de-a
sert), re-request RAS (re-asser)
t) To save labor. Each time a row matches and the request is serviced, the programmable counter is decremented. For example, when the counter reaches zero,
The row match priority bit is cleared, giving the new master access to the bus. When the port's new master is different from the old master, or when the request is not a row-matched request, the programmable value is again pre-loaded into the counter.

A write request to the memory port is sent to the switch network write data bus (SW_W).
Only allowed when D) is available. If not available, the request is selected, if any. There is one exception. It is an intervention (ITV) request from the D-cache. If such a request exists, S
If the W_WD bus is not available, no requests will be selected. Instead, the system is SW Wait until the WD bus is released before allowing the intervention request.

The switch network employs two software selectable arbitration schemes. The method is as follows.

1. Slave priority scheme. In this scheme,
Priority is given based on the slave or requested device (ie, memory or IOU port).

2. Master priority scheme. In this scheme, priority is given based on the master or requesting device (ie, IOU, D-cache, I-cache).

In the slave priority scheme, the priority is always the first memory port, eg, port 0, 1, 2,. . .
, And then to the IOU and back to port 0 again. This method is generally called a round-robin method. The master priority scheme is a fixed priority scheme, where the priority is first given to the IOU and then to the D-cache and the I-cache. In the master priority scheme of switch arbitration, intervention (ITV) requests may be given the highest priority. When the prefetch buffer eventually becomes empty, the I-cache may be given the highest priority.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the microprocessor architecture according to the present invention, designated generally by the reference numeral 1. The architecture 1 includes a plurality of general-purpose microprocessors 2, 3, 4,. . . N, special-purpose processor 5, orbiter (arbitration circuit) 6, and memory / memory
An array unit (MAU) 7 is provided. The microprocessors 2 to N can be constituted by a plurality of similar processors or a plurality of heterogeneous processors. The special purpose processor 5 can be constituted by a graphic controller, for example. All of the processors 2 to 5 have one or more memory ports PORT _O ...
It is connected to MAU system bus 25 via PORT _N. The MAU system bus 25 includes a MAU data bus 8, a ROW / COL address bus 9, a multiprocessor control bus 10, a MAU control bus 11, and a bus arbitration control signal bus 12. It is tied at 17. Bus 12 is used, for example, to request access arbitration, grant access, or signal that MAU data bus 8 is busy. The orbiter 6 is connected to the bus 12 via a bidirectional signal line 18.
MAU 7 is connected to a ROW / COL address bus 9 and a memory control bus 11, from which signals are transferred to the MAU via unidirectional signal lines 19 and 20, and via a bidirectional data bus 21. MAU data
Transferred to bus 8. Data buses 8 and 21 are typically 64-bit buses, but may operate as 32-bit buses under software control. This bus can have other bit widths, for example, 128 bits.

Each of the processors 2 to N typically includes:
An input / output IOU interface 53 is provided. This interface 53 is described in detail below with reference to FIG.
A plurality of peripheral input / output devices, such as an Ethernet (ETHERNET) interface 31, and other input / output devices, a 32-bit input / output bus 33 or an optional 32-bit input / output bus 34 and a plurality of 32-bit bidirectional signal buses 35; Through 42. Optional I / O bus 34 may be used by one or more of the processors to access special purpose I / O device 43.

As shown in FIG. 2, each of the processors 2-N has a memory connected to a cache control unit (CCU) 49 having a data cache (D cache) 51 and an instruction cache (I cache) 52. A control unit (MCU) (entirely indicated by reference numeral 50) and an input / output port 53 are provided. The input / output port 53 may be abbreviated as IOU below, but is connected to the input / output bus 33 or 34.

The MCU 50 includes a CCU 49, that is, a D cache 51 and an I cache 52 (read only), an IOU
Data and instructions are transferred (read and written) between the MAU 53 and the MAU 7 via the MAU system bus 25. The MCU 50 has a cache coherency, as described in more detail below.
y). This cache persistence means that the MCU in each slave CPU monitors all transactions of the master CPU on the MAU address bus 9, that is, snoops, Is requesting new data from the master CPU or trying to send new data to the master CPU. The MCU 50 is scalable for use with 6 memory ports, and supports up to 4 ways of memory.
Supporting interleaving on MAU data bus 8 can be supported. Also, external 64 or 32 bit
The use of data bus 8 can be supported, using a modified Hamming code to correct one data bit error and detect two or more data bit errors.

In the architecture of the present invention, the size of a cache subblock, or cache line, is a function of the memory bus size. For example,
If the bus size is 32 bits, the sub-block size will typically be 16 bytes. If the bus size is 64 bits, the sub-block size will typically be 32 bytes. If the bus size is 128 bits, the sub-block will be 64 bytes. As described above, MCU 50
Is designed to be programmed to support 1, 2 or 4 way interleaving, ie, the number of bytes transferred per cycle.

The MCU 50 includes one or more interfaces indicated by ports P _O ... P _N , a switch network 54, a D-cache interface 55,
An I-cache interface 56 and an input / output interface 57 are provided. As will be described in detail later with reference to FIG. 3, each of the port interfaces P _{0 to} P _N includes a port arbitration unit indicated by PAU ₀ ‥ PAU _N. The switch network 54 includes a switch arbitration unit 58.

When the MCU 50 is equipped with two or more port interfaces, each of the port interfaces P ₀ -P _N is connected to a separate MAU system bus, see FIG. This is the same as the bus 25 described above. FIG. 2 shows that two such buses are two buses.
5 are indicated by ₀ and 25 _N code. Bus 25 _N is a bus _{8 N, 9 N, 10 N} , 11 N and 12 _N, each of which buses _{13 N, 14 N, 15 N} ,
And it is connected to the port P _N at 16 _N and 17 _N. Buses 8 _N to 17 _N has been described above with reference to FIG. 1 8-17
Is the same as Similarly, each of the port interfaces, write (WR) data buses 60, 60 _N, read (RD) data buses 61 and 61 _N, and a plurality of the same kind individual bus consisting of address bus 62, 62 _N And a plurality of control buses 70, 71, 80, 81, 90, 91 and 70
_N, via a _{71 N, 80 N, 81 N} , 90 N, 91 N are connected to each of the output interface 55, 56, 57 and cache. The suffix _N in the code indicates a bus connecting the port interface _PN with the cache and the input / output interface.

The switch network 54 and the D-cache interface 55 are connected to the WR data bus 72, RD
It is connected via a data bus 73 and an address bus 74. The switch network 54 and the I-cache interface 56 are connected via an RD data bus 82 and an address bus 83. As described above, no write (WR) request is issued from the I-cache 52. The switch network 54 and the input / output interface 57 are connected via a plurality of bidirectional signal buses including an RD data bus 92, a WR data bus 93, and an address bus 94.

D-cache interface 55 and CC
U49, that is, the D cache 51 includes the WR data bus 100, the RD data bus 101, and the address bus 1
02 and a pair of control signal buses 103 and 104 are connected via a plurality of unidirectional signal buses. The I-cache interface 56 and the CCU 49, i.e., the I-cache 52,
It is connected via a bus 111 and a plurality of unidirectional signal buses including a pair of control signal buses 112 and 113.
The input / output interface 57 and the IOU 53 are connected to the R / W-I
/ O master data bus 120, R / W-I / O slave data bus 121, pair of control signal lines 12
3, 124 and a pair of address buses 125, 126 are connected via a plurality of unidirectional signal buses.
The names input / output (I / O) master and input / output (I / O) slave, as described in more detail below, refer to a particular when an input / output operation is being performed as a master or as a slave. It is used to indicate data transmission using a signal line.

[0038] Figure 3 shows the main data path of the switch network 54 is a block diagram showing the connection relationship between the D-cache interface 55 and port interface P _O. Port interface P ₁ −
P _N and I cache and input / output interface 56,
The connection relationship between the 57 is the same, except that no write data request is issued from the I-cache interface 56. As shown in FIG. 3, each of the port interfaces P ₀ -P _N is further granted an ID FIFO (First In First Out) 130 for storing an identification code (ID) of the read request, and access to the MAU. And a read data (RD) FIFO 132 for temporarily storing read data until the network 54 becomes available. Have been.

The switch network 54 has a request / address bus SW_REQ [28: 0],
A plurality of signal buses 140-143, also called write data buses SW_WD [31: 0], read data buses SW_RD [63: 0], and identification / bank start signal buses SW_IDBST [3: 0], and a switch arbitration unit 58 are provided. Switch arbitration unit 58 is intended to handle multiport I / O requests.

The cache and port interfaces switch directly on some signal buses and switch on other signal buses.
Indirectly connected via a network bus. For example, port interface P. .. _PN at each of the port arbitration units PAU
It is connected to the switch arbitration unit 58 via a pair of control signal buses consisting of Oa and REQUEST control lines 71b. Switch arbitration unit 58 is GRANT
It is connected to the D-cache interface 55 via a control signal line 71b. Lines 70a and 70b and lines 71a and 71b are signal lines on the buses 70 and 71 in FIG. Gate 75 and registers 76 and 7
8 are provided for storing the request causing the intervention and for storing the interrupted read request, respectively. The other port, cache, and input / output interface are connected by a corresponding control bus.

The function of the switch network 54 is to send various instructions and data requests to the cache control unit (CC).
U), that is, I cache 51, D cache 52,
And from the IOU 53. Upon receiving these requests, the switch arbitration unit 58 in the switch network 54 takes on one request at a time.
Prioritizes the requests and, depending on the address associated with the request, the corresponding port interface P. ~ P
Pass the request to _N or I / O interface. The port and the input / output interface are selected, for example, by upper bits of the address accompanying the request. Each port
The interface has a register 77 for storing the MAU address. The port interface generates necessary timing signals and exchanges necessary data with the MAU 77. If the request is a WR request, the interaction between the port interface and the switch network 54 stops when the switch pushes all the write data into the WDF (write FIFO) 131. If the request is an RD request, the exchange between the switch network 54 and the port interface ends only when the port interface sends the read data back to the switch network 54.

As described in detail below, a switch
The network 54 is provided for a master device and a slave device to communicate with each other. In this sense, the following can be the master device.

1. D cache 2. 2. I-cache Possible IOU slave devices include:

1. Memory port 2. The IOU switch network 54 is responsible for sending necessary intervention requests to the appropriate port interface for execution.

As described above, the switch network 54 is composed of four sets of tri-state buses for connecting between the cache interface, the input / output interface, and the memory port interface. 4 sets of 3 state buses are SW
_REQ, SW_WD, SW_RD, SW_IDBST
It is. The bus named SW_REQ [28: 0]
It is used to send the address, memory sharing signal and ID of the slave device from the master device to the slave device. As indicated above, the master can be a D-cache, I-cache or IOU
And the slave device can be a memory port or an IOU. When the master device issues a request to the slave, it is not necessary to send all 32 bits of the address on the switch bus SW_REQ. This is because in the multiple memory port structure of the present invention, a predefined memory space is allocated to each port.

Other required attributes such as the function code (FC) and the data width (WD) are not transmitted from the SW_REQ bus due to timing restrictions. Information sent over the switch network 54 arrives at the port interface one clock phase later than if the information was sent over a dedicated wire. Therefore, the initial request attribute (early request attribute)
ute) to the port interface one phase earlier, the port interface can start its state machine earlier, thus reducing memory latency. This is done by another signal line 79, as shown in FIG. Line 79 is one of the lines in control signal bus 70 of FIG.

The SW_WD [31: 0] bus transfers write data from the master device (D cache and IOU) to the WD FIFO1 in the memory port interface.
Used to send to 31. This tri-state bus is double pumped. That is, 32 bits of data are transferred for each phase. Bus is a double pump (doub)
When the circuit is designed, care must be taken to prevent the bus from wrapping around and causing a bus collision when switching from one master to another master. As will be appreciated, double pumping requires fewer bit lines, thereby minimizing the number of expensive wires required and minimizing performance degradation.

As shown in FIG. 9, SW_RD [63:
0] is used to send return read data from the slave device (memory port or IOU) back to the master device. Data is clock phase 1
(When CLK1 is high). This bus is not double pumped due to cache timing constraints. It is a cache requirement that the data be valid on the falling edge of CLK1. Since data is received from the port interface during phase 1, if the SW_RD bus is not double-pumped, the cache will get the earliest data on the CLK
1, but not on the negative edge of CLK1. Since the SW_RD bus is not double-pumped, it is only active at CLK1 (not tri-state), so that the problem of bus buffer collision does not occur. That is, no two bus drivers drive the same wire at the same time. SW IDBST
[3: 0] indicates that the identification (ID) code and the bank start code are transmitted from the slave device to the master device 88.
Used to return via Since data from a slave device is always returned in order,
There is no need to send D to the port. IDs are assigned to individual F prepared for each port in the interface.
It can be stored in the IFO.

Returning again to the read FIFO 132, data is only stored in the switch read bus SW_RD when it is not available. Bus S
If W_RD is currently in use on another port, incoming read data is temporarily pushed to the read FIFO 132, and when the SW_RD bus is released, the data is
And is forwarded through the switch network 54 to the requesting cache or IOU.

Data transfer between the D-cache interface 55, the I-cache interface 56, the input / output interface 57, and the port interfaces P ₀ -P _N is an example in which data is transferred to and from the D-cache interface 55. And will be described below.

D-cache, I-cache or IOU
If one of the users wants to access a port, it checks to see if that port is free.
The request is sent to the port arbitration unit PAU ₀ on the request signal line 70b as shown in FIG. If the port is free, the port interface notifies switch arbitration unit 58 using request control line 71a that a request exists. If the switch network 54 is free, the switch arbitration unit 5a indicates that the request has been granted on the control line 71b by the permission control line 7a.
It notifies the port on 0a and the master, for example, the D-cache interface 55.

If the request is a write request, the D-cache interface circuit 55
Check 2 to see if the MCU 50 is authorized to use the MAU bus 25. Still bus 25 to MCU
If is not granted, a bus request is issued. If the bus is granted, or is granted, the port arbitration unit 171 makes a request for the switch bus 140,141. When access to the switch buses 140 and 141 is permitted, the D-cache interface circuit 55
Indicates the corresponding address in the switch bus SW_REQ14.
0 and at the same time, write data
The data is sent out on the bus SW_WD 141 and the data
Store in the FIFO (WDF) 131. Data is WD
When placed in F, the MCU writes data sequentially to the MAU. The reason for checking whether the bus is permitted before sending write data to the port is that when the snoop request is received from the external processor, the MCU determines whether the bus is permitted.
This is to avoid checking the DF. Therefore, checking if there is any changed data
This is done only with the cache

If the request is a read request and it is determined that the port and switch network are free as described above, the port interface will switch to SW_REQ.
It receives the address sent from the requesting unit on the bus, and requests the orbiter to arbitrate for permission of the MAU bus 9. Before the port can actually use the bus, it must notify the MAU orbiter that the MAU bus has been granted. Thereafter, the request is forwarded from the switch to the port. When the MAU address bus 9 is free, the address is sent out on the MAU address bus. The port is informed in advance when data will be received. The port requires a switch return data bus, so if the bus is not busy, it is available when data is returned. If the bus is free, the port sends read data out on the bus,
The D-cache, I-cache or I / O interface will retrieve the data and deliver it to the respective requesting unit.

When the D / I caches 51 and 52 request an input / output address, the D / I cache interfaces 55 and 56 pass the request to the input / output interface unit 57 via the request bus SW_REQ.
The I / O interface unit 57 passes the request to the switch arbitration unit 58 via the control signal line 90 if it has an available entry in its queue to store the request. Once the switch network 54 is free, once again the switch arbitration unit 58 sends the D / I cache interface 5
5, 56, and the address is transferred to the address bus SW_.
REQ, and if it is a write request (D-cache only), write data is sent on the write data bus SW_WD so that it can be transferred to the IOU. Similarly, D / I cache interface 5
If the request from 5, 56 is a read request, the read data from the I / O interface 57 is transferred from the I / O interface 57 via the read data bus SW_RD of the switch network to the D / I cache interface. Passed to 55 and 56 and from there D /
The data is transferred to the I caches 51 and 52.

As shown in FIG.
Each of the interface and the cache has a code 16
Tests and sets (TS) indicated overall at 0, 168
A bypass circuit is provided. This bypass circuit is M
It monitors whether there is a semaphore address on the AU address bus 9, that is, snoops. As will be appreciated, the circuits 160, 168 save memory bandwidth consumed when spin locking the semaphore.

The TS circuits 160 and 168 include a snoop
Address generator (snoop address)
generator) 161, TS content address memory (CAM-content addressable)
e memory 162, flip flop 163 and MUXs 164, 165.

A semaphore is
Stored in an addressable location in memory,
Flags or labels to control access to memory and other areas of addressable resources. For example, when a certain CPU accesses a certain memory area associated with a semaphore,
When the user does not want to access, the accessing CPU puts all 1s in the semaphore. When another CPU attempts to access the area, it first checks the semaphore. If the semaphore is found to be all ones, the second CPU will be denied access. By that time, if the second CPU has issued an access request many times, the access is rejected many times, and as a result, a phenomenon called “semaphore spin lock” occurs. When this semaphore spin lock occurs, the requestor C
Since the PU must read and write, memory
A problem arises in that the amount of bandwidth is overused.

The test and set bypass circuits 160, 168 shown in FIG. 4 implement a simple algorithm that prevents excessive use of memory bandwidth when a semaphore spin lock occurs.

In operation, a CPU, or more precisely, a process within a processor, first requests load and set instructions, ie, a request to access the semaphore, in order to request a memory area with which the semaphore is associated. When issuing the relevant predetermined instruction, the CPU first accesses the semaphore and stores the semaphore address in the CAM 162. Issuing multiple load and set instructions will cause multiple entries to
It will be stored in M162. If the semaphore is all 1 ($ FFFF), 1 is returned, meaning that access is denied. When another process requests the semaphore, it checks its CAM. If the address of the requested semaphore is still in the CAM, the CPU is notified that the semaphore has not been released by another processor / process, and there is no need to spin lock the semaphore. Instead, M
Since the CU receives an all ones (semaphore failure), the semaphore is not required for memory, thereby preventing overuse of memory bandwidth. On the other hand, if the address of the semaphore is not in the CAM, it means that the semaphore has never been requested before or has been released.

The MAU bus does not provide a byte address. When the semaphore is released, the CAM needs to be cleared. Access to any part of the smallest detectable memory block surrounding the semaphore is MA
When done by any processor on the U bus,
CAM is cleared. The current block size is 4 or 8 bytes. In this way, the CAM will not retain the address of the cleared semaphore, even if the CAM may be cleared when the semaphore was not cleared by writing to another location in the memory block. The semaphore is cleared when any processor writes anything other than all 1s to the semaphore.

After writing to the memory block where the semaphore is located, if the semaphore is accessed by test and set instructions, the memory is accessed again. If the semaphore has been cleared, the cleared value is returned to the CPU and the address is set again in the CAM. When the semaphore is not cleared or locked again, the CAM is loaded with the semaphore address, but the locked value is returned to the CPU.

In operation of circuit 160 of FIG. 4, circuit 160 snoops on MAU address bus 9 and uses the detected address signal to generate a corresponding snoop address in address generator 161. , This address is on line 169 CMA 162
Sent to and compared to its contents. If there is a hit, that is, if there is an entry that matches the entry in CAM 162, that entry in CAM 162 is cleared. When a load and set request is made, for example, from the D-cache to the MCU, the D-cache interface circuit compares the address with the entry in the CAM. CAM16
When a match is found (when hit), the ID is latched in the register 163 of the cache interface, and the ID and all 1 ($ FFFF) are stored in the MU.
Returned to the cache interface via X164, 165.

To snoop the address and then generate a snoop address with the snoop address generator 161 to make a comparison with the CAM 162, M
Even if the address appearing on the AU address bus 9 is for a non-shared memory location, it will continue without adverse effects. Snoop address
Generator 161 typically has a MAU address
From the 11 bits of the MAU matrix address appearing on the bus 9, the cache block address (upper bit) is changed to M
It is generated using the AU control signals RAS and CAS and the BKST START MAU control signal on the control signal bus 11.

As shown in FIG. 5, there is provided a circuit, generally designated 170, for maintaining cache continuity according to another aspect of the present invention. The need for cacheability is required in a multiprocessor environment to ensure that the master device and the slave devices, that is, the CPUs, all have the latest data.

As shown outside the chip constituting the circuit 170, an orbiter 6, a memory 7, an MAU address bus 9, an MAU control bus 11, and a multiprocessor control bus 10 are provided. Circuit 172 includes a port arbitration unit interface 171, a bus arbitration control unit 172, a multiprocessor control 173, and a snoop address generator 161 shown in FIG.
Is provided. D-cache interface 55
Are connected to a multiprocessor control 173 via a pair of control signal buses 174, 175 and a snoop address bus 176. The I-cache interface 56 is connected to the multiprocessor control 173 via a pair of control signal buses 177, 178 and a snoop address bus 176. Snoop address generator 161 is connected to multiprocessor control 173 via control signal bus 179. Multiprocessor control 173 further
It is connected to the multiprocessor control bus 10 via a control signal bus 180 and to the bus arbitration unit 172 via a control signal bus 181. Port arbitration interface 1
Reference numeral 71 is connected to the bus arbitration control unit 172 via a control signal bus 182. Bus arbitration control unit 17
2 is connected to the orbiter 6 via the bus arbitration control unit 183. Snoop address generator 1
61 is also connected to MAU address bus 9 and MAU control bus 11 via address bus 14 and control bus 16, respectively.

When a request from the cache is sent,
An attribute indicating whether the request is for shared memory is sent with the request. When the request is for shared memory, the port interface places the shared signal SHARE on the multiprocessor control signal (MCS) bus 10.
Send D_REQ. When another CPU detects this shared signal on MCS bus 10, it begins to snoop MAU ADDR bus 9 to obtain a snoop address.

The snooping is as follows.
As described briefly above, it is a cache persistence protocol. According to this protocol, control is distributed to all caches on a shared memory bus, and all cache controllers (CCUs) listen (1isten) or snoop on the bus to determine if they have a copy of the shared block. I do. Thus, snooping is the process by which the slave MCU monitors all transactions on the bus to see if there is an RD / WR request issued by the master MCU. The primary task of the slave MCU is to snoop the bus to determine if there is data that needs to be received, that is, to invalidate previously received data, or to update the latest data to the master. To the side MCU, that is, to perform an intervention.

As described in more detail below, the multiprocessor control circuit 173 shown in FIG. 5 processes the invalidate, intervene, and snoop hit signals from the cache to generate a snoop hit, as described in more detail below. intervention/
Snoop hit (SNP_HI) when invalidation is indicated
T) and intervention (ITV_REQ) signals are generated on the multiprocessor control signal bus 180.

The bus arbitration control circuit 172 shown in FIG. 5 arbitrates the MAU bus in a normal read or write operation. The MAU is also used in case of intervention / invalidation.
It arbitrates for the bus and interfaces directly with an external bus arbitration control signal pin that leads directly to the external bus orbiter 6.

Next, the above-mentioned intervention and invalidation operations for guaranteeing the cache integrity are performed by using the read request, the write request, and the read with change intention (rea) issued from the master central processing unit (MSTR CPU).
The description will be made in connection with a d-with-intent-to-modify request.

When the MSTR CPU issues a read request, it issues an address on the memory array unit (MAU) address bus 9. Slave side (SLV) C
The PU snoops the address on the MAU bus 9. SL
If the data retrieved by the VCPU from the addressed memory location in its cache has been modified, the slave-side cache control unit (SLVC C
CU) sends an intervention signal on the multiprocessor control bus 10 to indicate that the data has been updated, ie changed. When the MSTR detects the ITV signal, it abandons the bus, and the SLVCCU writes the update data to the main memory, that is, the MAU7. If the data requested by the MSTR has not yet been received by the MSTR cache control unit (CCU), the MSTR MCU discards the requested data and again asserts that it requests data from the MAU. Requested data is MSTR CCU
If the ISTR has been transferred, the MSTR MCU notifies the MSTR CCU (or the IOU controller if the IOU is the MSTR) to discard the data. after that,
The MSTR MCU issues a read request again after the slave updates the main memory. Meanwhile, the port interface holds the master's read request pending, while the slave writes the modified data back to memory. Thereafter, a read request is performed.

The MSTR issues a write request and stores the address in the memory array unit (MAU) address bus 9
Out, and if the slave CCU has a copy of the original data from this address in its cache, the slave CCU invalidates, ie discards, the corresponding data located in its cache. .

The MSTR issues a read request with a change intention, and sends the address on the memory array unit (MAU) address bus 9, and the slave MCU sends the address sent from the master (MSTR) on the address bus. , One of two possible actions is taken:

1. If the SLV CCU has changed the data corresponding to the data addressed by the MSTR, the SLV issues an ITV signal, the MSTR receives the signal, gives up the bus, and writes the changed data to the memory. Allow that. This operation corresponds to the intervention operation described above.

2. If the SLV has unmodified data corresponding to the data addressed by the MSTR, S
The LV invalidates, ie, discards, the data. This operation corresponds to the invalidation operation described above.

As shown in FIG. 6, a circuit according to another embodiment of the present invention, generally designated by the reference numeral 190, is provided. This circuit 190 is used to perform row match comparison to reduce memory latency. The circuit 190 includes a comparator 191, a latch 192, and a pair of MUXs 193, 1
94 are provided.

The function of the row match comparison is to determine whether the current request has the same row address as the previous request. If they have the same row address, the port is R
There is no time penalty for canceling the AS request. Row match is mainly used in DRAM, but SRA
It is also possible to use M or ROM. That is,
Because ROMs and SRAMs pass addresses to the MAU in upper and lower address segments, similar to those used in DRAMs, there is no need to latch the MAU on top of the new address, i.e., the row bits. is there.

The operation of the row coincidence circuit shown in FIG. 6 will be described. The row address, including the array select bit corresponding to the address, is latched by MUX 193 to latch 19.
2 is stored. New address is switch network address line SW Each time it appears on REQ, its address is sent through a new request MUX 194 and compared with a previous request in a comparator 191. If the rows match, a signal is generated from the output of comparator 191 and transferred to the port interface via signal line 195, which is part of bus 70. If a row match is hit, the RAS cycle time is saved because the port interface is prohibited from canceling the RAS request.

The MUX 193 is used to extract the row address from the switch request address. Mapping a row address to a switch address is equivalent to a DRAM
(For example, 1Mx1 or 4Mx1 DRAM)
And the width of the MAU data bus (eg, 32 bits or 64 bits).

As shown in FIGS. 1 and 5, the external bus
The orbiter 6 is a unit mainly composed of a programmable logic array (PLA) and a storage element.
This orbiter receives a MAU bus request from a heterogeneous CPU, arbitrates which CPU should be granted a bus permission based on a software-selectable dynamic or fixed priority scheme, and issues a permission to the relevant CPU. I do. The storage element keeps track of which CPU was last granted the bus and can implement either a dynamic or flexible priority scheme and a fixed or "round robin" priority scheme. .

Referring to FIG. 7, the dynamic switch and port arbitration used in the multiprocessor environment of the present invention is described below. As described above, there are three masters and two resources served by the MCU.
The three masters are a D cache, an I cache, and an IOU. Two resources, the slave, are the memory port and the IOU. As is clear from the above, IO
U can be both a master and a resource / slave.

According to the present invention, two types of arbitration are performed.
You. One related to arbitration of memory port resources
And the other is the bus of the switch network 54.
SW Related to arbitration of REQ and SW_WD resources
is there.

Multiple devices may request data from main memory simultaneously. These devices are D-cache, I-cache and IOU.
The priority method of giving a certain priority to each master is intended to enable a request from a device having a high “importance” or “urgency” to receive a service as soon as possible. However, a strict fixed arbitration scheme is not preferable because a device having a low priority may be starved for a long time.
Instead, a dynamic arbitration scheme has been introduced that assigns different priorities on a device-by-device basis. The following factors influence the dynamic arbitration system.

1. 1. The unique priority of the device 2. The requested address and the address of the previously serviced request line match. 3. Device has been denied service too many times. The Master Has Received Too Many Services As shown in FIG. 7, the dynamic priority scheme used when requesting a memory port is as follows. Each request from a device has a unique priority. The IOU can request high or normal priority, then the D-cache, and then the I-cache. However, intervention (ITV) requests from the D-cache have the highest priority of all.

Special high priority I / O requests can be made. This priority is real-time (real time) that requires access to memory while minimizing memory latency
It is intended to be used in input / output peripheral devices. These requests can take precedence over all other requests except for the intervention cycle and row match as shown in FIG.

Factors that change the inherent priority of various devices include denial of service and input / output monopoly (I / O ho).
g) and line matching. Each time a device is denied service, the counter is decremented. When the counter reaches zero, the priority of the device is increased and a priority level named DENY PRIORITY is set. These counters can be loaded with up to 15 programmable values. When the counter reaches zero, the DENYP
The RIORITY bit is set, which is eventually cleared when the denied device is serviced. According to a method for increasing the priority of a denied device, a service deprivation (starv
ation) is prevented. Note that IOU
Since the inherent priority level of the
Is not assigned a denial of service priority.

Since the IOU is already a high priority device by nature, it is necessary to prevent the device from monopolizing the port by using a counter. Each time the IOU is granted port usage, the counter is decremented. When the counter reaches zero, the IOU is treated as monopolizing the bus and the IOU priority level is lowered. The priority level of the IOU is lowered only for a normal priority request, and not for a high priority input / output request. If the IOU is not granted the right to use the port during the request cycle, the exclusive priority bit (hog)
priority bit) is cleared.

Another factor that changes the unique priority of a request is row matching. Row match is of primary importance in the case of I-caches. When a device requests a memory location with the same row address as a previously serviced request, the requesting device is given a higher priority. This is done so that RAS need not be re-requested.

However, there is a certain limit to maintaining the line matching priority. Again, the counter is used with the maximum programmable value set. The counter is decremented each time a request is serviced due to row match priority. When the counter reaches zero, the row match priority bit is cleared. When a new master for a port is assigned or there is no request for a row match,
The counter is again pre-loaded with a programmable value. The counter described above is located in the switch arbitration unit 58.

A write request to a memory port is permitted only when the switch write data bus SW_WD is enabled. When not available,
Another request is selected. There is one exception, which is
This is the case of the intervention signal ITV. If SW_WD is not enabled, no requests will be selected. Instead, the processor waits for SW_WD to be free before passing the request to the switch orbiter.

The arbitration scheme for the switch network 54 is slightly different from the scheme used for port arbitration. The switch arbitration unit 58 of FIG. 3 utilizes two types of arbitration schemes when arbitrating software selectable ports.

1. 1. Slave priority scheme where priority is based on slave or requested device (ie, memory or IOU port) If the priority is the master or requesting device (ie,
Master priority scheme based on IOU, D-cache and I-cache) In the slave priority scheme, priority is always given to memory ports in a round robin manner. That is, the priorities are initially assigned to memory ports 0, 1, 2,. . . Given to
It is then given to the IOU. On the other hand, in the master priority system, the priority is first given to the IOU, and then to the D cache and the I cache. Of course, depending on the circumstances, it may be necessary or necessary to give the highest priority to the ITV request according to the master priority method. Also, if the prefetch buffer eventually becomes empty, it may be necessary or desirable to give the I-cache a high priority. In any case, the priority scheme used can be adjusted by software to suit various operating conditions.

[0093] Dynamic memory refresh is also based on a priority scheme. A counter connected to the state machine is used to record how many cycles have elapsed from one refresh to the next, that is, the number of times a refresh has been requested and rejected because the MAU bus is busy. Is done. When the counter reaches, or elapses, a predetermined count, a signal is generated for the port to notify the port that it needs to be refreshed. If the port is in use and servicing requests from D-cache, I-cache or IOU, refuse to service refresh requests if the number of rejected refresh requests has not reached the specified number. I do. In other words, when refresh requests are rejected up to a predetermined number of times, priority is given to servicing refresh requests. When the port is ready to service refresh requests,
Notifies the bus arbitration control unit to begin arbitration for the MAU bus.

The rows are preferably refreshed every 15 microseconds and need to be refreshed within a predetermined time period, for example, at least every 30 microseconds.

When RAS goes low (request-assert) and no CAS is requested, all CPUs are notified that refresh has been performed. All CPUs keep track of when refreshes occur, so any CPU can request a refresh when needed.

Although the preferred embodiment of the present invention has been described, it is needless to say that various modifications can be made without departing from the spirit and scope of the present invention. Therefore, the above-described embodiment is merely an example for describing the present invention, and the scope is not limited to the embodiment but should be determined from the invention described in the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a microprocessor architecture capable of supporting a plurality of heterogeneous microprocessors according to the present invention.

FIG. 2 is a block diagram illustrating a memory control unit according to the present invention.

FIG. 3 is a block diagram showing a switch network showing a connection state between a D-cache interface and a port interface according to the present invention.

FIG. 4 is a block diagram illustrating a test and set bypass circuit according to the present invention.

FIG. 5 is a block diagram illustrating circuitry used to generate intervention signals and to arbitrate MAU buses in accordance with the present invention.

FIG. 6 is a block diagram showing a row match comparison circuit according to the present invention.

FIG. 7 illustrates a dynamic arbitration scheme according to the present invention.

FIG. 8 is a diagram showing the timing of a write request.

FIG. 9 is a diagram showing the timing of a read request.

[Explanation of symbols]

1 .... architecture, 2, 3, 4, . . N: processor, 5: special purpose processor, 6: orbiter (arbitration circuit), 7: memory / memory array unit (MA)
U), 8 MAU data bus, 9 ROW / COL address bus, 10 multiprocessor control bus, 1
1: MAU control bus, 12: bus arbitration control signal bus, 2
5. MAU system bus

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Lau, Theri United States 94206 Palo Alto College Avenue, California 411 (72) Inventor Tan, Chenlong United States 95132 San Jose Camago Drive, California 1948

Claims (2)

[Claims] 1. A computer system having a memory array unit (MAU), a plurality of memory ports coupled to the MAU, and a plurality of devices accessing the MAU through the memory ports, wherein arbitration for the memory ports is provided. A method of arbitrating memory ports,
(1) assigning a priority to each device;
(2) servicing requests for said memory ports issued by said devices according to said priorities, wherein step (1) comprises: (a) assigning an initial priority to each of said devices. (B) raising the priority with respect to the first device having an initial priority lower than the first priority value when the first device is repeatedly denied service to the memory port; (c) Lowering the priority with respect to the second device having an initial priority higher than the second priority value when the second device is determined to be memory-exclusive; and (d) issued by the third device. A third device, wherein the row addressed by the pending memory access request corresponds to the row addressed by the preceding memory access request serviced by the MAU; Increasing the priority with respect to the memory port arbitration method. 2. The step (c) includes, when the second device receives service for the first time after the interruption, initializing a counter to a predetermined value, and the second device receives service without interruption. Reducing the number of the counter each time, and when the counter reaches zero,
Deciding that said second device is memory monopoly.