JP4985452B2 - Vector processing equipment - Google Patents

Description

  The present invention relates to a vector processing device.

  FIG. 1 shows the configuration of a conventional vector processing apparatus.

  As shown in FIG. 1, the conventional vector processing apparatus is a computer, and includes a first instruction decode stage 101, an instruction decoder 102, a second instruction decode stage 103, a resource match detection circuit 104, and an instruction issue stage. A plurality of instruction issue stages including (0 system) 105 and (1 system) 106, a storage unit (not shown) for storing the BUSY flag 107, an issue check circuit 108, a selection unit 111, and an instruction execution unit (shown) Not). This vector processing device operates with a clock.

  An instruction is set in the first instruction decode stage 101, and the first instruction decode stage 101 outputs this instruction to the instruction decoder 102. The instruction decoder 102 decodes this instruction and sets it to the second instruction decoding stage 103.

  The issue check circuit 108 manages the issue of subsequent instructions by the BUSY flag 107. The issue check circuit 108 outputs an issue instruction 109 for one of the instruction issue stages 105 and 106 and sets a BUSY flag 107. At this time, the issue check circuit 108 outputs the selection instruction 110 representing the one instruction issue stage, and the selection unit 111 executes the instruction set in the one instruction issue stage according to the selection instruction 110. To the output. That is, an instruction is issued. The instruction execution unit executes the issued instruction.

  The resource coincidence detection circuit 104 is set in the second instruction decode stage 103 when either of the instruction issue stages 105 and 106 is free and when no resource coincidence with any of the instruction issue stages 105 and 106 is detected. The issued instruction is set to one of the instruction issue stages 105 and 106 at the next clock.

  In the conventional vector processing apparatus, when instructions are arranged in the instruction issue stages 105 and 106, the order is not guaranteed, so the following problems occur. For example, a state is assumed in which a preceding instruction cannot be issued due to some factor (resource BUSY) and is waiting. At this time, in the conventional vector processing apparatus, the succeeding instruction in which the resource match is detected by the resource match detecting circuit 104 may be issued overtaking the preceding instruction, and therefore, setting to the instruction issuing stage is suppressed. . In such a case, all subsequent subsequent instructions are stopped by the subsequent instruction whose set is suppressed, and the performance is degraded. In the subsequent instructions that follow, there may be an instruction whose resource does not match that of the preceding instruction. In this case, it must be dropped to the instruction issue stage as much as possible.

  Introducing computer technology.

  Japanese Patent Laid-Open No. 8-305567 describes a parallel processing method for arithmetic instructions (Patent Document 1). The parallel processing method for arithmetic instructions is an information processing method for storing a plurality of arithmetic instructions having different arithmetic latencies and performing pipeline processing so that they can be overtaken. In this method, the conflict between the operation instruction being pipelined and the operation instruction scheduled to be issued to the pipeline is checked for each conflict type, and if there is a conflict, the operation instruction scheduled to be issued is suppressed from being issued to the pipeline. The output of the signal is controlled according to the competition type.

  JP-A-6-195313 discloses a computer system (Patent Document 2). The computer system includes a plurality of processors, a storage device that is divided into a plurality of partial storage devices that can be accessed in parallel with each other, and memory access requests for the storage devices that are output in parallel from the plurality of processors in parallel. A storage control circuit for transferring to the plurality of partial storage devices. Each of the plurality of processors includes one of a plurality of requesters, and each requester requests access to a plurality of storage locations in the storage device being executed by the processor to which the requester belongs (memory access instruction). In response to this, a plurality of access requests for requesting access to the plurality of storage locations are sequentially issued. Each requester has a first signal generation circuit that outputs a priority switching signal for requesting switching of priority regarding the requester. The storage control device is provided corresponding to one of the plurality of partial storage devices, and is one of a plurality of access requests to be transferred to the corresponding partial storage device respectively supplied from the plurality of processors. A plurality of selection circuits for selecting a plurality of selection circuits, and means for holding priority order information common to the plurality of selection circuits regarding the priority orders of the plurality of requesters to be supplied to the plurality of selection circuits; In response to a priority switching signal output from the first signal generation circuit included in any one of the requesters, the priority stored in the storage means is switched so as to switch the priority regarding the requester. And a switching circuit for switching information.

  Japanese Unexamined Patent Application Publication No. 2007-280184 describes a processor (Patent Document 3). The processor includes a fetch unit that fetches an instruction code, an arithmetic unit that can operate in parallel, and a register file unit. The register file unit decodes the fetched vector operation instruction and generates a vector register control signal necessary for performing control to write execution result data of the operation unit to the vector register, and a plurality of vector registers A write control circuit for performing control to write data into the vector register based on the vector register control signal. The plurality of vector registers are composed of a plurality of element registers, element registers having the same element number are grouped, and each group has a write port. The write control circuit selects an element group and a vector register to be written based on the vector register control signal, and writes data to be written to the write port to the element register of the selected vector register of the selected element group. It is characterized by performing control.

  Japanese Patent Publication No. 8-10431 discloses an information processing apparatus (Patent Document 4). The information processing apparatus has a plurality of pipelined arithmetic units having different functions. In this information processing apparatus, when the minimum number of pipeline stages required for each operation is different, a pipeline register that simply transfers the result to the subsequent stage for each operation unit is set to the same number of stages in each operation system pipeline. The necessary number of stages is added so that the switching means that can output the operation result from any of the added pipeline registers, and competition between different operation systems trying to select one of all the result outputs Control means for giving priority to the result if there is a need for the result earlier, and giving priority to the output from the arithmetic unit system having the longest number of pipeline stages necessary for the operation. It is a feature.

JP-A-8-305567 JP-A-6-195313 JP 2007-280184 A Japanese Patent Publication No. 8-10431

  An object of the present invention is to provide a vector processing apparatus that can efficiently use resources even if the resources compete between the instruction and the preceding instruction.

  The vector processing apparatus of the present invention includes an instruction decode stage in which an instruction is set, a plurality of instruction issue stages, a plurality of check circuits respectively corresponding to a plurality of instruction issue stages, and an instruction set in the instruction decode stage and a plurality of instructions A resource match detection circuit for detecting whether or not there is a resource match between the instructions set in the instruction issue stage. When the instruction set in the instruction decode stage is set in a free own instruction issue stage among a plurality of instruction issue stages, the resource coincidence detection circuit detects the instruction in the instruction decode stage and the plurality of instruction issue stages. As a result of detection between instructions, if the order must be maintained by competing resources, order flags corresponding to instruction issue stages other than the self instruction issue stage are set. As a result of detection, when overtaking is possible even if resources compete, priority flags corresponding to instruction issue stages other than the self instruction issue stage are set. The plurality of check circuits perform arbitration according to the order flag and the priority flag, and issue an instruction set in the own instruction issue stage based on the result of the arbitration.

  As described above, according to the vector processing device of the present invention, when resources compete between an instruction and a preceding instruction, many instructions can be entered in the instruction issue stage by flagging the competition relationship. Further, resources can be efficiently used by performing arbitration between an instruction and a preceding instruction and issuing from an instruction that can be issued with a high priority order.

  Hereinafter, a vector processing apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[Constitution]
FIG. 2 shows the configuration of the vector processing apparatus according to the embodiment of the present invention.

  As shown in FIG. 2, the vector processing apparatus according to the embodiment of the present invention is a computer, and includes a first instruction decode stage 1, an instruction decoder 2, a second instruction decode stage 3, and a resource match detection circuit 4. A storage unit (not shown) for storing a plurality of instruction issue stages, flags for the plurality of instruction issue stages, and a BUSY flag 9, a plurality of instruction issue check circuits, and a plurality of priority check circuits. .

  The plurality of instruction issue stages represent an A0 instruction issue stage 6, an A1 instruction issue stage 6 '(not shown), ..., an M0 instruction issue stage 8, an M1 instruction issue stage 8' (not shown),.

  The plurality of instruction issue check circuits include an A0 instruction issue check circuit 10, an A1 instruction issue check circuit 10 ′ (not shown),..., An M0 instruction issue check circuit 11, an M1 instruction issue check circuit 11 ′ (not shown),. Represents.

  The plurality of priority check circuits represent an A0 priority check circuit 12, an A1 priority check circuit 12 '(not shown),..., An M0 priority check circuit 13, an M1 priority check circuit 13' (not shown),.

  Flags for a plurality of instruction issue stages include, as priority flags, A0 instruction issue stage priority flag 5, A1 instruction issue stage priority flag 5 ′ (not shown),..., M0 instruction issue stage priority flag 7, M1 instruction issue stage priority flag. 7 '(not shown),. Further, as order flags, A0 instruction issue stage order flag 16, A1 instruction issue stage order flag 16 ′ (not shown),..., M0 instruction issue stage order flag 17, M1 instruction issue stage order flag 17 ′ (not shown), Includes ...

  Here, the order flags 16, 16 ', 17, 17' and priority flags 5, 5, 7, 7 'will be described.

  The order flags 16, 16 ′, 17, and 17 ′ indicate that when a self-instruction is set in the instruction issuance stage, there is a predecessor instruction that competes for resources in another instruction issuance stage, and the self-instruction overtakes the predecessor instruction. This flag indicates that it cannot be issued. When a self-instruction is set in the instruction issuance stage, if a resource conflict is detected in a preceding instruction in another instruction issuance stage, an order flag corresponding to that instruction issuance stage is set. The order flags 16, 16 ', 17, 17' are reset when a preceding instruction at the instruction issue stage corresponding to the order flags 16, 16 ', 17, 17' is issued. It is used to suppress the issue of its own instruction at the instruction issue stage for which the order flag is set until the preceding instruction at the instruction issue stage corresponding to the order flag is issued. Here, the relationship between the instructions that must be kept in order is the relationship that results in incorrect results when the execution order is changed, for example, the number matching relationship of the vector registers 29 to 36 shown in FIG. 4 or the number matching of the vector data registers 21 to 28. Show the relationship.

  The priority flags 5, 5, 7, and 7 'are flags that indicate that there is a preceding instruction that competes for resources in another issue stage when the self instruction is set in the instruction issue stage. When a self-instruction is set in the instruction issue stage, if a resource conflict is detected in a preceding instruction in another issue stage, a priority flag corresponding to the issue stage is set. The priority flags 5, 5, 7, and 7 'are reset when the preceding instruction of the instruction issue stage corresponding to the priority flags 5, 5, 7, and 7' is issued. The self-instruction of the instruction issue stage with the priority flag set has a function to suppress the issue of the self-instruction when the instruction of the issue stage corresponding to the priority flag can be issued, and the preceding instruction of the issue stage corresponding to the priority flag. This function is used to realize a function of overtaking the preceding instruction when the instruction can be issued instead of being issued. Here, the relationship of instructions that can be overtaken is that the execution order does not change between instructions, and the result does not cause fraud, for example, shared VDR Write PATH (signal lines L1, L2, L3, and L4 in FIG. 4) that cannot be used simultaneously. Shows the relationship.

  In order to facilitate the following description, there are two combinations of priority flag and issue stage: A0 instruction issue stage priority flag 5, A0 instruction issue stage 6, M0 instruction issue stage priority flag 7, and M0 instruction issue stage 8. The operation of the vector processing apparatus according to the embodiment of the present invention will be briefly described with reference to FIG.

  An instruction is set in the first instruction decode stage 1. The instruction decoder 2 decodes the instruction set in the first instruction decode stage 1 into a request for a resource in which the instruction is used, and sets it in the second instruction decode stage 3. The resource match detection circuit 4 detects whether or not there is a resource match between the instruction set in the second instruction decode stage 3 and the instructions set in a plurality of instruction issue stages. In this case, it is detected whether or not there is a resource match between the instruction (request) set in the second instruction decode stage 3 and the preceding instruction (request) of the instruction issue stages 6 and 8.

  The resource coincidence detection circuit 4 sets the instruction set in the second instruction decode stage 3 to a free own instruction issue stage (instruction issue stage 6 or instruction issue stage 8) of the instruction issue stages 6 and 8. At the same time, the order and priority flags are simultaneously set based on the detection result. At this time, when the resource match detection circuit 4 must keep the order by competing resources between the instruction of the second instruction decode stage 3 and the instructions of the instruction issue stages 6 and 8, as a result of the detection, Order flags corresponding to instruction issue stages other than the self instruction issue stage are set. On the other hand, as a result of the above detection, if overtaking is possible even if resources compete, priority flags corresponding to instruction issue stages other than the self instruction issue stage are set.

  Therefore, the more the order and priority flags are, the more subsequent instructions become. Once set, the priority flag is not reset unless a new instruction is set. It is reset when the instruction corresponding to the order and priority flag is executed. Therefore, the self-instruction cannot be executed unless all the order flags are reset. The instruction at the instruction issue stage holding the priority flag enables execution by overtaking the preceding instruction when the preceding instruction at the instruction issue stage corresponding to the priority flag cannot be executed due to other factors.

  The BUSY flag 9 manages resources used by the instruction being executed. The order flag described above guarantees the order between instructions waiting for execution at the issue stage, and is used as the BUSY flag 9 before execution. The priority flag need not guarantee the order, but is to avoid sharing resources when executed at the same time. If the timing to execute simultaneously can be avoided, it can be managed by the BUSY flag 9 after execution. That is, a time for setting the BUSY flag 9 is secured.

  The check circuits (A0 instruction issue check circuit 10 and A0 priority check circuit 12) perform arbitration according to the order flag and priority flag, and issue the instruction set in the instruction issue stage 6 based on the result of the arbitration. This will be described.

First, the A0 instruction issuance check circuit 10 checks whether the resource corresponding to the instruction (request) in the A0 instruction issuance stage 6 is free by using the BUSY flag 9 and determines whether there is an instruction whose order must be guaranteed for the preceding instruction. Whether or not the A0 order flag 16 is checked. If the BUSY flag 9 is not set and the order flag is not set in the A0 instruction issue stage 6, a notification indicating that an instruction can be issued is output to the A0 priority check circuit 12. Next, the A0 priority check circuit 12 receives a notification from the A0 instruction issue check circuit 10 and checks whether or not the priority flag is set in the A0 instruction issue stage 6. When the priority flag is not set in the A0 instruction issue stage 6, the A0 priority check circuit 12 outputs the issue instruction 14, and outputs the instruction in the own instruction issue stage (A0 instruction issue stage 6) to the instruction execution unit. In this case, an instruction is issued from the A0 priority check circuit 12. The instruction execution unit recognizes that an instruction is issued in response to the issue instruction 14, and executes the instruction issued from the A0 priority check circuit 12. The A0 priority check circuit 12 sets the BUSY flag 9 corresponding to the instruction (request) of the A0 instruction issue stage 6 when issuing the instruction of the A0 instruction issue stage 6. At the same time, the A0 instruction issue stage 6 which is a request for the self instruction is reset. Of the M0 instruction issue stage priority flag 7, the priority flag corresponding to the A0 instruction issue stage 6 is reset. The order flag corresponding to the A0 instruction issue stage 6 in the M0 instruction issue stage order flag 17 is reset. When life Ryosho sense of A0 instruction issue stage 6 is completed, and resets the BUSY flag 9 corresponding to the instruction A0 instruction issue stage 6.

On the other hand, when the priority flag is set in the A0 instruction issue stage 6, the A0 priority check circuit 12 determines whether there is an instruction that can be issued in the instruction issue stage (M0 instruction issue stage 8) corresponding to the priority flag. To check. When the instruction in the M0 instruction issue stage 8 cannot be issued, the A0 priority check circuit 12 outputs the issue instruction 14 and issues the instruction in the A0 instruction issue stage 6. The A0 priority check circuit 12 sets the BUSY flag 9 corresponding to the instruction (request) of the A0 instruction issue stage 6 when issuing the instruction of the A0 instruction issue stage 6. At the same time, the A0 instruction issue stage 6 which is a request for the self instruction is reset. When life Ryosho sense of A0 instruction issue stage 6 is completed, and resets the BUSY flag 9 corresponding to the instruction A0 instruction issue stage 6.

  As described above, when the priority flag is not set in the A0 instruction issue stage 6, the A0 priority check circuit 12 issues the instruction of the A0 instruction issue stage 6, but among the priority flags of the A0 instruction issue stage 6, If the priority flag corresponding to the M0 instruction issuance stage 8 is set, whether or not the instruction of the M0 instruction issuance stage 8 can be issued is determined based on the check result of the M0 instruction issuance check circuit 11. If the issuance is possible, the instruction issuance at the A0 instruction issuance stage 6 is suppressed.

  Similarly, the check circuits (M0 instruction issue check circuit 11, M0 priority check circuit 13) perform arbitration according to the order flag and priority flag, and issue the instruction set in the instruction issue stage 8 based on the result of the arbitration. . This will be described.

First, the M0 instruction issuance check circuit 11 checks whether the resource corresponding to the instruction (request) in the M0 instruction issuance stage 8 is free by using the BUSY flag 9 and determines whether there is an instruction whose order must be guaranteed for the preceding instruction. It is checked with the M0 order flag 17 whether or not. If the BUSY flag 9 is not set and the order flag is not set in the M0 instruction issue stage 8, a notification indicating that the instruction can be issued is output to the M0 priority check circuit 13. Next, the M0 priority check circuit 13 receives the notification from the M0 instruction issue check circuit 11 and checks whether or not the priority flag is set in the M0 instruction issue stage 8. When the priority flag is not set in the M0 instruction issue stage 8, the M0 priority check circuit 13 outputs the issue instruction 15 and outputs the instruction in the own instruction issue stage (M0 instruction issue stage 8) to the instruction execution unit. In this case, an instruction is issued from the M0 priority check circuit 13. The instruction execution unit recognizes that an instruction is issued in response to the issue instruction 15 and executes the instruction issued from the M0 priority check circuit 13. The M0 priority check circuit 13 sets the BUSY flag 9 corresponding to the instruction (request) of the M0 instruction issue stage 8 when issuing the M0 instruction issue stage 8 instruction. At the same time, the M0 instruction issue stage 8 which is a request for the own instruction is reset. Of the A0 instruction issue stage priority flag 5, the priority flag corresponding to the M0 instruction issue stage 8 is reset. The order flag corresponding to the M0 instruction issue stage 8 in the A0 instruction issue stage order flag 16 is reset. When the life Ryosho sense of M0 instruction issue stage 8 has been completed, and resets the BUSY flag 9 corresponding to the instruction of the M0 instruction issue stage 8.

On the other hand, when the priority flag is set in the M0 instruction issue stage 8, the M0 priority check circuit 13 determines whether there is an instruction that can be issued in the instruction issue stage (A0 instruction issue stage 6) corresponding to the priority flag. To check. If the A0 instruction issue stage 6 instruction cannot be issued, the M0 priority check circuit 13 outputs the issue instruction 15 and issues the M0 instruction issue stage 8 instruction. The M0 priority check circuit 13 sets the BUSY flag 9 corresponding to the instruction (request) of the M0 instruction issue stage 8 when issuing the M0 instruction issue stage 8 instruction. At the same time, the M0 instruction issue stage 8 which is a request for the own instruction is reset. When the life Ryosho sense of M0 instruction issue stage 8 has been completed, and resets the BUSY flag 9 corresponding to the instruction of the M0 instruction issue stage 8.

  As described above, when the priority flag is not set in the M0 instruction issue stage 8, the M0 priority check circuit 13 issues an instruction of the M0 instruction issue stage 8, but among the priority flags of the M0 instruction issue stage 8, If the priority flag corresponding to the A0 instruction issuance stage 6 is set, it is determined from the result of the check of the A0 instruction issuance check circuit 10 whether or not the instruction of the A0 instruction issuance stage 6 can be issued. If issuance is possible, instruction issuance at the M0 instruction issuance stage 8 is suppressed. If issuance is not possible, an instruction at the M0 instruction issuance stage 8 is issued.

  Thus, according to the vector processing device of the present invention, when resources compete with each other between the instruction and the preceding instruction, many instructions can be entered in the instruction issuing stage by flagging the competition relationship. Further, resources can be efficiently used by performing arbitration between an instruction and a preceding instruction and issuing from an instruction that can be issued with a high priority order.

[Operation]
Next, the operation of the vector processing apparatus according to the embodiment of the present invention will be described using specific examples shown in FIGS. FIG. 3 is a timing chart showing the operation of the conventional vector processing apparatus and the vector processing apparatus according to the embodiment of the present invention. In FIG. 3, the present invention and the prior art are compared in the case where there is resource contention between instructions. Here, in FIG.
Instruction X1: VD0 / V0 <-V0 + V1
Command X2: VD4 <−V6 + V7
Command X3: VD8 / V0 <-V2 * V3
Command X4: VD12 <−V4 * V5
And FIG. 4 is a schematic diagram of the vector calculation processing device.

  Resource usage management is performed by the BUSY flag 9. The vector data register 21 (VDR) has a large capacity and stores vector data in VD0, VD8, VD16. The VDR 22 stores vector data in VDR numbers VD4, VD12, VD20,. Similarly, the VDRs 23 to 28 store vector data in VDR numbers that jump 8 from the youngest number. The vector registers 29 to 35 (VAR) store vector data to be calculated from V0 to V7. Vector calculators (ADD0, MLT0, MLT1, ADD1) 37-40 receive vector data from VARs 29-36 and perform calculations. The X-BAR switch 41 receives calculation results calculated by the vector calculators 37 to 40 and supplies vector data to the VARs 29 to 36 or VDRs 21 to 28. The signal line L1 is connected from the X-BAR switch 41 to the VDRs 21 and 22 by VDR Write PATH0. The signal line L2 is connected to the VDRs 23 and 24 from the X-BAR switch 41 by VDR Write PATH1. The signal line L3 is connected to the VDRs 25 and 26 from the X-BAR switch 41 by VDR Write PATH2. The signal line L4 is configured to be connected from the X-BAR switch 41 to the VDRs 27 and 28 by VDR Write PATH3. Here, VD0, VD4, VD8, and VD12 are in a competitive relationship using the same VDR Write PATH0. Also, V0 and V0, and VD0 and VD0 are in a competitive relationship with the same VAR number and VDR number.

  At the first clock, the instruction X1 is set in the first instruction decode stage 1 in the order of the instructions from IN.

  At the second clock, the instruction X1 is decoded by the instruction decoder 2 into the resource request used by the instruction, READ request V0, V1, Write request VD0 (VDR Write PATH0), V0 Write, and used arithmetic unit A (adder system). At the same time as setting the second instruction decode stage 3, the instruction X2 is set to the first instruction decode stage 1.

  At the third clock, the instruction X1 set in the second instruction decode stage 3 is set in the A0 instruction issue stage 6 because it is an adder system instruction. At the same time, the resource match detection circuit 4 detects a conflict with a preceding instruction set in another issue stage, and sets the A0 instruction issue stage priority flag 5 and the instruction issue stage order flag 16. This time, nothing is set because the preceding instruction is not in the issue stage. The instruction X2 of the first instruction decode stage 1 is decoded by the instruction decoder 2 into a resource request used by the instruction, a READ request V6, V7, a Write request VD4 (VDR Write PATH0), and a computing unit A (adder system). At the same time as setting the second instruction decode stage 3, the instruction X3 is set to the first instruction decode stage 1.

  At the fourth clock, the A0 instruction issuance check circuit 10 reads the READ request V0, V1, Write request VD0 (VDR Write PATH0), V0 Write, and the used computing unit A (addition) for the instruction X1 set in the A0 instruction issuance stage 6. Check that the BUSY flag 9 corresponding to (system) is not set (V0 Write BUSY, VDR Write PATH0 BUSY). The A0 instruction issuance check circuit 10 can issue to other instruction issuance stages corresponding to the A0 instruction issuance stage priority flag 5 which checks that all the A0 instruction issuance stage order flags 16 are reset and becomes an issuable instruction. After the arbitration is confirmed by the A0 priority check circuit 12 that there is no correct instruction, an issue instruction 14 is output. In this case, issuance is waited until the V0 Write BUSY flag 9 set by the preceding instruction is reset.

  Since the instruction X2 set in the second instruction decode stage 3 is an adder system instruction, it is set in the vacant A1 instruction issue stage 6 '. At the same time, the resource match detection circuit 4 detects a conflict with the preceding instruction set in another issue stage, and sets the A1 instruction issue stage priority flag 5 'and the A0 instruction issue stage order flag 16'. In this case, the instruction of the preceding A0 instruction issue stage 6 and the signal line L1 are in a competitive relationship (VDR Write PATH0), and the relationship between the A1 issue stage and the preceding A0 instruction issue stage 6 is set as a priority flag A1-> A0. . Here, the priority flag A1-> A0 indicates the priority flag own instruction issue stage → the instruction issue stage of the preceding instruction. The instruction X4 is set in the first instruction decode stage 1. The instruction decoder 2 decodes the instruction X3 into a resource request used by the instruction, a READ request V2, V3, a write request VD8 (VDR Write PATH0), a V0 Write, and a used calculator M (multiplier system). Set to the second instruction decode stage 3.

  At the fifth clock, the instruction X3 set in the second instruction decode stage 3 is set in the M0 instruction issue stage 8 because it is a multiplier instruction. At the same time, the resource match detection circuit 4 detects a conflict with a preceding instruction set in another instruction issue stage, and sets the M0 instruction issue stage priority flag 7 and the M0 instruction issue stage order flag 17. In this case, both the instruction of the preceding A0 instruction issue stage 6 and the instruction of the A1 instruction issue stage 6 ′ and the signal line L1 are in a competitive relationship (VDR Write PATH0), and the priority flag M0-> as the M0 instruction issue stage priority flag 7 Set A0, priority flag M0-> A1. Since the preceding A0 instruction issuance stage 6 instruction is the same as V0 Write, the order flag M0-> A0 is set as the M0 instruction issuance stage order flag 17 for the relationship that must not be overtaken. The instruction decoder 2 decodes the instruction X4 into a request for resources used by the instruction, a READ request V4, V5, a write request VD12 (VDR Write PATH0), and a used computing unit M (multiplier system). Set to instruction decode stage 3.

  The A1 instruction issuance check circuit 10 ′ sends READ request V 6, V 7, Write request VD 4 (VDR Write PATH 0), and used arithmetic unit A (adder system) to the instruction X 2 set in the A1 instruction issuance stage 6 ′. It is checked that the corresponding BUSY flag 9 is not lit (VDR Write PATH0 BUSY) and that the A1 instruction issuance stage order flag 16 ′ is all reset, and the instruction X2 becomes an issueable instruction. The A1 instruction issuance check circuit 10 ′ outputs an issuance instruction 14 ′ after confirming arbitration by the A1 priority check circuit 12 ′ for an instruction that can be issued to another instruction issuance stage corresponding to the A1 instruction issuance stage priority flag 5 ′. To do. In this case, the priority flag A1-> A0 is turned on in relation to the instruction X1 set in the A0 instruction issue stage 6 waiting for issuance until the V0 Write BUSY flag 9 is reset by the V0 Write BUSY flag 9 set by the preceding instruction. After confirming that the instruction X1 cannot be issued by the A1 priority check circuit 12 ', the instruction X2 first issues the issue instruction 14' and issues the instruction, overtaking the instruction X1. The V0 Write BUSY flag 9 is reset at this point after the processing of the preceding instruction is completed.

  At the 6th clock, the instruction X2 uses the resource by issuing the instruction, so that the BUSY flag 9 (VDR Write PATH0 BUSY) is turned on, manages that the subsequent instruction does not use the resource, and issues the subsequent instruction. Deter. Also, the A1 instruction issue stage priority flag 5 '(priority flag M0-> A1) is reset. The instruction X4 set in the second instruction decode stage 3 is set in the free M1 instruction issue stage 8 'because it is a multiplier instruction. At the same time, the resource match detection circuit 4 detects a conflict with the preceding instruction set in another issue stage, and sets the M1 instruction issue stage priority flag 7 'and the M1 instruction issue stage order flag 17'. In this case, the instruction in the preceding A0 instruction issue stage 6 and the instruction in the M0 instruction issue stage 8 and the signal line L1 are in a competitive relationship (VDR Write PATH0), and the priority flag M1-> A0 and the priority flag M1-> M0 are set. . The signal line L1 is also in a competitive relationship (VDR Write PATH0) with the instruction in the preceding A1 instruction issue stage 6 ', but since there is no instruction in the A1 issue stage after the instruction is issued, the priority flag M1-> A1 is not set.

  In the seventh to ninth clocks, the remaining instructions X1, X3, and X4 are on issue until the (VDR Write PATH0 BUSY) of the BUSY flag 9 that manages the signal line L1 is reset.

  At the 10th clock, since the processing of the instruction X2 is completed, (VDR Write PATH0 BUSY) of the BUSY flag 9 that manages the signal line L1 is reset.

  At the eleventh clock, the instruction X1 that is waiting for issuance at the A0 instruction issuance stage 6 that does not have the A0 instruction issuance stage priority flag 5 and the A0 instruction issuance stage order flag 16 is high. The A0 instruction issuance check circuit 10 outputs the issuance instruction 14 after confirming that the instruction X2 is reset after issuance (VDR Write PATH0 BUSY).

  At the 12th clock, when the instruction X1 is issued, the BUSY flag 9 (V0 Write BUSY, VDR Write PATH0 BUSY) is reset. The BUSY flag 9 is managed so that subsequent instructions cannot be used, and issuance of subsequent instructions is suppressed. Also, the A1 instruction issue stage priority flag 5 ′ (priority flag A1 → A0), the M0 instruction issue stage priority flag 7 (priority flag M0 → A0), and the M1 instruction issue stage priority flag 7 ′ (priority flag M1 →). A0), M0 instruction issue stage order flag 17 (order flag M0-> A0) is reset by issuing instruction X1 of A0 instruction issue stage 6, and then BUSY flag 9 (V0 Write BUSY, VDR Write PATH0 BUSY). ) Change to management.

  In the 13th to 15th clocks, the remaining instructions X3 and X4 wait for issuance until the BUSY flag 9 (VDR Write PATH0 BUSY) is reset. Since the instruction X3 set in the M0 instruction issue stage 8 is a V0 Write instruction, the instruction X3 waits for issuance until the BUSY flag 9 (V0 Write BUSY) set by the preceding instruction X1 is reset.

  At the 16th clock, since the processing of the instruction X1 is completed, (VDR Write PATH0 BUSY) of the BUSY flag 9 that manages the signal line L1 is reset.

  At the 17th clock, the instruction X3 in the M0 instruction issue stage 8 cannot issue instructions because the BUSY flag 9 (V0 Write BUSY) is set. For this reason, the M1 instruction issuance check circuit 11 ′ is in competition with the instruction X3 of the M0 instruction issuance stage 8 (VDR Write PATH0), and the low priority instruction X4 having the priority flag M1-> M0 is given M1 priority. After the arbitration is confirmed by the check circuit 13 ′, the issue instruction 15 ′ is output by overtaking the preceding instruction X3. If the BUSY flag 9 (V0 Write BUSY) is reset earlier than the competing resource (VDR Write PATH0 BUSY), the M0 priority check circuit 13 confirms the arbitration of the instruction X3 that does not have the M0 instruction issue stage priority flag 7. An issue instruction 15 is output and an instruction is issued.

  At the 18th clock, after the instruction X4 is issued, the BUSY flag 9 (VDR Write PATH0 BUSY) is reset. The BUSY flag 9 is managed so that subsequent instructions cannot be used, and issuance of subsequent instructions is suppressed.

  At the 19th clock, the BUSY flag 9 (V0 Write BUSY) is reset, but the instruction X3 cannot be issued because the BUSY flag 9 (VDR Write PATH0 BUSY) is lit.

  In the 20th to 21st clocks, the remaining instruction X3 waits for issuance until the BUSY flag 9 (VDR Write PATH0 BUSY) is reset.

  Since the processing of the instruction X4 is completed at the 22nd clock, (VDR Write PATH0 BUSY) of the BUSY flag 9 that manages the signal line L1 is reset.

  At the 23rd clock, the M0 instruction issuance check circuit 11 confirms that the BUSY flag 9 (V0 Write BUSY, VDR Write PATH0 BUSY) is not lit and the M0 instruction issuance stage order flag for the last remaining instruction X3. After confirming that 17 is not lit, the instruction X3 can be issued. The M0 priority check circuit 13 turns on the issue instruction 15 after confirming whether the issue stage instruction corresponding to the M0 instruction issue stage priority flag can be issued, and the instruction X3 is issued.

  At the 24th clock, when the instruction X3 is issued, the BUSY flag 9 (VDR Write PATH0 BUSY) is reset. The BUSY flag 9 is managed so that subsequent instructions cannot be used, and issuance of subsequent instructions is suppressed. The M1 instruction issuance stage priority flag 7 '(priority flag M1-> M0) is reset when the instruction X3 of the M0 instruction issuance stage 8 is issued, and then the BUSY flag 9 (VDR Write PATH0 BUSY) is set. Change to management.

  Since the processing of the instruction X3 is completed at the 28th clock, the (VDR Write PATH0 BUSY) of the BUSY flag 9 that manages the signal line L1 is reset.

  Here, as shown in FIG. 3, the operations up to the first instruction decode stage 101, the instruction decoder 102, and the second instruction decode stage 103 do not change in the conventional operation, but the resource match detection circuit 104 stores the preceding instruction. The resource coincidence between the instruction at the instruction issue stage 105 and 106 and the subsequent instruction stored in the second instruction decode stage 103 is detected, and when a match is detected, the instruction at the second instruction decode stage 103 is It cannot be set until 106 instructions issue instructions. Therefore, in the current instruction sequence, the instructions X1 to X4 are not arranged in the instruction issue stages 105 and 106. If the instruction issue stage in which the resource match is detected by the resource match detection circuit 104 is issued after the preceding instruction is issued, the subsequent instruction is issued. An instruction can be set. Instructions are issued in the order in which the instructions are received. If the instruction issue is delayed due to a resource factor other than the competing signal line L1 (VDR Write PATH0), the signal line L1 (VDR Write PATH0) cannot be used effectively.

[effect]
As described above, according to the vector processing device of the present invention, when resources compete between an instruction and a preceding instruction, many instructions can be entered in the instruction issue stage by flagging the competition relationship. Further, resources can be efficiently used by performing arbitration between an instruction and a preceding instruction and issuing from an instruction that can be issued with a high priority order.

FIG. 1 shows the configuration of a conventional vector processing apparatus. FIG. 2 shows the configuration of the vector processing apparatus according to the embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the conventional vector processing apparatus and the vector processing apparatus according to the embodiment of the present invention. FIG. 4 is a schematic diagram of the vector calculation processing device.

Explanation of symbols

1 first instruction decode stage,
2 instruction decoder,
3 Second instruction decode stage,
4 resource match detection circuit,
5 A0 instruction issue stage priority flag,
6 A0 instruction issue stage,
7 M0 instruction issue stage priority flag,
8 M0 instruction issue stage,
9 BUSY flag,
10 A0 instruction issue check circuit,
11 M0 instruction issue check circuit,
12 A0 priority check circuit,
13 M0 priority check circuit,
14 Issuing instructions,
15 Issuing instructions,
16 A0 instruction issue stage order flag,
17 M0 instruction issue stage order flag,
21-28 vector data register (VDR),
29-36 vector register (VAR),
37 Vector calculator (ADD0),
38 vector calculator (MLT0),
39 Vector calculator (MLT1),
40 vector computing unit (ADD1),
41 X-BAR switch,
101 first instruction decode stage;
102 instruction decoder,
103 second instruction decode stage;
104 resource match detection circuit 105 instruction issue stage (system 0),
106 Instruction issue stage (system 1),
107 BUSY flag,
108 Issue check circuit,
109 Issuing instructions,
110 selection instructions,
111 selector,

Claims (7)

An instruction decode stage where the instruction is set;
Multiple instruction issue stages;
A plurality of check circuits each corresponding to the plurality of instruction issue stages;
A resource match detection circuit that detects whether there is a resource match between the instruction set in the instruction decode stage and the instructions set in the plurality of instruction issue stages;
Comprising
The resource match detection circuit includes:
When the instruction set in the instruction decode stage is set in a free own instruction issue stage of the plurality of instruction issue stages,
Among the instructions set in the plurality of instruction issue stages, a flag corresponding to an instruction that matches the instruction used in the instruction issue stage and the resource to be used and whose execution order cannot be changed, Set in the flag storage area for each instruction issue stage included in the issue flag of the issue stage,
Among the instructions set in the plurality of instruction issue stages, a flag corresponding to an instruction that matches the instruction used in the instruction issue stage and the resource to be used and whose execution order can be changed, Set in the flag storage area for each instruction issue stage included in the priority flag of the issue stage,
The plurality of check circuits perform arbitration according to the order flag of the own instruction issue stage and the priority flag of the own instruction issue stage, and issue an instruction set in the own instruction issue stage based on the result of the arbitration ,
Vector processing device. The plurality of check circuits include:
The BUSY flag is used to check whether resources used by the instruction set in the self instruction issue stage are free, and whether there is an instruction whose order must be guaranteed in the predecessor instruction issue stage. Instruction issue check circuit to check with
As a result of the check by the instruction issue check circuit, if the BUSY flag is not set and the flag storage area for each instruction issue stage included in the order flag of the own instruction issue stage is not set, A priority check circuit that checks whether or not a flag is set in a flag storage area for each instruction issue stage included in the priority flag of the instruction issue stage;
With
The priority check circuit includes:
If the flag is not set in the priority flag of the self instruction issue stage,
Issuing an instruction of the self-command issuing stage;
Set the BUSY flag of the resource used by the instruction set in the self-issued instruction issue stage;
Reset the self-issued issue stage,
Of the flag storage area for each instruction issue stage included in the priority flags of the plurality of instruction issue stages, reset the flag of the own instruction issue stage,
Of the flag storage area for each instruction issue stage included in the order flag of the plurality of instruction issue stages, reset the flag of the own instruction issue stage,
When the instruction processing of the self-instruction issue stage has ended, it resets the BUSY flag of resources the set in the self-instruction issue stage instruction uses,
The vector processing apparatus according to claim 1. The priority check circuit includes:
Check whether it is possible to issue an instruction in the instruction issue stage corresponding to the flag in the flag storage area for each instruction issue stage included in the priority flag of the own instruction issue stage,
If the instruction in the instruction issue stage corresponding to the flag in the flag storage area for each instruction issue stage included in the priority flag is not issueable,
Issuing an instruction of the self-command issuing stage;
It sets the BUSY flag of resources the set in the self-instruction issue stage instruction uses,
Reset the self-issued issue stage,
When the instruction processing of the self-instruction issue stage has ended, it resets the BUSY flag of resources the set in the self-instruction issue stage instruction uses,
The vector processing apparatus according to claim 2. A first instruction decode stage in which the instruction is set;
An instruction decoder for decoding the instruction set in the first instruction decoding stage;
A second instruction decode stage, wherein the instruction decode stage is set with the instruction decoded by the instruction decoder;
The vector processing apparatus according to claim 1, further comprising: A method using a computer having an instruction decode stage and a plurality of instruction issue stages,
Setting an instruction to the instruction decode stage;
Detecting whether there is a resource match between the instruction set in the instruction decode stage and the instructions set in the plurality of instruction issue stages;
When the instruction set in the instruction decode stage is set in a free own instruction issue stage of the plurality of instruction issue stages,
Among the instructions set in the plurality of instruction issue stages, a flag corresponding to an instruction that matches the instruction used in the instruction issue stage and the resource to be used and whose execution order cannot be changed, Setting in the flag storage area for each instruction issue stage included in the issue flag of the issue stage;
Among the instructions set in the plurality of instruction issue stages, a flag corresponding to an instruction that matches the instruction used in the instruction issue stage and the resource to be used and whose execution order can be changed, Setting a flag storage area for each instruction issue stage included in the priority flag of the issue stage;
Performing arbitration according to the order flag of the self-command issue stage, the priority flag of the self-command issue stage, and issuing an instruction set in the self-command issue stage based on the result of the arbitration;
A vector processing method comprising: Issuing the instructions comprises:
The BUSY flag is used to check whether resources used by the instruction set in the self instruction issue stage are free, and whether there is an instruction whose order must be guaranteed in the predecessor instruction issue stage. Step to check in,
As a result of checking by the checking step, when the BUSY flag is not set and the flag is not set in the flag storage area for each instruction issue stage included in the order flag of the own instruction issue stage, the self instruction Checking whether a flag is set in a flag storage area for each instruction issue stage included in the priority flag of the issue stage;
With
The step of checking whether or not a flag is set in the flag storage area for each instruction issue stage included in the priority flag of the own instruction issue stage,
If the flag is not set in the priority flag of the self instruction issue stage,
Issuing a command of the self-command issuing stage;
Setting the BUSY flag of the resource used by the instruction set in the self-command issue stage;
Resetting the instruction issuing stage;
Resetting the flag of the own instruction issue stage in the flag storage area for each instruction issue stage included in the priority flags of the plurality of instruction issue stages;
Resetting the flag of its own instruction issue stage in the flag storage area for each instruction issue stage included in the order flag of the plurality of instruction issue stages;
When the instruction processing of the self-instruction issue stage has been completed, and resetting the BUSY flag of resources the set in the self-instruction issue stage instruction uses,
The vector processing method according to claim 5. The step of checking whether or not a flag is set in the flag storage area for each instruction issue stage included in the priority flag of the own instruction issue stage,
Checking whether an instruction of an instruction issue stage corresponding to a flag in a flag storage area for each instruction issue stage included in the priority flag of the instruction issue stage can be issued;
If the instruction in the instruction issue stage corresponding to the flag in the flag storage area for each instruction issue stage included in the priority flag is not issueable,
Issuing a command of the self-command issuing stage;
A step of setting the BUSY flag resources that the use self instruction issue is set in stage instruction,
Resetting the instruction issuing stage;
When the instruction processing of the self-instruction issue stage has been completed, and resetting the BUSY flag of resources the set in the self-instruction issue stage instruction uses,
The vector processing method according to claim 6, further comprising:

Images