JPS61180370A - Data processor - Google Patents

Abstract

PURPOSE:To attain the effective application of an arithmetic unit and a memory requester by holding plural instructions already read and changing the execution order of instructions in response to the using condition of the operator and with no logical conflict. CONSTITUTION:A main control unit U1 reads out plural designated instructions in response to the instruction reading requests given from an instruction reading unit U2 and delivers them to a signal line l3. At the same time, the signal showing the validity of the read-out instruction is delivered through a signal line l4. while the unit U2 sends these read-out instructions to an instruction control unit U3 one by one. In other words, the instruction and the instruction valid signal are put on the signal lines l6 and l5 respectively. Then the instructions are read out successively as long as no request is issued from the unit U3 for discontinuation of transmission of instructions and sent to the unit U3. Then the unit U3 decodes the instructions and sends the start signals, etc. to memory requesters U10 and 11, operators U20 and 21, etc. in response to the contents of those instructions. In such a way, the effective applications of operators and memory requesters are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program-controlled digital computer, and particularly to a digital computer suitable for executing vector operations at high speed (hereinafter referred to as a vector processor).

[Prior art]

Vector processors have been devised for high-speed processing such as large matrix calculations that frequently appear in scientific and technical calculations.

In particular, a vector processor with vector registers and a chaining function has been proposed in order to effectively exploit the high speed of multiple pipeline arithmetic units and improve the transfer ability of arithmetic data (US Pat. No. 4,128). ,880
issue).

A. Conventional devices have the following problems with chaining. This will be explained using a simple example of vector calculation.

FORTRAN statement Do 10 I=1. L 10 Y(I)=A(T)+B(I)IC(I) If this process is expressed in the form of a vector instruction, 1, Ve
cl,, or Load V RO←A2,
Vector Load V R14-B3
゜V ector L oad V R2←C
4.Vector Multiply V R3←
VRI*VR2 5, Vector Add V R4←VRO
+VR3 6, Vector Store VR4-'
) Y where V Ri represents the i-th vector register. Each vector instruction repeatedly executes calculations and data transfers for L elements.

On the upper side, the multiplication result of vectors B and C, which is an intermediate result before obtaining the final result, is temporarily stored in the vector register VR3, and only the addition result Y of this and vector A is stored in the main memory. Generally, in a vector processor equipped with a vector register, a vector of intermediate results of an operation is temporarily stored in a vector VRI, and only a final result vector is stored in the main memory. This substantially reduces the number of data transfers to and from the main memory. Therefore, by speeding up the write and read operations of the vector register, it is possible to ensure sufficient data transfer capacity necessary for calculations even though the access capacity of the main memory device is relatively low compared to this.

In this way, conventional vector processors employ a system in which multiple arithmetic units are installed and executed simultaneously, but at this time, due to the interrelationship of multiple instructions, even if these arithmetic units are vacant, It may not be used at all. Conventional vector processors read instructions in the order they are stored in main memory, determine whether they can be executed,
If it is executable, move on to execution. All computing units are in use.

Alternatively, if a register cannot be executed because it is in use, etc., many control systems wait until it becomes executable. In this case, the next instruction after the unexecutable instruction is an executable instruction. However, the arithmetic unit is not used because the decoding of the instruction is made to wait unconditionally.

[Purpose of the invention]

An object of the present invention is to hold a plurality of decoded instructions.

It is an object of the present invention to provide a data processing device that can change the execution order of instructions without logically contradicting itself according to the usage status of arithmetic units, thereby making effective use of arithmetic units and memory requesters.

[Summary of the invention]

For this reason, one aspect of the present invention includes means for holding a plurality of decoded instructions, means for detecting an executable instruction among the held instructions, and means for instructing activation of the executable instruction, The detecting means performs two checks: that the registers and resources required by the instruction are available, and that there is no register conflict with other instructions in the instruction holding means that were decoded before the instruction. The means is configured to detect an instruction that satisfies the condition as an executable instruction, and the means for instructing activation of the instruction is configured to detect an instruction that is decoded before the detected executable instruction. It is configured to be able to be activated before the instruction is activated. − As a result, when it is impossible to start the instructions that were decoded first, the instructions that were decoded later can be started first, making effective use of resources such as arithmetic units and memory requesters. can.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

■ Schematic device structure In FIG. 1, the main memory control unit Ul performs predetermined operations in response to memory requests (reading or storing vector data and reading vector instructions) from the instruction reading unit U2 and the memory requester U10゜Ull. Let's do it.

The instruction read unit U2 sends an instruction read request via a signal line Ql and an instruction address via a signal line Q2 to the main memory control unit Ul. In response to this, the main memory control unit U1 reads the plurality of instructions specified by this instruction address, and returns the read instructions to the signal line Q3 with a signal indicating that the instructions are valid placed on the signal line Q4. .

The instruction reading unit U2 puts the read instructions into an instruction buffer (not shown) and sends these instructions one by one to the instruction control unit U3. A command is placed on the signal line 116, and a command valid signal is placed on the signal line a5. The instruction reading unit U2 reads out instructions one after another and sends them to the instruction control unit U3, unless a request to stop sending out the instructions is requested from the instruction control unit U3 via the signal line Q7.

The instruction control unit U3 decodes the instruction and sends activation signals and the like to the memory requesters UIO and Ull, the vector register unit U4, and the arithmetic unit U20°Q21 according to the instruction.

■ Outline of operation (1) When the instruction execution start instruction control unit U3 starts instruction execution,
Set the necessary data on the signal line fill~Q14, set the activation signal on the line Q10, and then open the memory requester UI.
O, Ul 1 and vector register unit U4 or arithmetic unit U20. U21 and vector register unit U
Start on 4.

Here, the conditions for starting the instruction are that the necessary memory requester UIO or Ull or the arithmetic unit U20 or Q21 is not currently in use, and that the registers necessary for the instruction among the vector registers VR in the vector register unit U4 are not currently in use. This means that it is in a usable condition.

Here, whether or not a certain vector register can be used differs from whether or not that vector register is currently in use, as will be described later. Even if it's not in use.

Some vector registers cannot be used, and others can be used even though they are in use.

Instructions for which activation conditions are not met are registered in a sequence of instructions waiting to be activated, and subsequently, when an instruction that satisfies the activation conditions is decoded, this decoded instruction is activated first.

A signal line 1211 sends out an instruction code that specifies the type of operation of the instruction to be executed, such as addition and squaring, vector read, vector write, and the like.

Signal line Q12 specifies the register number used by the instruction. Here, each instruction can specify up to three registers. In this embodiment, the vector register unit U4 is provided with eight vector registers VRO to VR7, and the same number of vector address registers U5. A vector address increment register U6 is connected to memory requesters 0,1. Numbers O~7, 8~15, and 16~23 are assigned in advance to these vector registers, vector address registers, and vector address increment registers, respectively.

Signal line Q13 specifies the number of the memory requester or arithmetic unit to be activated. Here, there are three signal lines Q13: one specifies the memory requester, one specifies the arithmetic unit, and the other specifies the number of either the memory requester or the arithmetic unit used by the instruction. Since the number of memory requesters or arithmetic units is two each, only one line is required to specify these numbers.

Signal line Q14 specifies the number of vector elements to be processed.

Memory requestor UIO, Ull, vector register unit U4. Arithmetic unit U20. Q21 performs the following operations in response to the activation signal on line Q10.

(ii) Reading vector data from main memory When the execution of an instruction for this purpose is specified by the instruction code on line Ω11, the memory requester UIO, for example, reads the second and third signals specified on signal line Ω12. According to the register number, one each of vector address register U5 and vector address increment register U6 is selected to set the vector address and its increment therein. The memory requester UIO sends read commands, vector addresses, and address valid signals to signal lines Q20 and Q2, respectively.
1. It is sent to the main memory control unit Ul via Q23. The main memory control unit U1 reads the vector element data specified by this vector address from the main memory (not shown here), and sends the data FD and a data valid signal via signal lines (124, Q25). and returns it to the memory requester UIO.Memory requester UIO
connects this data and data valid signal to signal line Q2, respectively.
9. Q30 and sends it to vector register unit U4. In the vector register unit U4, the vector element data input from the line Q29 is stored in the vector register having the first register number designated by the signal line Q12. The memory requester UIO updates the vector address based on the set vector address increment value, and similarly reads the next vector element data based on the updated address. This operation is performed based on the number of vector elements specified by the signal line Q14. is repeated. When memory requester UIO sends the final vector element address to main memory control unit U1.

The final vector data signal is sent on line Ω32.

Main memory control unit U1 sends this signal on line 433 when outputting the final vector element. The memory requester UIO places the final vector data signal on the signal line Q2G at the same time as sending out the data valid signal of the final vector element. This signal is.

It is sent to the instruction control unit U3 to notify that this memory requester UIO is vacant, and is also sent to the vector register unit U4, where it is also used to control the end of vector register writing. The end of vector register writing is also known from vector register unit U4 to instruction control unit U3 via signal line Q15.

(iii) Storing vector data in main memory When an instruction to store vector data in main memory is executed,
The vector address and its increment are set in the memory requester UIO as in (ii).

In the case of storage, vector data is read out one after another from the vector register of the number indicated by the signal line 1212 in the vector register unit U4, and is placed on the signal line Q27, and a data valid signal is placed on the line f128. and is sent to the memory requester UIO, for example. The memory requester UIO further attaches a vector address to these, and writes a write command, a vector address,
Vector element data and data valid signals are transmitted through signal lines Q20. Q21. Q22, 1123 and sends it to the main memory control unit U1. When the vector data element to be sent is the final element, a final vector data signal is further sent to line Q32. The main memory control unit U1 further controls storage in the main memory.

When the required number of vector elements has been sent from the vector register unit U4, the final vector data signal is sent to the memory requester UIO via the signal line Q31, and the memory requester UIO performs the following as in case (ii). It is placed on the signal line Q26 and notified to the command control unit U3.

(iv) Vector operation Arithmetic unit U20 or U2 for executing vector operation instructions
When vector register unit U4 (here referred to as U3O) is activated, they operate as follows. Note that each arithmetic unit is capable of executing a plurality of types of operations required by various instructions.

The vector register unit U4 reads the first element data from the vector registers of generally two register numbers specified by the signal line Q2, and sends each data to the signal line Q41. Q42 and send the data valid signal to the signal line f.
143 and sent to the arithmetic unit U20. The arithmetic unit U20 calculates the two sets of vector element data according to the OP code on the line 1211, and then sends the results and the data valid signal to the signal line ρ45. The vector register write signal I- is sent back to the vector register unit U4 on ρ46.
At step 04, the result is stored in the vector register of the signal specified by the signal line Q12. These processes are sequentially performed on the primary element data.

When the last vector element is reached, the final vector data signal is sent from the vector register unit U4 to the arithmetic unit U20 via the signal line 1240, and in synchronization with the final result from the arithmetic unit U20, the vector data signal is sent again via the signal line Q44. Once returned to the register unit U4, this signal is also notified to the instruction control unit U3 at the same time, informing it of the vacancy of the arithmetic unit and the vacancy of the vector register.

In the above, vector element data is transferred in response to the machine clock, but if a pair of vector element data to be transferred is not available in two vector registers, the vector register unit U4 prohibits transfer until the pair of vector element data is available. do.

Therefore, vector elements are read or stored intermittently.

Note that the memory requester Ul1. The configuration of calculation unit 11U21 is memory requester U10° and calculation unit U2.
0, and the signal lines marked with a prime (") in FIG. 1 respond to those without it.

■Registers Before explaining the detailed operation, the formation of necessary registers will be described below. FIG. 2(a) shows the configuration of an instruction register (I register) in which instructions are set. Here, the OP field indicates the instruction code, R1, R2, R3
The field indicates the register number. Of course, the instruction itself has the fields shown in this figure. The registers indicated by the R1-R3 fields are a vector register, a vector address register, and a vector address increment register, and which register is designated depends on the type of instruction as follows.

(i) Instructions to perform calculations in the arithmetic unit (addition 2 multiplication instructions, etc.) R1: Vector register number in which the calculation result vector is to be stored R2: Vector data to be calculated (addend, multiplicand, etc.)
Vector register number where R3 is stored: Vector register number where vector data to be calculated (addend 1 multiplier, etc.) is stored Here, the R1, R2, and R3 fields all specify different vector registers. .

Note that the R3 field may not be used depending on the instruction (transfer instruction, etc.).

(ii) Instruction to read data from main memory R1: Vector register number to store data R2: Vector address register number R3: Vector address increment register number (iii)
Instruction to store data in main memory R1: Vector register number in which data is stored R2: Vector address register number R3: Vector address increment register number Figure 2 (b)
is the computing unit U20. U21. memory requester UIO,
Registers that control Ull (hereinafter sometimes referred to collectively as resources), namely, decode resource register (DS register), queue resource register (QS register), executable resource register (ES register), This shows the format of a register unit resource register (RS register), where the S, A, and N fields specify the use of a memory requester, the use of an arithmetic unit, and the number of the memory requester or arithmetic unit, respectively. Note that the DS register and QS register do not have an N field.

Figure 2(e) shows the registers involved in vector register control, namely the decode register register (DG register), queue register register (QS register), memory requester register register (MG register), and register unit register register (RG register). Indicates the format, where Vi (i = 1 to 3) field is Wi, a field that specifies whether there is valid data in the GNi field, W i l, the field specified in the next GNi field. A field that specifies whether the vector register is used for writing or reading; 'l' or #103 for writing and reading, respectively.
1, and the Ri Mitsuield of the instruction is set in the GNi field. In addition.

The MG register is GN2. It has only GN3 field.

FIG. 2(d) shows the format of the resource status word register (R5SW register) that controls the status of resources. Here, the SO, SL fields indicate whether the memory requester UIO, Ul 1 is in use, and the AO, At
The fields are each operated by arithmetic unit U20. Indicates whether U21 is in use (when in use, it is set as l'').

Figure 2(a) shows the format of the register status word register (RGSW register) that controls the state of vector registers, where fields WO to W7 indicate whether vector registers VRO to VR7 are in use for writing, respectively. The RO-R7 fields each indicate whether the vector registers VRO-VR7 are in use for reading (when in use, they are set to "1").

■Details of command control unit The details of each unit shown in FIG. 1 will be explained below.

Note that the main memory control unit (Ul in FIG. 1) and the instruction reading unit (U2 in FIG. 1) respond to access requests from two memory requesters UIO and Ull, and simultaneously handle access from these requesters. when a request is made.

It gives priority to one of them and accesses the main memory,
Since this is the same as what has been achieved in the past, it will not be explained here. Furthermore, timing inputs to flip-flops and registers are omitted. It is assumed that inputs of flip-flops and registers that do not receive control signals are always set at predetermined timings.

Referring to FIG. 3, the vector command read by the command reading unit U2 and the valid signal corresponding to the command are shown on lines n6. The instruction is sent through Q5, the instruction is set in the instruction register (register 2) r301, and the instruction valid signal is set in the flip-flop f30+. The instruction valid signal is also used as a signal to the register IR, r301. Unless the instruction control unit U3 sends a request to stop sending instructions on the line Q7, instructions will be sent one after another from the instruction reading unit U2. This interval is
■The instruction in register r301 is the decode instruction register.
(DI register) As soon as it is moved to r302, the next instruction is controlled to be input. ■Instructions set to register specification exceptions.

It will be transferred via four routes. DI register r30
2, the OP field is transferred. At this time, the output of the flip-flop f301 controls the setting of the DI register r302, and is also transferred to the flip-flop f302 via the AND gate g307. Here, the output of the specified exception detection circuit b316 is input to the AND gate g307 in addition to the output of the flip-flop f301, and this circuit b316 checks the R1 to R3 fields of the vector instruction set in the E register "301". and only if there are no register specification exceptions
Output. As a result, an instruction valid signal is set in the flip-flop f302. The instructions in registers IR, r3Ql are also. It is sent to the decoder b301, the resource to be used is determined by the ○P field, and the result is sent to the decode resource register (DS register) r30.
Sera 1- is done in 3. DS register "303 is shown in Figure 2 (
As shown in b), it has <S, A fields. However, there is no N field, and the decoder b301 inputs 1 to the S field when this ○P field uses memory requester UIO or Ull, and when this instruction uses operation block U20 or U21. Enter 1 in the A field. The output of AND gate g307 is also used to input these data in DS register r303. ■The instruction in register r301 is further sent to decoder b303, and its OP code, R1, R2, R
The contents of the 3 fields are decoded and the result is set in the decode register (DG register) r305. As shown in FIG. 2(c), the DG register r305 contains a field GN indicating the number of the vector register used by the instruction set to I register specification exception.
i (i = 1 to 3), a field Wi (i = 1 to 3) indicating whether the register is used for reading or writing.
) and a field Vi (i=1 to 3) indicating whether these fields are valid or not, and the decoder b303 has I
It decodes the instruction in register 301 and outputs the information in these fields.In other words, it is predetermined by the OP code of the instruction whether or not fields R1-R3 of the instruction are valid as register specifications, so the decoder b303 determines Vi based on the OP code.Also, whether or not the register field Ri determined to be valid is for writing is also determined in advance by the OP code, so the decoder b303 can determine the pit Wi by looking at the OP code. .The decoder b303 inputs the contents of the field R4 to the GNtN field.In this way, the input to the DS register r303 is determined.DG register r305
The outputs of the anime games 1 to g307 are also used to control the cents.

As is clear from the above explanation, DS register r303
The decoding results set in the DG register r305 and the instruction code set in the DI register r302 are for the same instruction, and hereinafter, each piece of data set in these registers will be referred to as an instruction, or they will be collectively referred to as an instruction. This is sometimes referred to as the instruction in the DI register r302. When an instruction is set to DI register r302; DS register r303; and DG register r305, it is next checked whether or not the resource can be activated.

The instruction queue register (Ql register) q301 is composed of three registers QTRO-Q for receiving the OP code of the instruction waiting for execution from the DI register 302 and transferring it to the register 1.
Consists of IR2. Similarly, the queue resource register (QS
register) q302 is these three registers QIRO~
The queue register register (QG
register) q303 is the OP in register QIRO~2
It consists of three registers QGRO to 3 that receive and store vector register use requests for codes from DG registers R and r305.

In the end, three instructions waiting to be executed are stored in registers q301-q302. Hereinafter, for the sake of simplicity, these three queue registers may be collectively referred to as an instruction queue register or instruction queue register q301.

As mentioned above, whether a resource can be activated for a newly set instruction in the DI register r302 is determined based on different criteria depending on whether or not an instruction is already stored in these instruction queue registers.

That is, there are the following cases.

(a) When there are no instructions in the instruction queue register.

(a-1) A case where the instruction in the DI register r302 is activated immediately.

(a-2) A case where the instruction in the DI register r302 cannot be activated immediately and the instruction must be placed in the instruction queue register.

(b) When the instruction queue register contains an instruction.

(b-1) When starting an instruction in the instruction queue register.

(b-2) A case where the instruction in the DI register r302 is activated even though there is an instruction in the instruction queue register.

The device operation in each case will be described below.

(a-1) When there is no instruction in the instruction queue register q301 and the instruction in the DI register r302 is activated.

This occurs when the resource (operator or memory requester) and vector register required by the instruction in DI register r302 are both available.

In this embodiment, each resource is configured to be usable by only one instruction at a certain time, and therefore,
Whether a resource is available or not depends on whether the resource is not in use or in use.

The resource availability status is determined as follows. Roughly speaking, a resource usage check circuit b305 checks the status of the requested resource specified by the DS register r303 and the resource managed by the R8SW register r304, and checks whether the requested resource is available via the line Q.
At 310.

The vacant resource number is output to Q309.

Details will be explained with reference to FIG.

The output of S field r3031 in DS register r303 is connected to AND gate g320. g321, and these AND gates g320 and g321 each have
Furthermore, the SO field r in R55W register “304”
3041°Sl field r3042 outputs are respectively inverted gates g335. It is input via g336. Therefore, the output of AND gate g3201g321 becomes '1'' when memory requesters 0 and 1 are requested to be used, and memory requesters 0 and 1 are free, respectively. g328. Therefore,
The output of the or game 1-g 332 becomes ``1'' when the requested memory requester O or I is free.

Also, and gate g320. The output of g321 is also input to encoder b320, and an available memory requester number is output. In other words, antgate g320
When the output of the encoder b320 is "B", regardless of the output of the AND gate g321, the output of the encoder b320 is "0" (indicating that memory requester 0 is empty), and the AND gate g3
When the output of the encoder b320 is “o” and the output of the anime game h g 321 is “bi”, the output of the encoder b320 is “1”.
(indicating the availability of memory requester 1) (in this embodiment, there are no more than two memory requesters, so the encoder has one output line). and gate g320
．． When both outputs of g32+ are O, encoder b3
The output of 21 may have any value. Similarly, regarding the empty state of the arithmetic unit, the output of the A field r3032 of the DS register r303 and the A field of the R35W register r304 are
O, AI field r3043. From the output of r3044 to the inverting gate g337. g338. and gate g32
2. g323, or gate g329, encoder b32
1, the instruction requests the use of an arithmetic unit, and if the requested arithmetic unit 0 or l is present, the output of the ORG+-g329 is "BI" and the arithmetic unit number is sent from the encoder b321. Output.OR gate g3
The output of 28°g329 is input to OR gate g332, whose output line Q310 indicates that the requested resource is free. On the other hand, encoders b320, b3
21 is selected by the selector 5310 and placed on the line Q, 3093, and the OR gates g32g, g
Line Q along with output lines Q3091 and Q3092 of 329
Output as 30 pieces. Here, orgate g32
By controlling the selector 5310 with the output of 9, when a request for use of the arithmetic unit is made and the arithmetic unit is vacant, the memory requester number is selected when the arithmetic unit number is other than that. Note that the contents of line Q309 are selected by selector 5302 and output to line Q320. Line 320 is signal line 3 indicating the availability of memory requester.
201, a signal line 3202 indicating the availability of arithmetic units; memory·
Consists of signal LA3203 indicating the number of the requester or arithmetic unit.

Selector 5302 selectively outputs signals on lines Q3091 to +113093, respectively. selector 53
02 connects lines Q309 and Q311 to input line Q321 #O
+l or rr 1 rr, and in this case, as described later, the input line Q321 is PA0'''.In this way, the vacant resource number among the requested resources is output to the line Q320. Ru.

Line Q320 is also input to decoder b302 and R55
It is used to set each bit of W register Y304.

Here, the decoder b302 includes a memory requester number decoder b3022 and an arithmetic unit number decoder b30.
21, each having a decode enable terminal E, and decodes the decode input signal only when E is 11111. The decoding valid terminal E of the decoder b3021 is connected to the line a32 of the line Q320, which indicates the vacant space of the arithmetic unit.
The input signal terminal where 02 is decoded has a line Q indicating the number.
3203 is connected. Similarly, decoder b302
Of the lines Q320, a line 123201 indicating an empty memory requester is connected to the decode valid terminal E of No. 2, and a line 123203 indicating a number is connected as a signal to be decoded.

Decoder b3021. The output of b3022 is the corresponding R5
Four fields r3 forming the 5W register r304
041-r3044 (all of which consist of flip-flops) is connected to the set terminal S of the line Q32.
01. Corresponds to the empty resource number input from Q3203. One of the SO, Sl, AO, and AI fields is set. In this way, resource use is checked by the single circuit b305, and the R35W register r304 is updated according to the check result.

Next, returning to FIG. 3, a check regarding the use of vector registers used by instructions in the DI register r302 will be described. The first check is DC register r30
Based on the usage request vector register number and usage type (read/write) shown in 5, and the vector register usage status in the RGSW register r306, the register usage check circuit b307 determines whether the instruction in the DI register r302 is required; The purpose is to check whether a register is currently available. In this case, it is assumed that there is no instruction in the instruction queue register q301. However, in general, instructions waiting for resource availability are stored in the instruction queue register 9301, and when the instruction in the DI register r302 is executed by overtaking the instruction already stored in the instruction queue register 9301, the 5-vector register 9301 is stored. Register conflict check circuit b to check if there is any conflict in the order of use
It is necessary to check in 309-b311.

This is the second check. Note that in this embodiment, this first. The second check is performed only on the vector register, not on the vector address register U5 or the vector address increment register U6. In this embodiment, for simplicity, the contents of these registers are not changed, and the configuration is such that two memory requesters can read these registers simultaneously (details will be described later).

Therefore, there is no need to check whether these registers can be used.

Figure 6a shows the details of the register usage check circuit b307 between the DG register r305 and the RS SW register r306.
It is expressed including.

R1 field r3051 in DG register r305
Based on the output of the RGSW register r306, the RGSW register use check circuit b3071 determines that the register can be used only in the case shown in FIG. 6(b). In other words, when the register use request is a write to a vector register (V!=W+=, l GNI<8), the number GNI
When the vector register of is unused (W i = Ri
=0.1=GN1), and when the use request is to read the vector register (Vl=1.W1=0.GNI<8),
It is determined that the vector register with the number GNI is usable only when it is unused or is being written (Ri=0, 1=GNI), and outputs ``1'' to the AND gate g343. v
When the i bit is '0''', the vector register can be used, and in this case as well, the AND gate g343 is set to rr.
1 Output rr. Similarly, R2 field r3052. of DC register r305. R3 field r3053
Regarding the second. Third usage check circuit b30
72, b3073, checked using exactly the same criteria,
The result is input to AND gate g343. thus,
When all the vector registers specified by the R1, R2, and R3 fields are available, ! A signal "1"' indicating that the vector register can be used is output to f1313.

Note that the register use check circuit b305 is characterized in that it determines that the register can be used even if the vector register required by the instruction in the DI register 302 is currently being written by a preceding instruction. This is because, as will be described later, in this embodiment, vector registers are chained so that a read operation can be performed in parallel with the write operation to the vector register in which the vector element is being written. be.

FIG. 7(a) shows register conflict check circuits b309 to b.
311 details are shown. Register conflict check circuit b30
9 is the first to third register conflict check circuit b3091
〜b3093, and each register r
R1-R3 fields of 305 r 3051- r 3
Vector register use request and QG indicated by 053
Conflicts between vector register use requests indicated by register q303b'' are checked. When there is no conflict, the outputs of these circuits become 'l'' (details will be described later). AND gate g353 connects these check circuits b3091-
Both b3093 outputs are 117″ or game hg3
59 to line Q315. On the other hand, or gate g
The output of the 1-inversion gate g356 is also input to 359. Therefore, input line Q32 to inverting gate g356
Even when 5 is 'O'', a signal II 1 +1 indicating no conflict is output to the line Ω315.The register conflict check circuits b310 and b311 are also connected to the circuit b309.
It has the same configuration as AND gate g354. g355 or inversion gate g357. g358, or gate g36
0. g361 outputs the conflict check result on line R316°9317.

Lines Q323 to Q325 represent flip-flops f304 to
f306 (Figure 3).

These flip-flops are connected to the instruction queue register (1
301 (FIG. 7), and is set when an instruction exists in these registers (details will be described later).

In this case, it is assumed that there is no instruction in the instruction queue register q301, so these flip-flops are set, and their output lines Q323, R324, Q32
5 is 110H. Therefore, line Q315
The outputs of ~Q317 are all 1. In this way, when there is no instruction in the instruction queue register q301, a signal indicating that there is no conflict in the vector register is generated regardless of the outputs of the conflict check circuits b309 to b311.

The explanation will be given by returning to FIG. 3 again. Output lines from the register conflict check circuits b309 to b31].

As mentioned above, Q315 to Q317 are set to ``1''. Therefore, the output 12322 of the AND gate g301 which receives these as input is 1. In this case, the register usage check circuit b307 Output line Q3
13 is also rr 1 rr on the assumption that the vector register can be used, and therefore the output of the AND gate g302 is also 111 II. Also,
The output line p310 of the resource usage check circuit b305 is also set to 1''' on the assumption that the resource can be used.
It has become. Further, the output line Q302 of the flip-flop f302 indicating that there is a valid instruction in the DI register r302 is also set to '1'.

As described later, the output of AND gate g305 is II O
Because of rH, the output of the inverting gate g310 is ``'1pa.'' When the output of the AND gate g304 is
The output of is also II l gg, and therefore, or game 1~
A flip-flop via the output line n330 of g306,
f303 is set. This flip flop f30
3 is a D type flip-flop that is set/reset only by timing.

An instruction activation signal ST is transmitted via line QIO to vector register unit U4, memory requester U10.Ull, arithmetic unit U20. It is sent to U21 (see Figure 1). Also,
Since there is no instruction in the instruction queue register q301,
111 when there is an instruction in registers QIRO to QIR2
Corresponding flip-flop f304 where II is set
The outputs of ~f306 are all it O71, and the selector 5 to which the output lines 323~Q325 are input
The output of the AND gate g303 is also "o" regardless of the selection operation (described in detail later) of the selector 53036. Therefore, the output line Q32.1 of the AND gate g305 to which this output line Q326 is input also becomes II OII. Selector 33
01.5302, 5304 are DI registers r
302, the operation code on the output line Q303, the resource use request (resource type 2 number) on the exit line Q309 of the resource use check circuit b305, and the DG register r3.
Vector register use request on output line Q307 of 05 (
register number, usage type) and select each El register r308. , ES register r309. Set the EQ register to 312. The setting is indicated by the line Q330. Note that the vector length register (VLR) r30
It is assumed that the vector length (VL) to be processed by another means (not shown) is stored in advance in 7. The contents of these registers are transferred by lines Ω11-1114 to the vector register unit U4, each resource U10°U1. It is sent to R20 and R21. With this,
This means that a command has been issued to start executing the command.

Note that here, since the instruction in the DI register r302 can be started immediately, there is no need to put it in the instruction queue register q301. In this case, since the output of the AND gate g304 is rr 1 rr, the inversion gate g3
The output of 08 becomes '0''', and the output line Q327 of AND gate g303 to which this output is input becomes II Og.
g. In this way, input of the contents of DI register r302 to instruction queue register q301 controlled by signal line Q327 is suppressed. Similarly, register q302. New input to q303 is also prohibited. Flip-flops f304 to f: 30 G indicating that an instruction exists in the instruction queue register g301
instruction queue register g3 to be set next.
An inpointer indicating a location in 01.

Suppress updates to IP, r310, etc.

Additionally, as the instruction starts, it is necessary to change the Rsw register r304, which manages the state of the resources used, and the RGSW register 306, which manages the state of the vector register.
4 was described in the explanation of FIG. R
To change the state of the GSW register 306, proceed as follows. In other words, the output of the DG register r305 selected by the selector 5304 is sent to the decoder b30.
4, where the vector register number.

Reads, writes, etc. are decoded and the corresponding bit in RGSW register r306 is set to 'bi'. That is, field Ri (i=1
~3), Wi is 1 on the condition that Vi=1.
Wj (
j=GNi) or Rj is set to 1. Further, as will be described later, in the RGSW register, a signal indicating that writing or reading of the vector register has been completed is sent from the vector register unit U4 to the line Q15. When input via Q16, the field Rj or Wj specified by this signal is reset.

(a-2) When there is no instruction in the instruction queue register q301, the instruction in the DI register r302 cannot be activated, and the instruction is placed in the instruction queue register q301.

This occurs when the resource (operator or memory requester) or vector register required by the instruction in DI register r302 is not available.

For checking the usage of resources and vector registers used by instructions in DI register r302,
This is as described in the explanation of (a-1) according to FIGS. 5 to 7. In this case, as a result of checking the usage status of resources and vector registers, the resource required by the instruction in the DI register r302 is in use, so the output Q310 of the resource usage check circuit b305 becomes "0".

Further, if the vector register required by the instruction in the DI register "302" is unavailable, the output Q313 of the register use check circuit b307 becomes '0'. In either case, the output of AND gate g304 is II Q #l
, Therefore, the output of the inverting gate g308 becomes '1''.

Also, since there is no instruction in the instruction queue register, (a
As mentioned in the explanation of -1), since the output line Q326 of the selector 5303 is 0'', the AND gate g30
5 is 0''. Therefore, the flip-flop f303 is not set to anything, and the instruction activation signal ST is on the line Q.
Not output to lO. The output of the inverting gate g308 is It
I II and the output of the flip-flop f302 is also 1'', so the output line Q of the AND gate g303
327 becomes II I It. As a result, the operation of putting an instruction into the instruction queue register is performed as follows.

Details of the instruction queue register q301 are shown in FIG. In FIG. 4, the output IP of the in-pointer (IP) register r310 is the number of the register to be set on the line Q327 when the set signal S to the instruction queue register is set on the line Q327.
28, the respective decoders b33
It is input to the decoding enable terminal (E) of 0 and the data terminal and is decoded. As a result, line a327 is 1117
When it is 1, the contents of line Q328 are decoded, and as a result, the contents of the input line (lines Q303, Q305, or R307 in FIG. 3) are set in any of the designated registers r350 to r352. The above is the setting to the instruction queue register (1301).The 'All output operation of the instruction queue register, which will be described later, will also be described here.
op) Output of register r311 (Figure 3) By outputting the contents of the register [350 to r351] with the number specified by OP, this
This can be realized by controlling the selection of the selector 5350 to which the output of No. 2 is connected using the output line Q329 of the ○P register r311.

Note that the QS register 9302 includes registers r350 to r3.
52 has the same structure as the instruction queue register q301 except for the difference in the number of bits required. QG register q3
03 differs from the instruction queue register q301 in that, in addition to the difference in the number of bits required by registers r350 to r352, there is also an additional signal line for direct output from registers r350 to r352 via selector 5350. Only.

The explanation will be given by returning to FIG. 3 again. In this way, the instruction code, the type of resource used by the instruction, and the register number are stored in the instruction queue register q301=q30.
To 3! When recording A, flip-flops f304 to f3 indicate that instructions exist in these instruction queue registers.
Of 06, the register QIRi (i
=0.1or2). This operation causes line Q327 to become II I II, which is input to the decode valid terminal of decoder b312, and input to the data terminal (output line Q328).
Flip-flops f304 to f3 with numbers designated by P
06 is set by the decoder b312. When the above is completed, the IP register r310 is updated. The output line Q328 of the IP register r310 is input to the ternary counter b314 to create the next IP value, and when the line Q327 becomes '1'', the I
The value of the primary pointer is set in P register r310. The ternary counter b314 inputs 1, 2, . It outputs O.

Note that once all instructions have been placed in the instruction queue register (up to three instructions can be queued here), no more instructions can be placed in the instruction queue register. It is necessary to suppress instruction sending. This is a flip-flop f304~ that specifies that an instruction exists in the instruction queue register.
This is realized by inputting the output of 306 to the anime games 1 to 309 and sending this output aQ7 to the instruction reading unit U2.

As described above, instructions waiting to be activated are stored in the instruction queue register q301 according to their decoding order.

(b-1) When starting an instruction in the instruction queue register.

This means that there is an instruction in the instruction queue register q301,
This occurs when the required resources and vector registers are available.

This is regardless of whether there is an instruction in the DI register r302 or whether the instruction can be activated. In this case, if there is an instruction in DI register r302, that instruction will not be executed, so according to the procedure described in (a-2), the instruction in DI register r302 is transferred to instruction queue register q301.
will be registered.

The following describes the process of taking out an instruction from the instruction queue register q301 and activating it.

The process of taking out and activating an instruction from the instruction queue register q301 is very similar to the process of activating an instruction in the Dr register r302. That is, instruction queue register r3
The instruction specified by out pointer register ``311'' in 01 and the instruction in DI register r302 can be exchanged.

Invoking an instruction requires that the necessary resources and vector registers be available (
It was also mentioned in a-1).

The availability of resources used by instructions in the instruction queue register q301 is checked by the resource usage check circuit b306 in Figure 3, and the availability of vector registers is checked by the register usage check circuit b30, also shown in Figure 3.
It will be held at 8.

The details of the resource usage check circuit h306 are the same as the check circuit b305 as shown in FIG. The type of resource required by the instruction in the instruction queue register q301 selected by the out pointer, OP, is input from the QS register 9302 via the gland Q318.

On the other hand, the resource status is input from the R35W register "304. These are the
4~ is compared by 327 to check the resource availability, and as a result, or gate g330゜g331
．． g333, encoder b322°! +323-Selector 8311 and the like ultimately place the result on a line Q312 indicating that the resource is vacant and a line Q311 indicating the type and number of the resource. The above operation is performed by DS
The operation is exactly the same as that of the resource usage check circuit b305, which places the results on the lines Q310 and Q309 by checking the register r'303 and the R35W register r304, so a detailed explanation will be omitted.

The configuration of the register use check circuit b308 is the same as that of the check circuit b307, and its operation is performed by using the third register instead of the output of the DG register r305 in FIG. 6(a).
The operation is the same as that of the circuit b307 when the output line Q319 of the QG register q303 in the figure is connected. The result of the check is placed on the output line Q314 (FIG. 3) of the register usage check circuit b308.

The explanation will be given by returning to FIG. 3 again. The resource usage check circuit b306 outputs ``1'' to the signal line Q312 indicating that the resource is vacant, the resource type 2 number at that time is output to the line 111311, and the register usage check circuit b308 outputs the vector II 11 on signal line Q314 indicating that the register is available
7 is output, and the flip-flops f304 to f3
The output line Q326 of the selector 5303 that selects the output of 06 when the out pointer OP is O~2 is "l".
” (meaning that there is an activatable instruction in the register Q I Ri in the instruction queue register specified by the out pointer), the output lines f1321 of the anime games 1 to g305 become ``BI''. When this output line Q321 becomes #1 n, selector S301.5302,5
3041. Output line Q304 of l-removed instruction queue register q301. The contents of the output line Q311 from the resource use check circuit b306 and the output line 319 from the QG register q303 are selected and sent to the EI register r308, ES register r309. EG register r31
2, set the instruction code, resource type and number, register number, and usage pattern. Therefore, if the instruction in the instruction queue register q301 can be activated,
It can be seen that the former instruction is activated regardless of whether the instruction in the DI register 302 can be activated or not.
Q321 sets the flip-flop f303 via the OR gate g306 and becomes a vector register unit.

A command activation signal ST is sent to each resource via line Q10. The output line Q330 of the OR gate g30G is El
register r308. ES register r309. It is also used to control the set of EG register r312. The instruction activation is exactly the same as the explanation in (a-1). Furthermore, the signal of Pavi' on line Q321 is applied to the inverting gate g3
10 closes the AND gate g301. As a result, the output of 1 inversion game 1''g308 becomes 'l'', and D
When the I register r302 contains an instruction (when the flip-flop f302 is '1'), the line a327 is set to '1' and the instruction is controlled to be registered in the instruction queue register. This process is as described in (a-2). The line 12321 is also connected to the decoding enable terminal of the decoder b313, and the decoder b313 is connected to the flip-flop f30 specified by the out pointer, OP.
4 to f306. This is OP
The instruction in the instruction queue register specified by is fetched,
This is because it is activated. Finally, line Q321 is used to set the OP register r311, and the out pointer is updated. This update control is performed in ternary format, as in the case of the inpointer. Generation of ternary value is performed by circuit b314
This is performed in a circuit b315 having the same configuration as .

(b-2) Even though there is an instruction in the instruction queue register, the instruction in DI register r302 is activated first.

This occurs in the following secondary cases.

(1) The resource or vector register required by the instruction in the instruction queue register is unavailable and the instruction cannot be activated. and (2) the resource or vector register required by the instruction in DI register r302 is available, and
There is no vector register conflict between the instructions stored in the instruction queue register q301 and the instructions in the DI register r302.

To overtake the instructions in the instruction queue register (1301) and start the instructions in the DI register 302 first,
There is no register conflict; that is, the instruction in DI register r302 does not use the vector register that is modified by the instruction in instruction queue register q301, and the vector read by the instruction in instruction queue register q301 is For registers, DI register r30
It is necessary that the instructions in 2 do not change. There is no problem with reading a vector register that is only used for reading by an instruction in the instruction queue register with an instruction in the DI register, because even if the instruction overtakes the vector register, the order in which the registers are read is simply reversed. . The circuits that perform the register conflict check described above are the circuits b309 to b3 in FIG.
It is 11.

The details will be explained based on FIG. 7.

The details of the circuit in FIG. 7 have already been described, except for the details of circuits b3091 to b3093.

The register conflict check circuit b3091 compares the R1 field r3051 of the DG register r305 with the R1 to R3 fields of the QGRO register g3030, and if any of the following conditions is not met, a signal 111 u indicating that there is no register conflict is detected. is output to AND gate g353.

(1) DGL/distor Vl=1. W1 = C1), in one field Rj of register QGRO, yj = Wj = l, GNj = NI of DG register (2) DGL/register (7) Vl = 1. W1=1(
7) Time.

In one field Rj of register QGRO, Vj=l, GNj=DGL/register (7) Similarly to GNI, R2 field r3052. of register DG. For R3 field r3053, the second . Third register conflict check circuit b3092. b3093 performs a similar check.

On the other hand, the output of the flip-flop f304c (see Figure 3) indicating that an executable instruction is stored in the instruction queue register is input to the AND gate g353 via the line Q323, and all the inputs of the AND gate g353 are When is "I", the output of 2 is passed through OR gate g35G and placed on line Q315. In this way, the vector register specified by DG register r305 becomes register Q
It is checked whether there is any conflict with any vector register specified in GRO. Similarly, D
A vector register specified by G register r305,
The competition relationship between the vector registers specified by the register QGRI is checked by the check circuit b310 and by the DG register r305.
A check circuit b311 checks the competitive relationship between the vector register specified by the vector register specified by the register QGR2 and the vector register specified by the register QGR2, and the results are sent to the respective AND gates g354. After g355, orgate g360.
The output line of g361 is placed on Q316゜Q317.

To check the usage status of resources and registers required by instructions in DI register r302, see (a
The details are as described in the explanation of the process in -1).

As a result of the check, in FIG. 3, as the output of the resource use check circuit b305, a signal of "l" indicating that the resource is available on the line Q310 is output on the line Q309.
The resource type 2 number is register usage check circuit B
As an output of 307, a ``BI'' signal is output on line Q313 indicating that the vector register is available.

On the other hand, since either or both of the resources and vector registers used by the instruction specified by the out pointer OP in the instruction queue register are not usable, the output line Q312 of the resource usage check circuit b306
Or, the output line Q of the register usage check circuit b308
At least one of 3I4 is set to P0''''. Further, since an instruction exists in the instruction queue register, the output line Q326 of the selector 5303 becomes II L H, and since an instruction exists in the DI register r302, the line Q302 also becomes rr 1 rr.

Under such circumstances, the output line Q321 of the AND gate g305 does not become re 1 , g.

In this case, it is assumed that there is no conflict between the registers required by the instruction in the DI register and the instruction in the instruction queue register, so lines Q315 to Q317 become II 1 gg, and the output of Antogame h g 301 becomes II 10. and the output of AND gate g301.

The output of AND gate g302 to which line Q313 is input becomes (L 1 +1, and this output 111'g and line Q3
10, a line Q302 indicating that the DI register contains a valid instruction, and the output of the AND gate g304, which is an output obtained by inverting the line Q321 with an inverting gate g310, outputs re 1 gg. Become. Thereafter, the process up to activating the instruction is exactly the same as the instruction activation process in the DI register in (a-1). In addition,
Since the output of AND gate g304 is 11111, the output line Q327 of AND gate g303 to which the result of inverting the output by inverting gate g308 is input, and the line Q321 mentioned above are both IIO, J.

Neither the IP nor the OP is updated, and the states of the flow knobs 304 to f306, which indicate that an instruction exists in the instruction queue register, do not change.

(2) Modification of Command Control Unit The details of the command control unit 1-03 (see FIG. 1) have been described above. In this embodiment, the overtaking of instruction execution is D
This is carried out only between the I register r302 and the instruction queue register, and once an instruction enters the instruction queue register, it is taken out in the order in which it entered the instruction queue register by the pointer from 1 to the instruction queue register. There is no overtaking of instruction execution between the two. However, overtaking execution between instructions in this instruction queue register is also
This can be easily realized by controlling in the same manner as the execution of the instruction in the register and the instruction in the instruction queue register. In this case, it is necessary to remember the execution order of the instructions on the instruction queue register. In addition, registration of instructions to the instruction queue register is also done using the in-pointer (I
The registration is not performed in the order specified by P), but is performed in an empty register.

FIG. 8 mainly shows the parts of the circuit for realizing this that are different from the circuit of FIG. 3. In the figure, flip-flop f304. f305, f306 are
This is a flip-flop that indicates that a valid instruction is contained in the instruction queue register (when it is contained, it is set to II i '1), and the flip-flops f304 to f30 in FIG.
It is the same as 6. When the output of this flip-flop is inverted by inverting gates g380 to g382 and input to a priority encoder b395, the number i of the smallest number among the empty registers in the instruction queue is outputted. In this modification, I
In place of P register r310, ternary counter b314, inverting gates g380 to g381 and priority encoder b395 are used, and the output of the priority encoder is used as inpointer IP instead of IP in FIG.

Furthermore, it is necessary to remember the activation order of the instructions in the instruction queue register q301.

In this modification, flip-flops f380 to f382 and an execution order changing circuit b393 are added to the circuit of FIG. 3. If the instructions set in the instruction queue register q301 with IP=O~2 are named QO, Ql, and Q2, then these instructions are written as QO→ Ql →Q2 QO−+ Q2 →QI Ql−)Q2 → QO Ql → QO−+ 02 Q2 → QO → QI Q2 → Ql → QO may be activated in this order. These six states are stored in flip-flops f380 to f381. flip flop f 380. The relationship between the storage information of g381°[382 and the instruction execution order at this time is shown in the following table.

f 380 f 381 f 382 Instruction execution order 0 0 0 QO-)
Ql →Q20 0 1 Q
O→Q2→Q10 1 0
Ql->Q2→Q00 1 1
Ql → QO → Q21 0
0 Q2→QO-+Q11 0
1 To change the execution order of Q2→Q1→QO instructions, flip-flops f304 to f306 are
” to “O” (from in use to not in use). This change is controlled by the change control circuit b39.
It is 3.

The circuit b393 includes flip-flops f304 to f30.
6 outputs Q323-Q325 and outputs Q396-Q380 of flip-flops f380-f382 representing the current activation state.
Q398 is input and the next activation state is on lines Q376 to Q3.
78, and the flip-flops f380~'
It is set to 382. Inside the circuit b393, one instruction in the instruction queue register q301 is activated and the line Q
323-(1325 captures the point in time when it changes from pavi' to "o", creates an output from the contents of lines Q396-Q398 as follows, and places it on lines ρ376-Q378.

That is, the remaining two instructions in the instruction queue register q301 are activated first, and at this time, the activation order of these two instructions is such that the flip-flops r380-f
382, and set flip 20 knobs f380 to f382 so that after activating these two instructions, the instruction newly stored in the instruction queue register will be activated instead of the currently activated instruction. do.

(]) When MQ323 becomes II [,,→rl O'p.

(2) When the line Q324 changes from "bi' to "o",
(3) When the line Q325 changes from ``l'' to ``o'', the lines Q323 to Q325 change from ``bi'' to ``o'' at the same time.
o'' because it is activated one by one.

In order to be able to start any instruction in the instruction queue register q30+, check the resource and vector 1 register usage status for all instructions in the instruction queue register, and It is necessary to check for conflicts in registers between all instructions. In Figure 8, register q30
20~q 3022 (Q S RO/ 1/2
) holds the type of resource required by the instruction in the instruction queue register q301, and is similar to the QS register q302 II in FIG. However, in this modification, a signal g line is provided to directly send out a resource use request from each register q3020 to q3030, regardless of ○P. The RSSW register r manages resource requests for each instruction and resource status.
The content of 304 is 5Resource usage check circuit b in Figure 3
306 is checked by resource usage check circuits b380 to b382 provided in this modification, and a signal indicating whether or not the resource is vacant is sent from each to line 12.
380 to Q382, the types and numbers of available resources are output to lines Q383 to Q385.

The resource use check circuits b380 to b382 are the fifth
It has exactly the same configuration as the circuit b305 explained in the figure. In FIG. 8, QGRO to QGR2 register q30
30~(!3032 stores the register number etc. required by each instruction in the instruction queue.
This is in the G register q303. R that manages register requests for each instruction and the state of vector registers.
The contents of the GSW register r306 are 9.Register usage check circuits newly provided in the modified example b383 to b
385, and a signal indicating whether all requested vector registers are available is sent to Q386-Q38.
8 is output. These register usage check circuits are exactly the same as the circuit b307 described in FIG. In addition, register conflict check circuits b386 to b391 newly provided in the single modified ffl+ are used to check conflicts between the standard registers required by each instruction. We want to allow any order of execution of the instructions in the instruction queue register. There is a station that can hold 3 instructions in the instruction queue register. Two check circuits are required in order for one instruction to be activated with priority over the other two instructions, which is equivalent to h-3 instructions, so a total of 6 check circuits are required.
register conflict check circuits b386 to b391 are required.

The circuit b386 receives the R1-R3 field 1- of QGRO and the R1-R3 field of QG R1, and the former performs a register conflict check on each of the latter.
When no register conflict is detected in any field, II II II is output on line Q390. It has the same configuration as the register conflict check circuit b309 in FIG. The output line Q324 of the flip-flop f305 is also input to the circuit b386, and similarly to the circuit b309 (Fig. 7), when this signal line Q324 is "0",
Unconditionally line Q, 390 to II 11. Output. Similarly, in circuit b387, each field of QGRI is QGRO.
This is a circuit that checks whether there is any register conflict for each field in the field. Similarly, circuits b688 to b391
are QGR2 to QGR2, QGR2 to QGRI, QGR2 to QGRO, and QGR
This is to check the register conflict of QGRO with respect to 2. These register conflict check circuit b386
Output lines Q390 to Q395 of ~b391 are manually inputted to an instruction selection circuit b394. The instruction selection circuit b394 includes the resource usage check circuits b380 to b38 described above.
2 output lines Q380 to Q382, output lines Q386 to Q388 of register use check circuits b383 to b385,
Flip-flop f380~ that specifies the instruction activation order
Output of f382 and flip-flop f30 indicating that an executable instruction is in the instruction queue register
Output lines Q323 to Q325 of 4 to f306 are also input,
Vector register, resources are empty, full 1
When using the ~le register, an instruction in the instruction queue register that does not cause a conflict is selected by the instruction selection circuit b394, and the number of the selected instruction in the instruction queue register becomes 0.329 as an out pointer ○P. A signal indicating that the instruction queue in the instruction queue register has been selected is output on line Q321.

Details of the instruction selection circuit b394 are shown in FIG.

The AND gate g383 has a flip-flop "304
Output 5Q 323, resource usage check circuit b38
0 output line 12380. Output line Q386 of register usage check circuit b383, register conflict check circuit b386. The output line 1390.395 of b39+ is input, and when these inputs are LL I ++, the output line Q370 of Antogame 1-g 3 g 3 is "
]”. This is the 0th position in the instruction queue register.
Indicates that the numbered instruction QO may be executed. Similarly, the first . The signal line related to No. 2 is input, and the line Q371
゜Output to Q372. The line Q370-Q372 is.

It is also possible that it becomes "t" at the same time. rear Q370-
Q372 is input to or gate g387, and if any one of them can execute the command, it is input to or gate g38.
The output line Q321 of No. 7 is designated as II 111.

The instruction execution order determining circuit b395 selects one of the signals output to lines Q370 to Q372 indicating that the instruction is executable. The circuit b395 has a line Q37.
In addition to 0 to Q372, output lines Q396 to Q398 of flip-flops f380 to f382 indicate the instruction execution order.
is input, and the number on the instruction queue register to be executed is output to line Q329 as follows. There are actually two lines Q329 (7) lQ3290 (upper), Q329L
(lower), and the binary numbers 00, 01°10 are represented by two lines indicating the number of the instruction in the instruction queue register.

(1) Lines l1396 to Q398 are “o” “o” “o”
” Q 370 Q 371 Q: 372
Q:'1290 Q 32!111
* * OO (* indicates don't care) (2) Ji! 1Q396~Q398 is rl Orr #
l O++ When 1″ Bi’ Q 370 Q 371 Q 372 Q 32
90 Q 3291i * *
o.

(3) jljAQ39G-Q39B is II Ou +1
1 ++ II When O++ Q 370 Q 371 Q 372 Q
3290 Q 3291* 1
*0 1 (4)!
When ff396-Q398 is "O""1""l" Q 370 Q 371 Q 372 Q
3290 Q 32910 0 1
1 0゜* 1*
O1 (5) Line Q396-2398 is “1” “O” “O”
When Q 370 Q 371 Q 372 Q
3290 Q 3291* *
l I 0(
6) ap396-n39s is “1” “0””
Q 370 Q 371 Q 372 fl 3
290 u 3291 * * I
In FIG. 3, the output of the I/O direction selection circuit b394, the line Q329, and the line Q321 are respectively the output of the out pointer (○P) register r311 and the line Q3.
It can be used in place of the output line Q321 of 29 and Antogame 1 to g305. therefore.

3rd II Arara 1 - Pointer register r311. Ternary counter b315, selector 5303. Antoge h g
305 becomes unnecessary.

Note that the selector 5380 in FIG. 8 indicates the type of resource required by the instruction in the instruction queue register.

Select the number according to the 1-pointer (located on line Q329) and this output line Ω311 is 5.

It is used in place of the output line of the resource usage check circuit b306 in FIG.

As described above, according to the present invention, the instruction control unit decodes read instructions one after another, activates instructions that can be activated one after another, and places instructions that cannot be activated into an instruction queue register. Then, when the vector 1 to 1 register with an empty resource becomes available, the resource and the vector 1 to 1 register can be used by activating instructions regardless of the order in which they are decoded, provided that there are no restrictions on the order in which vector registers are used. It is possible to shorten the idle time and process instructions in a shorter time.

(2) Vector Register Element No. 1 to (1) Overview In FIG. 10, the vector register unit U4 is divided into a vector register control unit I-'U 40 and a vector register data unit I-041.

In the vector register control unit hU40, based on the commands from the command control unit 1 to U3, the vector register V is set in the vector register data unit 1 to 041.
The necessary data is read from R, and the arithmetic unit [J20. U21
, control sent to memory requester U20°0+1 (FIG. 5), and arithmetic unit 1J20. U21. Controls writing of data sent from memory requester U10°Ull into vector register VR. Also, the instruction control unit U3 terminates the use of the vector register VR.
Let me know.

Each of the vector registers VR holds three vector elements, but here it is assumed that it is constituted by a memory element as in the prior art. Therefore, an address counter (
(Details will be described later) exist for each solid register VR.

These address counters are controlled by vector register control units 1 to U4O.

It should be noted that the readout of vector elements from vector register VR is carried out in a linear manner under the control of vector register control units 1 to U40. In this embodiment, by executing a certain instruction.

When an element of vector data is written to a certain vector register VR, if there is a subsequent instruction that wants to read the entire register, the write operation is executed as soon as an arbitrary number of elements have been written to this vector register. Chaining of all registers is performed so that read operations are started in parallel. Moreover, in this chaining, if the write operation by the preceding instruction is performed intermittently, the read operation by the subsequent instruction is also performed intermittently. Furthermore, a certain instruction has two edges 1-
When using vector registers, even if only some vector register elements are written to at least one of these vector registers, the vector elements written to these vector registers are Start reading out elements with the same number in pairs. Moreover, if the remaining elements to these vector registers are publicly input, each time a pair of elements of the same number -n become readable at the same time, the elements of this pair are read. put out.

The vector data supplied to the operation 'JA'j is normally read out from the memory, stored in the vector register, and then supplied to the 'JA'j. is performed in synchronization with the machine clock, but the unreadable elements read from main memory are processed every machine cycle due to read contention on main memory (for example, which occurs when two memory requesters operate simultaneously). It is not always written to the vector register continuously. At this time, the vector element data supplied to the arithmetic unit intermittently arrives at the vector register and is written into the vector register. Even in the original, the read operation (!) is performed in parallel with the !
Chaining) is 11, and the command is 2 solid 1
- When a single register is required, the operator is asked to specify the single value of the same vector element number in the two single registers.
- By simultaneously supplying 0 (zero) data,
Three things can be done to speed up the start of command execution.

(11) Overview of vector register control unit 1 to vector register control unit 1 to U40, as shown in FIG. Control circuits b410 to b417 and arithmetic unit U20. Operand control circuits b420 to b423 corresponding to U21 and memory requestors UIO and Ull, respectively, and flip-flops f400 to f407 holding outputs from operand control @paths b420 to b423, respectively.

Resource-register conversion circuit (hereinafter referred to as SG conversion circuit) b401. b404. b405, register resource conversion circuit (hereinafter referred to as G-3 conversion circuit) b402. b
Consists of 403. a-5 conversion circuit b402. b403 is a - for reading specified by the instruction control unit U3.
or for two vector register numbers. The operand control circuit b/I20 sends signals from any two of the vector register control circuits b410 to b417 to the resource numbers designated by the instruction control units 1 to U3.
It is sent to - of ~b427.

SG conversion circuit b401 (or b404 and b4'
05) converts the signal sent from the resource with the number specified by the instruction control unit U3 (or the operand control circuits b420 to b427 for this) into the writing solids 1 to 1 specified by the instruction control unit U3.
The signal is sent to one of the vector register control circuits b460 to b467 (or the vector register of this number) corresponding to the vector register number.

First, the instruction activation control circuit b400 starts the instruction control unit U.
3, start signal (on line Q10), instruction code (on line 12)
11), register number (on line Q12), resource type number (on line Q13), and processing vector length (on line Q14), and if the instruction code requires the use of vector registers, use the following: Operate.

(1) SG conversion circuit, b401. b404゜b405
．． The resource numbers and vector register numbers necessary for conversion, and their set signals are sent to the G-S conversion circuits b402 and b403.

(2) Vector register control circuit b41Q to b41
7, the one with the specified vector register number,
Issues a write or read start signal.

(3) Among the operand control circuits b420 to b423, the circuit corresponding to the specified resource type and number is
For instructions that do not use vector length data, its set signal, or at least one operand, a signal indicating this is issued.

When an instruction is executed, a control signal is transmitted in a first-order manner. Here, the operation at the time of execution of an instruction to read data from vector registers 0 and 1, perform arithmetic operations on arithmetic unit 0, and write the result to vector register 7 will be described.

When it becomes possible to read a certain vector element in the vector register O, a vector register read permission signal is output from the vector register control circuit b410 to the line Q480.
Sign. Similarly, the vector register control circuit b411 also outputs a full register read permission signal for the vector register I to the line Q481. G-3 conversion circuit b
Line Q480 at 402°b403. The signal of Q481 is transmitted to the output line Q490, 0500 for the arithmetic unit O, and is input to the operand control circuit b420. The operand control circuit b420 creates a vector data sending signal for each vector element on the condition that these vector register read permissions (:'i exist simultaneously), and outputs them to the S20. This signal is once received by the flip-flop f401 and then sent to the line Q43.
The data is sent to the arithmetic unit 0 as a data valid signal. on the other hand,
Data transmission on line Q520 (No. 1 is S-C conversion circuit b
404. b405 is also input, each is solid 1
- line Q540.corresponding to register number 0°1. Q55
1, respectively, and read address counters for vector registers O and 1 in vector register data units 1 to U41 (see FIG. 10) by lines Q470 and Q471, respectively (described later) is used for updating. In the present invention, after the vector element data sending signal (on line Q520) is created, the address counter (described later) for reading the flat data is activated.

One of its features is that it updates to the next address.

The operation of actually reading data is performed after confirming that it is possible to read data from two operands (vector registers O and 1 in this case).

Now, the data valid signal v (on L@1243) and the solid 1
~ element data is sent to the arithmetic unit 0, and when it is calculated, the calculation result is sent to the vector 1 register data unit hU41 via the line Q45 (Fig. 10), and the data valid belief V is sent to the line 24.
6 through the register control unit y h U 4
Return it to 0! Sign. This data valid signal (2) is transmitted by the SG conversion circuit b401 to aQ437 corresponding to write vector 1 register #7. In response to the signal on line Q437, vector register control circuit b417 controls ! to vector register 7. In addition to transmitting the F-included address j ~ ゛ address counter update signal to the vector register data unit 1 ~ [J41 via gl 127, it also writes to any side 1 ~ element of the vector register control circuit command code. Used to manage small pointers (described later). This pointer is
- This is used to control reading of vector elements up to the input vector element when the vector register is used for reading in a subsequent instruction while writing to the vector register 7.

When sending the final vector element to arithmetic unit 0, operand control tH circuit b is used to specify that the final vector element is final.
From 420, the final vector data signal E is output to line Q510 in synchronization with the solid data transmission signal. In other words, the circuit b420 is configured to memorize the processing vector length that is set at the start of critical execution, and output the final beta data signal after issuing this number of beta data sending signals. ing. This signal is once stored in the flip-flop f400 and then sent to the line 240 in the calculation r10.
The same J[(, te, line ρ4
4, it is returned to the SG conversion circuit b401. Line Q
44 is transmitted to the line Q427 corresponding to the vector register 7 by the SG conversion circuit b401, and input to the vector register control circuit b417. The control circuit b417 terminates the write operation to the vector register 7, and also sends the instruction control unit U3 to the vector register 7 via the line 12I6.
- Informs that writing to register 7 has been completed. on the other hand,
The final vector data signal E on the output line R510 from the operand control circuit b420 is sent to the SG conversion circuit b404.
b405, is output to lines Q530 and Q531 corresponding to vector registers 0 and 1, and further passes through OR gates g410 to g411 to lines Q460. Q
461, the vector register control circuit b410. b
411 to terminate the read operation of the vector register, and the command control unit U is input to the line Q15.
3 to inform that the reading of vector register 0.1 has been completed.

(iii) Instruction activation control circuit As shown in FIG. 12, the instruction activation control circuit b400 receives an instruction activation signal ST, an instruction code use register number, and a usage pattern input from the instruction control unit U3 through lines Q10 to QL4, respectively. .

The resource type and number used and the processing vector length are stored in the flip-flop f410 and register RGR, respectively.

r400. RIG, r401. R2H, r402゜RV
Both IR and r403 are set in response to the instruction activation signal ST.

The output of the flip-flop f410 is sent out via a line Q419 as an information set signal to the S-G/a-S conversion circuits 402 to 405 (FIG. 14) and others.
Used to create various data signals internally.

From the contents of RGR, r400, SG conversion circuit.

The register number given to the G-8 conversion circuit (Figure 11),
Creates an initialization/activation signal to be given to the vector register control circuit and vector register data unit. A normal vector instruction uses a write vector register in the RI field and a read vector register in the R2/R3 fields. For this reason, the SG conversion circuit b4 in FIG.
In 01.

The register number of the R1 field is converted to the G-5 conversion circuit b4.
02, it is sufficient to give the register number of the R2 field to the S-G conversion circuit b404, and the register number of the R3 field to the a-S conversion circuit b403 and the S-G conversion circuit b405. As mentioned in the explanation, in the instruction to store vector data in main memory, R1
Since the field specifies the vector register number for reading, it is necessary to transfer the register number of the R1 field to the signal line that normally sends the register number of the R2 field. For this purpose, the GNI field and v1 field of RGRr400 are transmitted together via line a439,
It is sent to the SG conversion circuit b401 and is also input to the selector 5400 as the first set. On the other hand, the GN2 and v2 fields of the register r400 are input to the selector 5400 as a second set, and one of them is selected and the SG conversion circuit b404. G-8
It is sent to the conversion circuit b402.

The selection control of this selector 5400 is performed by the decoder b438, and the selector 5400 is controlled so that the former or the latter is selected depending on whether the instruction code in the RIRr401 is for an instruction to store vector data in the main memory. . The GN3 and v3 fields of RGRr400 are directly connected to the S-G conversion circuit b405 by the line Q459.
It is sent to the G-8 conversion circuit b403.

In order to start writing to the vector register control circuits b410 to b417 and the vector register in the vector register data unit U41, RGR, r
400 R1-R3 fields are sent to decoder b430. The decoder b430 has a decode enable terminal (E) with an AND gate (A), and decoding is enabled when all input lines to the AND gate (A) are 1''.

The AND gate (A) of the decoder b430 contains the v1 field, the W1 field, and the flip-flop f4.
10 outputs are respectively wire Ω580°11581, ff1
419 is connected, and the GNI field is input via line Q439 as a signal to be decoded. The decoding is valid, that is, the data in the GNI field has meaning (Vl field = “1n”), writing is specified (Wl field; The contents of the input GNI field are decoded and this GNI field is decoded.
When the NI field has a number from vector register 0 to 7, 8 output lines f1410-J
417(7) One of them becomes 1′l”, here,
When the GNI field is “O”, the output line Q410 is 1
1", '1", the output line n411 is # l ##, "
2", the output line Q412 is decoded as "(1#j"). In the instruction considered as an example, the R1 field in RGR, r400 instructs writing to vector register 0 (W1 =1.GN1=O), so only wire polishing 410 becomes "1", decoding b4
30 output lines 8410-12417 are sent to vector register control circuits b410-b417 (FIG. 11) and vector register data unit U41. Decoders b433 to b435 are for starting reading of the vector register. These decoders have Wl to the decoder valid terminal with AND gate (A).

W2. W3 field instead of inversion gate g
The inverted output from 420 to g422 is the line Q589 to 591
input via RGR.

When field Ri of r400 is for reading (Wi=O
), the only difference is that decoding is enabled, and the rest is completely the same as decoder b430. decoder b
The outputs of 433-b435 are OR gates g440-g4
47, and are sent as read activation signals to vector register control circuits b410 to b417 and vector register data unit U41, respectively, via lines 2400 to 2407. In the above embodiment, the decoder b43
3 is omitted and the output of the selector 5400 is sent to the decoder b43.
4 may be input. At this time, the selector 540
0, the outputs of the W1 field and W2 field are also GNI.

It must be entered together with the GN2 field and must be selected.

The decoder b436 includes operand control circuits b420 to b
423. The line Q419 is input to the decode valid terminal E, and the resource type and number are input from R2H, r402 to the data terminal DI, and when these are decoded, one of the lines Q440 to Q443 becomes It I 11. This line Q440~Q44
The signal “1” of 3 is the operand control circuit b42.
This is the activation signal for 0 to b423.

Decoder b437 includes operand control circuits b420 to b
423 to indicate a case where it is not necessary to synchronize two vector elements. Cases where synchronization of two operands is not required include, for example, storing vector data from one vector register to main memory, transferring vector data between a pair of vector registers, or converting vector data in one vector register. Like converting vector data to store in one vector register to another,
There is only one vector register to read, and R3 of the instruction
This is a case where the field is not required, and in this case, RGR
, r400's v3 field is jJ OII. The decoder b437 has a decoding enable terminal E with a two-way gate (A), which has an RGR signal in addition to the line Q419.

The output obtained by inverting the output of field 3 of 400 by an inversion gate g423 is input. The decoder b437 is R
2H, decodes the resource type and number given from r402 and outputs "1" to one of the lines Q450 to Q453. The output of decoder b437 is the line Ω450~04
53 respectively to the operand control circuit b420-b.
423.

The resource type number in R2H, r402 is also the line Q42.
9 via the S-G conversion circuit b401. b404, b40
5. G-5 conversion circuit b402. It is commonly input to b403.

The processing vector length in RVLR, r403 is line Q469
Therefore, it is commonly input to each operand control circuit b420 to b423.

(tv) The SG conversion circuit in FIG. 13 supplies the data valid signal given from each resource in the SG conversion circuit b401 to the vector register control circuit for the register number specified by the instruction control unit U3. Shows the circuit.

In FIG. 13, a resource type number is inputted to the data terminal of a decoder b439 via a line Q429, a vector register number for writing is inputted via a line Ω439 to registers r410 to r413 provided corresponding to the resources,
The command activation signal ST is sent to the decoder b43 via the line Ω419.
It is input to the decoding enable terminal (E) of No.9. register r
410 to r413 are memory requester 0.1 and arithmetic unit 0.413, respectively. It is provided corresponding to l.

In addition to the register number GNI, the line Q439 also includes a signal V indicating whether the register number is valid, as described in the explanation of FIG. These signals are sent to the decoder b corresponding to the resource type and number on extension Q429 of register r410 = r413.
439. Registers r410 to r4
The register numbers GNI in 13 are respectively decoder b4.
The V bit is input to one input terminal of the decode enable terminal (E) with an AND gate (A) of the decoders b440 to b443. The other input terminals of these terminals E receive data valid signals from memory requesters 0 and 1 and arithmetic units 0 and 1, respectively, on lines Q46. Q46', Q29. For example, under the condition that the output +11 I+ of the V field in register r410 is input to the AND gate of decoder b440, when Ig 171 is input from line Q46, decoder b440 decodes The output of the ON field of the register r410 is decoded, and any of the output terminals 0 to 7 of the decoder becomes "1", and the output line Q420 of the OR gates g430 to g437 connected to each output terminal is activated. ~
One of Q427 becomes "1". This output line Q42
0 to Q427 correspond to vector registers O to 7, and supply data valid signals to vector register control circuits 0 to 7, respectively.

In this way, once the data is set in the registers r410" and r413, the line Q46 becomes "1".

A change of "0" is directly transmitted to any of the lines Q420 to Q427. What should be noted here is that as long as the register numbers in register r 410 = r 413 are different, line Q46. fi46'.

Q29. Q29' number at the same time each line Q420~
Q427 can be supplied to the corresponding line. This simultaneous supply is possible for up to four register numbers. In this way, it becomes possible to operate four resources in parallel.

It should be noted that the final vector data signals supplied from each resource in the SG conversion circuit b401 are sent to the instruction control units 1 to 401.
The circuit portion that supplies the register control circuits O to 7 for the register number designated by U3 is indicated by line Q46. in FIG. f146'.

Q29. Q29' as line 144. Q44'.

Q26. Q2G'L:, replace with more, line Q42o~Q4
It can be obtained by replacing 27 with lines Q430 to Q437.

The SG conversion circuit b404 transfers the vector data sending signals input from the operand control circuits 0 to 3 corresponding to each resource via the lines f1520Q523 to the vector registers having the register numbers specified by the instruction control unit U3 through lines Q540 to The circuit part that sends out via either Q543 and the line a5 from the operand control circuits O to 3.
10 to f1513 to vector register control circuits 0 to 7 for the resource number specified by instruction control unit U3 via lines Ω530 to Q537. In the former case, line Q439 is connected to line Ω44 in FIG.
9, line Q46. Q46' and Ω29' are respectively replaced by the line Ω520-fi523, and the line fi
420 to Q427 by lines Q540 to Q547, respectively. The latter is similarly connected to the line Ω459. in FIG. Obtained by using lines Q510-Q513 and 12530-Q537. S
The -G conversion circuit b405 is also formed in the same manner as the single circuit b404, so the details will be omitted.The signal line numbers after these replacements are indicated by signal line numbers 046. Q4
6', Q29, Q29', and are shown in parentheses after f1420-Q427.

(v) G-8 conversion circuit FIG. 14 shows details of the a-S conversion circuit b402 (FIG. 11). The type and number of the resource are input from the umbrella start control circuit b400 via the line Q429, the register number is input via the line j1449, and the line Q
A set signal via 419 is input. Line Q429
The type and number of the above resource are set to the one corresponding to the register number on the line 2449 among the registers r420 to r427 corresponding to the vector registers. To specify the register to be set, the register number on IIAQ449 is input to the data terminal, and the set signal on line C419 is input.
It is controlled by a decoder b449 which inputs a signal V indicating the validity of the register number on 1Q449 to an AND gate (A) of the decoder b449. Registers r420 to r4
The outputs of 27 are sent to corresponding decoders b450~
b457 is input. decoder b450-b45
7 is a decoding enable terminal (
The vector register successive permission signal input to E) is “1”.
”, then # from any one of the output terminals corresponding to the resource type 1 number input from the data Kugata terminal.
#, outputs 1jl. As a result, decoders b450~
Any of the OR gates g440 to g443 connected to the output terminals numbered 0 to 3 of b457, line Q
The line corresponding to the specified resource among 490-f1493 is ``'1'' tonal, and any of the lines Q480-Q487 is (
10", the corresponding decoders b450 to b457 are no longer valid for decoding, so the ga480
~Q487 “1” and “O” correspond to signal line Q490
- It will be transmitted to Q498 as 1", "O".

Note that once the resource number types set in the registers r420" and r427 are different, the 1" signals on the lines Q480 to Q487 are connected to the respective lines Ω490-
Corresponding lines within Q493 can be fed simultaneously, and this simultaneous feeding can be done for up to four resources. This allows parallel operation of four resources.

Note that the G-8 conversion circuit b403 in FIG. 11 replaces the signal line Q449 in FIG. 14 with a line 12459, and the line Q4
It can be obtained by replacing 90 to Q497 with lines a500 to Q507, respectively. In addition, in FIG. 14, the signal numbers after this replacement are shown in parentheses after the number of the signal line to be replaced.

(vi) Vector register control circuit FIG. 15 shows details of the vector register control circuit b410. Other vector register control circuit 1
. . . . . . . . . . . . . . . . . . . C41
0, fi420° C430, C460, n480 can be obtained by replacing these signal line numbers with the number lines written in parentheses. This control circuit performs three operations: a write or read only operation and a chaining operation (simultaneous write and read operations).

(a) Write-only operation When an instruction to start writing to the vector register O is transmitted via the line Q410 by the instruction start control circuit b400 (FIG. 14), the flip-flop f4 indicates that writing is in progress.
20 is set.

Up/down counter (hereinafter referred to as U/D counter) C40
0 is cleared. The U/D counter C400 has U, D
Provides the following output for the input of the terminal.

Input Output U D
(Contents of the counter) OO unchanged 0 1 -1 changed 1 o +1 changed 1 1 When a data valid signal is input from the SG conversion circuit b401 via the unchanged line Q420, this signal is sent to the flip-flop Through the AND gate g420 which is opened by the output n 1 n of f420.

The signal is input to the U terminal of the U/D counter C400, increments the contents of the counter by 1, and is sent as is to the vector register data unit U41 (FIG. 10). S-
When the final vector data signal is sent from the G conversion circuits b401 to C430, this signal resets the flip-flop f420, stops the writing state, and sends the instruction control unit U via the direct line Q430.
3 (Figure 1), and the write vector register number (for example, j
) is reset. Note that the line Q15 in FIG. 1 is obtained by bundling the line f1430 with the corresponding output lines Q431 to Q437 of the other vector register control circuits 1 to 7.

(b) Read-only operation When the write operation of the vector register O is not activated and a read activation instruction for this vector register is transmitted via the instruction activation control circuit b400 (FIG. 11) stranded wire M400, Flip-flop f421 indicating that reading is in progress is set. Since flip-flop f420 is in a reset state, its output is passed to inverting gate g451. It is input via the OR gate g452, and the output of the flip-flop f421 is also input. The output line U480 of the AND gate g453 becomes "1". Line Q
480 is a readable signal, and the G-3 conversion circuit b40
2 (Figure 11). Therefore, as explained with respect to instruction control unit U3, when a vector register is used for reading in a certain instruction as explained with respect to U3 in a certain instruction, a read-behind instruction that uses this vector register for writing is It will not be activated until this reading is completed. Therefore, since flip-flop f420 is not set until this reading is completed, the read enable signal continues to be sent to line Q480 until flip-flop f421 is reset. In this way, when reading of all elements of the vector register O is completed, the final vector data signal is inputted from the SG conversion circuit b404 via the line Q460, and this signal causes the flip-flop f42 to
1 is reset.

Note that the line Q460 is connected to another vector register control circuit b.
Corresponding signal lines Q461 to Ω46 in 411 to b417
7, as line 1216, RGSW in command control unit U3.

r306 (FIG. 3) and is used to signal the completion of reading vector register O and to reset bit RO of this register to zero.

(c) Chaining operation A chaining operation occurs when a write operation is first instructed to a certain vector register for a certain instruction, and then a read operation is instructed for another instruction before that operation is completed. arise.

Even if a write operation is instructed, unless a data valid signal and write data arrive from the resource, writing to the vector register will not actually be performed. It doesn't matter what the relationship is.

(c −1) For example, after a write operation is commanded by line Q410, flip-flop f420 is set, and U/D counter C400 is reset, and before the arrival of the data valid signal from line 2420, a read operation is :':: Q 4
Directed by 00.

When the flip-flop 5421 is set, a positive detection circuit b46 detects that the content of the counter connected to the output of the U/D counter C400 is 1 or more.
The output of 0 is IIOl#, and the output of the inverting gate g451 is also "0", so the output line Q of the AND gate g453
480 also remains "O". Here, when a data valid signal comes to line Ω420 in a certain machine cycle n,
Via AND gate g450, U/D counter C400
This signal enters, and in this machine cycle n,
The content of the U/D counter C400 becomes +1. Then,
The output of the positive detection circuit b460 becomes "1", and a vector register read enable signal is output to the line a480 via the OR gate g452 and the AND gate g453. Line Q4
80 is connected to the D terminal of the U/D counter C400, and when the next data valid signal does not come in from the line Q420 in the machine cycle (n+1), the value of the counter C400 is 0 after the machine cycle (n+1).
Return to Therefore, the read enable signal will be output to Q480 only once.

Even after that, if the data valid signal is input intermittently, the read enable signal 0480 is output each time.

On the other hand, if the data valid signal is continuously input after machine cycle (n+1), "l" is input to the U and D terminals, so the value of counter C400 remains 1" without changing, and the line "1" is subsequently output to Q480. (c-2) A write operation is instructed by line Ω410, flip-flop f420 is set, and after U/D counter C400 is reset, data becomes valid. Each time a signal arrives over multiple machine cycles, the U/D counter C400
Assume that the flip-flop f421 is set by read activation in machine cycle n while the value is being counted up and displaying a non-zero value. U/
Since the output of the positive detection circuit b460 connected to the output of the D counter C400 is 111 ##, the vector register read enable signal is output to the line Q480.

Since line 11480 is input to the D terminal of U/D counter C400,! If the data valid signal from f1420 is not input in the next machine cycle (n+1), it is set to -1, and if it is input, the value remains unchanged.

The above operation is repeated until the content of the U/D counter c400 becomes O. The number of read enable signals output on line Q480 during a machine cycle after read activation is equal to U before flip-flop f421 is set.
This is the sum of the contents of the /D counter c400 and the number of data valid signals subsequently input from the green Q420. In this way, in either case (c-1) or (c-2), it is guaranteed that the number of vector elements written in the vector register will not be read out. In addition,
The contents of the U/D counter c400 can be considered to represent the difference between the number of vector elements written into the vector register and the number of vector elements read from the vector register.

When writing is completed during the chaining operation and the flip-flop f420 is reset, the contents of the U/D counter have no meaning and become equivalent to the read-only operation in (b).

(vii) Operand control circuit FIG. 16 shows details of the operand control circuit Q, b420. The configurations of the other operand control circuits 1 to 3 are the same, and the signal line numbers in this figure can be changed to the signal line numbers shown in parentheses afterward.

When the command start control circuit b400 outputs a start signal via the line a440, the selector 5410 selects the line 1469.
The above processing vector length (VL) (assumed to be greater than or equal to 1) is selected and the vector length counter (VLCTR)
Set to c403. Also, this activation signal causes U
/D counter c401. The contents of c402 are cleared. Furthermore, flip-flop f431 is set,
It is stored that the processing of this operand control circuit O has become valid. If an instruction that requires memory requester 0 corresponding to operand control circuit 0 only requires reading one vector register (assuming here that the R3 field of the instruction does not specify a vector register read), then The instruction signal is the command activation control circuit b40
0 via line fi450 to set flip-flop f430.

Here, first, instructions R2 and R3 that require arithmetic unit O
A case will be explained in which both the field and the vector register are designated to be read. In this case, flip-flop f430 is II OPI. Line Q490. Q
500 are G-8 conversion circuits b402. This signal line inputs a vector register read permission signal from b403 to the U terminals of counters c401 and c402, respectively, and there are various ways in which this signal can be input.

Operations are performed in accordance with these cases for each machine cycle. Here, the counters c401+c402 are the same as the counters c400 (FIG. 15), and the positive detection circuits b461. b462 is a positive detection circuit b460 (15th
This is the same as in Figure).

(a) Case where both are not input This case further includes the following four cases.

(a-1) U/D counter c401. c40
(a-2) When only U/D counter c401 is positive; (a-3) When only U/D counter c402 is positive; (a-4) When U/D counter c401. c40
When both of 2 are positive, cases (a-1) to (a-3) In these cases, AND gates g461 to g464
None of the outputs becomes 11111, and no output is produced.

Case (a-4) In this case, the line Q490. Occurs after the vector register read enable signal is sent via Q500. At this time, the outputs of the positive detection circuits b481 and b462 become "1", and the former is directly connected to the OR gate g460.
is input to AND gate g464. The output 111 IT of this AND gate g464 is OR gate g4
65 and is input to AND gate g466. The output “1” of the flip-flop f431 is input to the AND gate g466. Also, and gate g46
6 @1630. fi631 is input, which will be described later. Here, it is assumed that both are "1". A vector data sending signal is output to the output line Q520 of AND gate g466. Output line n520 is U
/D is input to the D terminal of counters C401 and C402,
The contents of the counter are decremented by one.

Further, the output line 1520 is VLCTR.

It is input as a set signal to c403 and decrements the value of the counter by 1. That is, the output of VLCTR,c403 is connected to the 11 subtraction circuit b463, and the value obtained by -1 is input to the selector 5410. At this time, since the command activation signal is no longer coming to the control terminal of the selector 5410 via the line Q440, the output of the 11 subtraction circuit b463 is selected and set to V L CTR,c 403. This next circuit operation is performed by U/D counter c4Q1.
．． Depending on the content of c402, 1ifi490. f
This differs depending on the input status of the vector register read enable signal from 1500.

Note that when the vector data sending signal is output to the line Q520, the 1 detection circuit b464 detects VLCTR, c4.
When it is detected that the original content of 01 before being subtracted by 1 is 11'', that signal is ANDed with the vector data sending signal at AND gate g467, and then sent to line Ω510 as the final vector data signal. Also,
The signal on line f1510 causes flip-flops f431. Reset f430.

(b) Case where only line 2490 is input or (c)
Since the operation is the same in all cases where only the line Ω500 is input, case (b) will be explained here. In this case, there are two further cases:

(b-1) When U/D counter c402 is 0'', (b-2) U/D callan'l c 402
When xi positive t+ (7), case (b-1) At this time, the output of the positive detection circuit b462 is "O", so the output of none of the AND gates g461 to g464 becomes It 11j, and therefore or gate g465
The output of AND gate g466 is also 0", and the D terminal input of U/D counter c401 tc402 is t# O.
It remains IT. Vector data sending signal is on line Q52
It is not output to 0. Since the vector register read permission signal is input from the line Q490 to the U terminal of the U/D counter c401, the U/D counter c401 is +1.
be done.

Case (b-2) At this time, the output of the positive detection circuit b462 is "1", so the output of the AND gate g462 is "1",
A vector data sending signal is sent to line n 520 L= via OR gate g465 and AND gate g466.

VLCTRc403, flip-flop f430. f4
Since the operations such as resetting 31 are the same as in case (a-4), they will be omitted here. Since the line Q520 becomes "1", the U/D counter c401. Both D terminals of c402 become "1". Since "1" is input to the U terminal of the U/D counter c401, the contents of the counter do not change. The U terminal of the U/D counter c402 has “O
Since It has been input, the contents of the counter are incremented by -1.

(d) Line Q490. A case in which both Q500 are input at the same time This case can be further divided into the following four cases.

(d-1) U/D counter c401. (d-2) When only the U/D counter C401 is positive.

(d-3) When only the U/D counter c402 is positive.

(d-4) U/D counter c401. When both c402 are positive, case (d-1) In this case, the line Q490. The vector register read permission signal on Q500 causes the output signal of AND gate g461 to become "1", and as a result, a vector data sending signal is output to line Q520. U/D counter c40
1. The U terminal of c402 is “1” and the D terminal is also connected to the line Q5.
Since 1'1 #1 on 20 is input, the contents of the counter remain unchanged.The operations such as control of 1°VLCTR and c403 are the same as those described in case (a-4).

Cases (a-2) and (d-3) Since the operations in both cases are similar, the case (d-2) will be described.

In case (d-2), only the U/D counter C401 has a positive content, so the output of the positive detector b461 is “1”.
Then, the outputs of AND gates g461 and g463 become It 11j. Therefore, a vector data sending signal is sent to line Q520 via OR gate g465w and gate g466. VLCTR,c4
Since the control in case 03 and the like is the same as in case (a-4), the explanation will be omitted. U/D counter c401. The contents of c402 do not change because the operation is the same as in case (d-1).

Case (d-4) In this case, the U/D counter c 401 +c40
Since the content of 2 is positive, the positive detection circuit b461. b46
The output of 2 becomes 111", and the AND gate g461~g
All outputs of 464 become "1". The following behavior is (
Similar to case d-2), a vector data sending signal is sent on line Q520. U/D counter c401゜c
The contents of 402 similarly do not change.

As can be seen from the above explanation of the operation, the U/D counter c
401. c402 plays the role of synchronizing the sending of two operands (vector data). When only one of the vector register read permission signals comes, it is stored in the counter and the counter is incremented by 1). When it is taken out, the counter is incremented by -1. 1. When the vector register read permission signals arrive at the same time, the contents of the counter do not change.

Next, a case where only one operand is used will be explained. In this case, when the operand control circuit is activated, flip-flop f430 is set to indicate that only one of the operands is used. This output is input to the other input terminal of the OR gate g460 connected to the output of the positive detection circuit b462, and the output of the OR gate g460 is set to "1" regardless of the contents of the U/D counter c402. In this way, the vector data sending signal is generated as before only by the vector register read permission signal inputted from line Q490.

Note that the line Q630 shown in FIG. 16 is a signal for permitting transmission of the vector data transmission signal, and is used as necessary. (This is not particularly necessary in the present invention.) This is useful, for example, when it is desired to send vector data (therefore, a data valid signal) to the arithmetic unit at a certain interval or more (for example, when the arithmetic unit receives data continuously). used when this is not possible). In this case, this enable signal should be created within the operand control circuit. For example, the output of a flip-flop that is reset by a data valid signal and set after a certain period of time from the data valid signal becomes this permission signal. It is also used when temporarily stopping vector data sent to a memory requester (when storing data in the main memory again). In this case.

This permission signal is sent to the main memory control unit Ul (see Figure 5).
, or created by the memory requester. fi12
At 630, when vector data transmission is not permitted, the line Q
490. The vector register read permission signal input from Q500 is U/D counter c40! , c402 and the counter is updated. When the permission signal is input from af1630, 1iAQ490. Even if there is no signal input from Q500, U/D counter c401. c401
Since the content of is positive, the output of AND gate g464 becomes 1", and a vector data sending signal is sent to line a520. At the same time, U/D counter c401
．． c402 is set to -1.

Further, the timing control circuit b465 is a circuit that controls the sending timing of the vector data sending signal. 18th
As detailed in the explanation of the figure, each vector register is configured with two memory elements in order to read and write to the vector register when the number of times it appears exceeds the limit, and read and write to each memory element alternately. . That is, when writing to one memory element, the other memory element is controlled to read, and vice versa in the next cycle. Therefore, since it is not possible to simultaneously read from a memory element that is being written to, it is necessary to make the reading wait in that cycle and control the reading in the next cycle. For this purpose, control is performed so that the transmission of the vector data transmission signal is temporarily stopped. The timing control circuit b4 corresponds to this role.
In step 65, it is determined that the vector data transmission signal should not be transmitted in the first cycle.

Timing control circuit b465 connects output line Q631 to II
The output of Antogame 1''g 466 is suppressed as OII.

Specifically, the timing control circuit b465.

It works like this: That is, when a vector data sending signal is input in a certain machine cycle, 11'' is output in the next machine cycle, the second cycle, the fourth cycle, and so on.

1st cycle, 3rd cycle... For the next machine cycle, apply II O11 :J'J. This timing is shown in FIG. When R time is input without sending vector data continuously, 7! The machine cycle of A is # I I
Since I is output, the timing control circuit b465
Note that 111 II is output continuously from .

In this embodiment, the operand control circuit is described as inputting the read enable signals of two vector registers, but when the read enable signals of three or more registers are input, Creating a transmission signal can be similarly easily realized.

In FIG. 18, each of the eight vector registers in the vector register circuits b470 to b477 has a large capacity, so each vector register has a large capacity. Consists of elements.

A memory element is given five addresses to write data to or read data from that location, but it is not possible to read and write to different addresses at the same time. In order to realize the chaining operation, it is necessary to write a certain vector element and read other vector data at the same time, so in this embodiment, two memory elements m4'oo and m401 are used for one vector register. - form vector registers, and read and write to them alternately. This allows simultaneous reading and writing to different addresses.

The numbering of vector elements is as follows:
It is assumed that odd-numbered vector elements are arranged so that they become the same memory element.

The details of the operation are explained below. Writing and reading from vector register O will be explained here.
The same applies to operations on other vector registers.

When an instruction is activated, the vector register control unit U
From the instruction start control circuit b400 (FIG. 12) in 40, the SG conversion circuit b480. G-3 conversion circuit b481.
The resource type and number are sent to b482 via line ρ429,
The write vector register number is sent via line Q439, and the read vector register number (both numbers since there are two operands) is sent via line 1449. The above set signal is sent via line Q419 via Q459, and the S-G
Conversion circuit b480. G-8 conversion circuit b481°b482
is set inside. SG/SG conversion circuit b480.
b481. b482 is Fig. 13.

This is the same as that explained with reference to FIG.

Writing to vector register 0 operates as follows. First, a signal instructing to start writing to vector register 0 is sent to instruction activation control circuit b400 via line Q410.
It is sent from. This signal clears the write address counter c411 to 0. The output of the write address counter c411 is sent to the selectors 5420 and 5421.
is input. The other inputs of the selectors 5420 and 5421 are the outputs of the read address counter c410, and the output of the timing control circuit b482 and the output obtained by inverting the same with the inverting gate g480 are input to the control terminals of these selectors, respectively. Timing control circuit b482
is configured so that a trigger type flip-flop (not shown) receives a clock issued every machine cycle, and it is turned on every machine cycle.
Therefore, when the timing control circuit b482 selects the output of the read address counter c410 with the selector 5420, the timing control circuit b482 selects the output of the write address counter C411 with the selector 5421. However, in the next machine cycle, control is performed to select the opposite.Selector 5420
The output of selector 5421 is given as the address of memory element m400, and the output of selector 5421 is given as the address of memory element m401. Now, lines Q45°Q45', Q29 . Q2
9', the write data is sent to the SG conversion circuit b480.
, this data is input from the resource specified by line Q429 to one of vector register circuits b470-b477 corresponding to the vector register specified by line f1439. Here, vector register O
Since the data is written to , it is input to circuit b470.

The write data is sent to the registers VRIRE, r430°VRIRO, and r440 provided at the entrance of the circuit b470.
They are set alternately according to instructions from the RIR input control circuit b484.

The data valid signal 1 is input to the VRIR input control circuit b484.
1420 is input, and VRI RE is input for each even and odd data valid signal.

r430. Control is performed to set data in VRIRO and r440, respectively. Memory element m 400 in which there are two cycles for writing.

m401 (details will be described later), and may be forced to wait for any vector in any cycle.
At this time, the next write data may arrive at the same vector register circuit b470, so two registers VRIRE and VRIRO are provided to transfer two successive write data to different memory elements m400. Enabled to write to m401. A write instruction is given by a data valid signal input from vector register control circuit 0 (FIG. 14) via line Q420. This signal is input to the write timing control circuit b483.

The circuit b483 outputs two signals held for two machine cycles according to the even/odd write instructions at the timing shown in FIG. 19, and these outputs are respectively input to the AND gate g481. g482. On the other hand, the output of the timing control circuit b482 and the output obtained by inverting it by the inverting gate g480 are input to these AND gates, and the outputs become write enable signals for the memory elements m400 and m401, respectively. The write address counter c411 is +1 times circuit 4 so as to point to the next address.
+1 after 81. This control is and gate g48
1. This is performed by ORing the output of g482 with OR gate g48. Note that writing is performed in memory element m400.
．． Since data is written alternately to memory element m400. It would be sufficient to add +1 after writing to both of m401, but here, the value ignoring the lower 1 bit of the write address counter is set as the write address, and the selector 5420, 5421
input. This is the read address counter c41
The same applies to 0. As described above, the vector elements are memory elements m400. They are written alternately to m401.

A time chart of the above operation is shown in FIG. 19.

Reading from vector register O operates as follows. First, a signal instructing the start of reading from vector register O is sent to instruction activation control circuit b via line Q400.
It is sent from 400.

This signal clears the read address counter C410. At first, the read address counter C410
is cleared to 0, so selectors 5420 and 54
21, the address is the memory element m400. m401
is given to selector 5, the data at address 0 is read out, and the data at address 0 is read out.
422. The output of the timing control circuit b482 is connected to the control terminal of the selector 5422 through an inverting gate g4.
The inverted output is inputted at 80, and it is instructed which memory element to select the data read from, and the memory m
Control is performed so that the output of memory m400 is alternately selected in the readout cycle 400, and the output of memory m401 is selected in the next cycle. The data selected by this is once set in the register (VROR) r450, and then in the G-8 conversion circuit b481. b482, it is converted into data corresponding to the resource. For example, if it is data of an operand to arithmetic unit 0, it is converted to data corresponding to the resource by line Q41.
sent to. Since only one data is required for the memory requester (data stored in the main memory), only one G-5 conversion circuit is required.
Just use one. Here, in circuit b481, G-8
I am trying to do the conversion. 1 of vector data
When the vector element is sent out, the vector register control unit U40 sends out an update signal for the vector register read address counter C410 via the line Q470. As a result, the read address counter c
410 is updated one by one. Update is done by counter C410
The output of +1 is passed through the adder circuit b480 to the counter c410.
This is done by returning to the input of

As mentioned above, the vector register unit reads the vector data supplied to the resource and stores the vector data sent from the resource. Since this is necessary, the two vector data must be aligned before being sent. Moreover, for vector elements on any two vector registers stored at unequal intervals in each vector register by chaining operation,
It is necessary to read the data after confirming that both data are complete. For this purpose, each of the vector registers has a circuit for detecting whether reading is possible or not, and two circuits corresponding to the resources.
The data is read from the vector register only when it is readable. (In reality, the data has already been read, and the read address counter is updated for the next read.) do)
.

■ Memory requester The details of the circuit of memory requester 0 are shown in FIG.

The operations of the memory requester are divided into three: initialization operation at the time of instruction activation, read operation from main memory, and storage operation to main memory.

(1) Initialization operation at the time of command startup In FIG.
An instruction activation signal is sent via line Q13, a resource type and number are sent via line Q11, and an instruction code is sent via line Q11.
The register number is sent via line ρ12, and the processing vector length is sent via fiu14. The resource type and number on the line Q13 are decoded by the decoder bloo, and if the self memory requester is designated, 1''' is output from the decoder bLOo, and the AND It is input to the gate gloo, and u 1 n is output to its output line R100.mQ
100 is input to the flip-flop floO to set the flip-flop, and the register MIR,r
It is input to the set terminals of loo, MGR, rlol,
MIR the instruction code and register number, respectively.
Set it to MGR. Also, 1lQloo is selector 5
It is input to the control terminal of LO3, selects the processing vector length on IIρ14, and controls the processing vector length counter (M V
L CTR), set the processing vector length to cloo.

Also connect the wire Q10 to the set terminal of MVLCTR,c 100.
0 is connected. This completes the initialization operation.

(n) Read operation from main memory A read operation from main memory means that the output of MIR, rlooo, where the instruction code is set, is sent to decoder b1.
This can be known by decoding with 01. decoder b10
The output line Q20 of No. 1 is sent to the main memory control unit Ul (see FIG. 1), which specifies read or store operations, and selectors 5104, 5105, 5106, and
07 control terminal, and each selector's J(
Select the side marked FII. Note that if storage in main memory is specified by MIR, rlooo,
Select the side of the selector marked 'S'.

The outputs of vector address register U5 and vector address increment register U6 (see FIG. 1) are respectively connected to lines Q18. selector s10 respectively via line Q19
0.5101, and the vector address register U5.0 is specified by the output of MGR, rlol to which the register number is set. and the contents of the vector address increment register U6 are selected, and the vector address is selected in the selector (WVAR) rl 10 and the working vector address increment register (WVAIR) rll
It is set to l. Setting to both registers is controlled by the output MI2101 of the flip-flop f100. The line Qlo1 is also connected to the control terminal of the selector 5102, and controls the output of the selector 5100 to be selected. When the vector address is set to WVAR,rllo, the line f121 causes the main memory control unit U
1 (FIG. 1), the first vector element address is sent. At the same time, from the non-zero detection circuit b104 connected to the output of 1MVLCTR,c100 (1MVLCTR,c100
Assuming that the above is set in MVLCTR)
l#lFj is output, passes through selector 5107, and is connected to line Q.
23, the address is sent to the main memory control unit U1 as an address valid signal.

Line Q23 is also input to the control terminal of MVLCTR,cloo to set the contents of MVLCTR,cloo(7) to -1
do. The value subtracted by 1 was connected to the output of MVLCTR, cloo. It is created by the 1 subtraction circuit b103, and is input to MVLCTR, rloo through the selector 5103. Furthermore, line Q23 is WVAR,rllo(7)
Control terminal D is also input, WVAR, rl 10, and WV
AIR.

The result of adding the contents of rllll by adder b102 is sent to WVAR again via selector 5102.

control to set it to rllo. This results in 1
The next vector element address is WVAR.

This means that it is set to rllo. By repeating this one after another, the vector address is determined and sent along with the address valid signal (@(123)) to the main memory control unit U1 via the line Q21, and the read operation of the main memory is not performed.

When the read operation in the main memory is completed, the read data is transferred from the main memory control unit U1 to the line Q25 via the line Ω24.
A data valid signal is returned via. Read data on line 1224 is input to data register DR, r120 via selector 5105, and line Q25 is input to selector 51.
After 04.

The reading ratio data is input to the set terminal of DR, r120 and is set to DR, r120, and its output is sent to the line Q2.
9, the vector register data unit U41 (
Figure 10). Also.

The data valid signal on line Q25 is connected to a flip-flop, f1.
02 and sent via line 1230 to vector register control unit U40.

MVLCTR,c 100 is subtracted, and the contents become “
When it becomes 1'', it is determined by the 1 detection circuit b105.

It is detected that it is the final vector element, and the final vector data signal is sent to the main memory control unit U1 along with the vector address (line Q21) and address valid signal (line Ω23) via line L32, and via line 133,
Returned synchronously with read data. The final vector data signal on line Q33 is once set by flip-flop f103, passes through selector 5106, and is sent to vector register control unit U4 (FIG. 10) via line Q26.
sent to. When the contents of MVLCTR,cloo become 110" after passing through the 1 subtraction circuit b103, the non-zero detection circuit b
104 outputs II OIf, and the sending of the address valid signal is stopped. This completes the vector data read operation.

(■) Storage operation of vector data In storing vector data, first, a signal designating storage is sent to the main memory control unit U1 via the line Q20. This signal is created by decoding the contents of MIR, rloO by the decoder b101. Sending out the main memory address of the data to be stored is exactly the same as the read operation. That is, a designated one of the vector address register and the vector address increment register is selected by selectors 5loo and 5lo1, respectively, WVAR, r 110 .

WVAIR, set to r120. WVAR.

The output line 121 of rllo connects the main memory control unit U1.
The fact that a vector address is sent to is also similar to the read operation.

The data to be stored is transferred by line Q27 to vector register unit U4 along with the data valid signal (on line Q28).
It is sent from Vector data is selector 5105
DR,r is set to 120. DR, r1
The setting to DR, r120 is controlled by inputting the data valid signal on line Q2B via selector 5105 to the set terminal of DR, r120. The data valid signal on line Ω28 is also present. It is also input to the flip-flop, flol, and once set, its output is sent to the selector 5107.
DR via line Q23.

It is sent to the main memory control unit U1 together with the vector data to be stored on r120. As a result, the main memory control unit performs a write operation to the main memory. line 1
The address valid signal on 23 is.

Input to the set terminal of WVAR, rllo.

WVAR, rl 10 is used to update the address in the same manner as the read operation. Each time the data to be stored and the data valid signal are sent from the spectrum register unit, the address is At the same time, WVAR and rllo are updated to prepare for storing the primary vector data. This is repeated as long as data is sent from the vector register unit.

Note that in the storage operation, MVLCTR.

cloo operates similarly to the read operation, but has no meaning. Even though the final vector data signal is sent to the main memory control unit on line Q32, it is ignored during store operations.

(2) Arithmetic unit FIG. 21 shows an outline of the arithmetic unit 0. Arithmetic unit 1 also has the same structure. In this embodiment, as already known, the arithmetic circuits b210 to b213 perform partial arithmetic operations on inputs to each arithmetic circuits b201 to b204.
It is carried out under the control of Here, it is assumed that the pipeline operation is executed in four stages, but there is no particular limit to the number of stages, and there is no limit to the number of stages.
It is assumed that ゜1 is capable of performing various operations specified by instructions. In this embodiment, when vector data and its data valid signal are input as input operands,
The resulting vector data calculated by the pipeline stage and the data valid signal are output in synchronization, and when the final vector data signal is input, this signal is also output in synchronization with the data valid signal. is a feature.

An outline of the operation will be explained below.

An instruction activation signal is input from the instruction control unit U3 to the AND gate g200 via the line Q10, and the resource type 1 number is input to the decoder b200 via the line 813.
, 1ifill, the instruction code is transferred to register r200.
is input. The output of the decoder b200 becomes "1" when the input to it is for the self-operating unit, and is passed through the AND gate g200 to the registers AIR and r2.
Instructs 00 to set the instruction code on 1lfllll.

The output of #IR, r200 is the arithmetic control circuit b201 to b
204 and is input to the arithmetic circuit b2 in each stage.
10 to b213.

On the other hand, the vector data to be calculated is transmitted from the vector register unit to the line Q41. When a data valid signal is sent out through line Q43 by Q42, vector data is set in registers r210 to r220, and the data valid signal is set in flip-flop f200. The data valid signal (Q43) is the register r210. It is also used as a set signal to r220. register r210. r22
The contents on the register r211. An intermediate result is set in r221. The output of flip-flop f200 is used to set the register, and this output is also transmitted to flip-flop f210. Similarly, register r21
1. The output of r212 is input to the arithmetic circuit b211 to perform arithmetic operations, and in the next cycle, the output is input to the register r212.
An intermediate result is set in r222. In sync with this,
The output of the flip-flop f201 is the flip-flop f
202. Hereafter, by repeating this, arithmetic circuit b
212, register r213, and arithmetic circuit b213, the arithmetic operation progresses and the final result is set in register r214. The data valid signal is also transferred from flip-flop f202 to flip-flop f203 and then to flip-flop f204. The calculation result and a data valid signal indicating that the data is valid are returned to the vector register unit by lines 45 and ff46, respectively.

The data to be calculated is from register r210*r220,
Register r211. Once transferred to r221, the next data to be operated on is transferred to register r210. Setting r220 is the same as in a general pipeline arithmetic unit.

When the final vector data signal is input to flip-flop f210 by line 140, it is set in flip-flop f210 in the same manner as it is set in register. The data valid signal is applied to the flip-flops f200 to f.
204, the final vector data signal moves through flip-flops f210-f214 and is output on line Ω44 and returned to vector register unit U4.

As described above, in the arithmetic unit of the present invention, vector data and a data valid signal are input synchronously, the data is operated in synchronization with the movement of the data valid signal through the pipeline stage, and the result is Its feature is that it is output in synchronization with the valid signal. The same applies to the final vector data signal.

(5) Summary As explained above, according to the present invention, the execution order of instructions can be changed and started without logical contradiction, depending on the availability of the arithmetic unit or memory requester. It is possible to make effective use of memory requesters.

[Brief explanation of drawings]

1 is a schematic configuration diagram of a vector processor according to the present invention; FIG. 2 is a diagram showing the structure of various registers used in the present invention; FIG. 3 is a diagram showing details of the instruction control unit; Figure 5 shows details of the instruction queue register.
Figure 6 shows details of the resource usage check circuit.
Figure (a) shows the details of the register usage check circuit, (b) shows the check conditions, Figure 7 shows the details of the register conflict check circuit, and Figure 8 shows the instruction control unit. 9 is a detailed block diagram of the selector (b 394) in FIG. 8, FIG. 10 is a diagram showing the configuration of the vector register unit, and FIG. 11 is a diagram showing the configuration of the vector register control unit. Detailed diagrams: FIG. 12 is a diagram showing details of the instruction activation control circuit; FIG. 13 is a diagram showing details of the SG conversion circuit; FIG. 14 is a diagram showing details of the G-8 conversion circuit; FIG. 15 is a diagram showing details of the vector register control circuit, FIG. 16 is a diagram showing details of the operand control circuit, FIG. 17 is a time chart of the operation of the timing control circuit of FIG. 16, and FIG. The figure shows the details of the vector register data unit.
20 is a diagram showing details of the memory requester, and FIG. 21 is a diagram showing details of the arithmetic unit. 'i! Figure 54 2nd reason (see i) λ-ton Nl 慕;

Claims (1)

[Claims] 1. A plurality of program-specifiable registers that hold data, a plurality of resources that receive data from or supply data to the plurality of registers, and sequentially decode instructions. a decoding means for detecting registers and resources required by the instruction; an instruction storage means for holding a plurality of instructions decoded by the decoding means; means for detecting one instruction; means for instructing the start of execution of the detected executable instruction; and means for reading data from a register specified by the instruction in response to the instruction for starting execution; and an instruction execution means for sending data to a resource specified by the instruction or from a resource specified by the instruction to a register specified by the instruction, and the detection means is configured to detect that the resources and registers required by the instruction are available. means for detecting as an executable instruction an instruction that satisfies both the condition that the instruction is stored in the instruction storage means and that there is no register conflict between the instruction and the instruction that is decoded before the instruction. A data processing device, wherein the execution start instructing means instructs to start execution of the executable instruction before the previously decoded instruction. 2. When the execution start instructing means detects that a plurality of instructions are executable among the instructions held in the instruction holding means, the execution start instruction means selects the oldest decoded instruction among the plurality of executable instructions. 2. The data processing device according to claim 1, wherein the data processing device is means for instructing the start of execution of a command before other commands. 3. The detecting means detects the executable possibility of the oldest decoded instruction and at least one other instruction among the instructions held in the instruction holding means.
Item 2: A data processing device comprising first and second detection means. 4. The data processing device according to item 3, wherein the second detection means is means for detecting the executable possibility of the most recently decoded instruction among the instructions held in the instruction holding means. 5. The data processing device according to item 3, wherein the second detection means is means for detecting the possibility of executing an instruction other than the most recently decoded instruction. 6. The detecting means includes a first state indicating means for indicating the usage status of each resource, a second status indicating means for indicating the usage status of each register, and the first and second status indicating means. 2. The data processing device according to claim 1, comprising means for holding an instruction and means for determining whether or not the instruction is executable based on the resources and register numbers required by the held instruction. 7. The execution start instructing means has means for controlling the first and second state instructing means so as to change the state of use of resources and registers required by the instruction to which the execution start is directed at the time of the execution start instruction. , the instruction execution means controls the first state indication means in synchronization with the end of register reading or register writing for the instruction for which execution has been instructed, and in synchronization with the end of resource operation for the instruction. 7. The data processing device according to claim 6, further comprising means for controlling said second state indicating means. 8. The detection means detects whether one instruction held in the instruction holding means or an older decoded instruction requests data writing to the same register, and the result is 2. The data processing device according to claim 1, further comprising means for outputting a signal indicating that there is a register conflict for the one instruction when the result is positive. 9. Each register is a vector register that holds a plurality of vector elements, and each vector register has write means and read means that can operate in parallel with each other to sequentially access the vector elements in each vector register, and each resource The detection means sequentially receives vector elements from the vector register or sequentially supplies vector elements to the vector register, and the detection means requires writing to the vector register in which one instruction held in the instruction holding means is located. In this case, the data processing device according to item 1, further comprising means for determining that the instruction can be executed even if the vector register is in a read state.