SU1352493A1 - Device for forming identification signal of computer instruction start - Google Patents

Abstract

The invention relates to a pulse technique and can be used in debugging devices of a computer system. The goal is to increase accuracy. The device contains a trigger 1, a node 2 blocking the counter, three elements And 3,5,8, a counter 6. element OR 4, a delay element 7, an encoder 9. The device allows you to debug the program of the tested mini-computer at the lowest cost. 2 Il. "L from from 01 to 4 00

Description

The invention relates to a pulse technique and can be used in devices for debugging programs of a computer system 1.

The aim of the invention is to improve the accuracy of signal formation.

FIG. 1 shows a block diagram of the device in FIG. 2 is a block diagram of the meter blocking node.

The device contains a trigger 1, a node 2 blocking the counter, the first element AND 3, the element OR 4, the second element AND 5, the counter 6, the delay element 7, the third element AND 8, the encoder 9, the inversion input 10, the direct access enable input 11, data highway 12 input, initial setup input 13, direct memory access input 14, interrupt indication input 15, information input 16, a group of information inputs 17, command start 18 output.

Node 2 lock counter contains the first trigger 19, the second trigger 20, the element And 21, the element 22 of the delay. Node 2 lock counter

provides preservation-value of the counter for the counter and the output of the element OR 4. When

6 when implementing the procedure of extra-processor data transmission over the mini-computer data highway. The encoder 9 establishes a specified correspondence between the code of the input information signal, the signal level at the clock input and the code stored in counter 6.

To perform its functions, the device is connected to a mini-computer with few Q pulses. In all - / steel-following way.

 The mini computer mainline is connected to the group of information inputs 17 of the device.

Signal tires: PVB (device sampling confirmation); RP, TS (Direct Access Permission) -; ZAN (Data Highway Usage Index); PODG (System Reset to Initial State) J CX3 (Master Sync) i PREP (Processor Program Interrupt Request); The SHI (Synchronization of the Executive) j mini-computers are connected to the inputs 10-16 of the device, respectively.

At the initial moment of time, a signal to reset the system to its initial state (POD), coming from the input of the device 13 to the quarter input of the node 2

cases (when the information on the data of the mini-computer should not i. be identified as the code of the first word of the instruction

45) the signal SHI acts as the counting pulse of the device.

When executing a mini-computer, the instructions read in the first cycle of data exchange on the miniGQ data bus of a computer, the sequence of issuing control signals determining the exchange and used in the device is also, namely: issuing CXZ signals; Reception performer SHH, vschacha on

ds data history of a certain information; installation of a CXIi; receiving information on resetting the PSS; reset SHI.

After reading the first word of the tool, exit counter 6, in which

locking the counter and the first input of counter 6, resets the device to its original state. In this case, a high potential is supplied to the first inputs of the AND 3.5 and 8 elements from the output of the blocking counter, and a low potential from the output of the counter 6 to the information input of the trigger 1.

After that, the mini-computer reads the first word of the instruction to be executed.

The minicomputer issues a SHI (Executive Sync) signal, which

through the input 16 of the device enters the input of the element And 8. At the same time, the element And 8 opens, i.e. its first input is supplied with a high potential from the output of node 2 of the meter’s blocking and on the leading edge of the pulse from the output of the element AND 8, the unit is summed to counter 6. At the same time, the SHI signal with a delay due to the presence of element 7

delays, arrives at the third input of the element And 5. It opens, since high potentials arrive at its first and second inputs, respectively, from the output of block 2

five

this sets the additional number of pulses in counter 6.

Nadz note that the SHI signal corresponding to the moment of passing the mini-computer code of the first word of the instruction to be executed is used in the device as a recording strobe into the code counter of the number of pulses. In all - / steel-

In many cases (when the information on the data bus of the mini-computer should not i. be identified as the first word code of the instruction to be executed), the SHI signal acts as the counting pulse of the device.

When executing a mini-computer, the instructions read in the first cycle of data exchange over the mini-computer data line, the sequence of issuing control signals determining the exchange and used in the device is the same, namely: issuing signals of the sanitary control system; Receiving the contractor of the SHZ, on the data line of certain information, installing the CXIi; receiving information, resetting SHZH; reset SHI.

After reading the first word of instruction on the output of counter 6, in which

an additional pulse number code was set, and a high potential is applied to the information input of trigger 1. Therefore, the first signal of the CXS (the first after reading the instruction code) trigger 1 will stop in an eternal state and low potential from its inverse output will close element 5. And this will install into the counter 6 a new pulse number code. At the same time, the low potential from the inverse output of the trigger 1 goes to the second input of the element 15, which closes and the low potential at its output (which is connected to the output of the device 18) indicates that the information on the mini-computer data line should not be identified. as the first word of the instruction to be fulfilled (the mini-EBM has begun to implement the instruction and exchange information defined by it).

In the process of exchanging data over a data source of mini-computers, counter 6 is filled (according to the signals of the SHI, which in this case are countable for the device). By overflowing the counter, which is a sign that the miniature electrical machine has finished executing the instruction, the low potential from its output goes to the information input of trigger 1, and the very first CXS signal that is initial in the procedure for reading the first word of the next the instruction to be executed, trigger 1 is reset to the zero state.

A high potential from an inverse 40 output through an OR 4 element enters the second input of element 5. At the arrival of the signal from the SHI (on the data bus of the mini-computer there is an instruction code), a setting is set into the counter 45 6 of the new additional code of the number of pulses defined by the code the first word of the instruction to be executed and. In the future, the operation of the device is similar to the gg described method.

Consider the operation of the device on a specific example of performing a specific instruction. In this case, we assume that the device is in the IC-gc

the output state (counter 6 is reset to the zero state from the output of block 2 of the counter 2, to the first inputs of the And 3.5 and 8 elements,

the high potential) j instruction to be executed is the instruction to transfer the word MoV X, (R2) machine code 013712. In this case, the source is absolutely addressed and the address is indirectly addressed (via register) to the receiver of the operand. The instruction dumps the contents of the memory location whose address is indicated by an X and is stored in the second word of the instruction in a memory location whose address is specified in R2. The execution of the instruction includes the following steps: reading the first word of the instruction containing the operation code, the addressing mode and the receiver; reading the second word of the instruction that is the address of the memory location — the source of the operand j reading the operand from the memory location whose address was specified in the second word of the instructionj — sending the operand to memory location — the destination of the operand.

Since the moment of reading the first word of the instructions to be executed corresponds to the setting of the new code of the number of pulses in the device, i.e. a single counting device pulse (SHI) is not taken into account, then when 17 devices arrive from a group of information inputs to a group of information inputs of the encoder 9 of the code 013712., from its group to the information

about

Counter 6 inputs must be supplied with the code 1101j (three cycles of data exchange over the mini-computer data highway, that is, excluding the reading of the first word of the instruction in the additional code). At the same time, code 1102.2 will be set to counter 6. This will count the three cycles of information exchange on the mini-computer data line. Upon the arrival of the third after the end of the reading procedure of the first word of the instruction to be executed (SHI signal), the counter 6 will overflow. From its output to the input of the trigger 1 will be given. low potential And the first (after overflow) signal of the SCS, which is the initial one in the procedure of reading the first word of the next instruction to be executed, will reset trigger 1 to the zero state. In the subsequent operation of the device occurs in the same way as described (only the code entered into counter 6 is changed, depending on

from the code of the first word of the instruction to be executed).

The encoder works as follows,

In the case of a transition to the mini-computer to the external interruption service procedure, the transition algorithm to the service subroutine following the arbitration of the received interruption requests, the device that obtained access to the mini-computer data line exposes its interrupt vector to it and generates a PEPP signal the interrupt vector is the address of the memory word in which the new processor PC is stored; reading from the memory of the new PC processor; reading from the memory of the next word ((PC) +2), which is a new PS processor, writing to the stack of the old PC processor; write to the stack of the old PS processor; go to reading the first word of the first instruction of the interrupt handling routines.

The moment of reading the mini-computer of the interrupt vector corresponds to the setpoint in the counter 6 of the new code of the number of pulses. Therefore, the first in the transition procedure to the interrupt service routine is a device counting pulse (SHI) recording a new setpoint in counter 6, the first word of the first instruction to be executed by the interrupt service routine on the mini-computer data line should occur after the count of counting pulse pulses devices (SHI) (setpoint code 11002), the setpoint being entered into counter 6 should not depend on the interrupt vector code coming from the data bus

minicomputer per group of information inputs 17 devices. Therefore, when the PREP signal arrives at the device input 15, it sets trigger 1 to one state. The low potential from the inverse output of the trigger 1 is fed to the second input of the OF element, the element is closed. The low potential from its output goes to the output 18 of the device, and this indicates that the information appearing on the mini-computer data line in the procedure for switching to the service of the aborting subroutine should not be identified as the first word of the instruction . At the same time, the PREP signal through the element OR 4 is fed to the second input

50

5 0 5

0

5 0 5

element 5, thereby preparing the device for setting into counter 6 of the new code of the number of pulses. However, it has already been said that the setpoint entered in counter 6 should not depend on the input information signal. Therefore, the PEPP signal is applied to the clock input of the encoder 9, and regardless of the interrupt vector code from the mini-computer data bus to the group of information inputs 17 of the device, the IIOOj code is fed from the output of the encoder 9 to the group of information inputs of counter 6. When the CXI signal following the PEPP arrives, this code is set into counter 6. The device making the request and receiving as a result of arbitration of requests for interruption access to the mini-computer data line gets the set from the CXI, removes its interrupt vector from the data line then the PREP reset. By resetting the PREP signal, code 1100 is removed from the output of the encoder 9 ,.

The installation of the IIOOj code in counter 6 provides for the counting of four cycles of information exchange on the mini-computer data highway (excluding the transmission vector of the interruption vector) in the procedure of transition to the interrupt routine. On the fourth counting signal of the device (SHI), counter 6 will overflow. From its output, low potential will be supplied to the information input of trigger 1. Therefore, according to the order of the signal of the SCS (following the last, fourth, signal of the SHI), which is the initial in the procedure of reading the first word of the first instruction of the interrupt processing subroutine to be executed, trigger 1 is reset to the zero state. In the future, the device operates in the same way as when executing an interrupted program.

The operation of the counter lockout unit is carried out as follows.

. The node 2 of the blocking of the counter ensures that the value of the counter 6 is preserved during the implementation of the out-of-processor data transfer procedure and simultaneously sets a low potential at the output 18 of the device. This is due to the fact that not a single word from the data transmitted via the highway of the mini-computer during the direct access can be identified as the first word to be executed at the given time of the instruction.

At the initial time, the signal ZAN is not installed. Therefore, the low potential from the input 12 of the device is fed to the inverse installation (R) input of the trigger 20. The trigger 20 is reset to the zero state. The initial preparation signal, which from the input 13 of the device is fed to the setup (R) input of the trigger 19, also resets it to the zero state. The inverse output of the trigger 20 is the output of the counter lockout node 2. Therefore, at the initial moment of time from the output of the blocking node of the counter to the first inputs, the first word is subject to

And 3.5 and 8 elements are supplied with high potential, which ensures the operation of the device in a similar way. In the case of re-initiating the procedure of extra-processor data transmission, the sequence of issuing control signals governing the procedure of extra-processor data and used in the device is as follows: (direct access permission); output signal UIP (confirmation of the sample requesting device); installation by the requesting device of the PIT signal, from that moment on the requesting device becomes the master of the bus and starts information transmission cycles; the arbitrator, having received the PVB installation, resets the RCC; shortly before completion of the transfer of information, the setting device resets the PVB; completing the data transfer, the master resets the ZAN,

In accordance with the described sequence, the node 2 lock counter operates as follows 5 (Fig, 2).

The PVB and RCC signals, arriving respectively from the inputs 10 and 11 of the device, to the first and second inputs, respectively, of the element 21, open it and the flip-flop 19 is set to a single state. When installing the ZAN signal, its leading edge comes to the clock (C) trigger input 20 with a delay (due to the delay element 22) relative to the high potential installation on the inverse mounting (R) trigger input 20, this ensures

to follow the instructions.

At the end of the out-of-processor data transfer procedure, the requesting device resets the ZAN by the data bus of the mini-computer, Trigger 20 is reset to the zero state. At the same time, the elements And 3.5 and 8, t, e are opened. the operation of the device to execute the first word of the instruction to be executed continues from the moment when the execution of the mini-computer program was interrupted by a request for non-processor transfer of data. At the same time, the positive edge of the signal that is formed

40

when the flip-flop 20 is moved from one state to zero, the inverted output is fed to the clock input of the flip-flop 19, because by this time the low potential is applied to the set input of the flip-flop 19 from the output of the And 21. (PVB and RCC signals are reset) the trigger 19 is also reset to the zero state, thereby the node 2 of the blocking of the counter goes to the initial state.

Claims (1)

Formula invented and 50 A device for generating an identification signal of the beginning of a computer command, comprising a trigger, a counter, and an encoder, the group of information inputs of the device being connected to the group of inputs of the encoder, the output of the overflow of the counter is connected to the information input of the trigger, which is due to the fact that The flip-flop 20 is set to one, because its potential input is supplied with a high potential from the flip-flop output 19. A low potential from the inverse flip-flop output of the flip-flop 20, which is the output of the counter-lock node 2, is fed to the first inputs of the AND 3.5 and 8 elements. . Thereby they are closed, which excludes both the change in the number of pulses code recorded in counter 6 and the entry in it of a new code of the number of pulses. The low potential at the output of the element And 3 indicates that all the information that is transmitted through the data bus of the mini-computer during the procedure of non-processor data transfer should not be identified. five to follow the instructions. At the end of the out-of-processor data transfer procedure, the requesting device resets the ZAN by the data bus of the mini-computer and the Trigger 20 is reset to the zero state. At the same time, the elements And 3.5 and 8, t, e are opened. the operation of the device for the execution of the first word of the instruction to be executed continues from the moment when the execution of the mini-computer program was interrupted by a request for non-processor transfer of data. At the same time, the positive edge of the signal that is formed 0 when the flip-flop 20 is moved from one state to zero, the inverted output is fed to the clock input of the flip-flop 19, because by this time the low potential is applied to the set input of the flip-flop 19 from the output of the And 21. (PVB and RCC signals are reset) the trigger 19 is also reset to the zero state, thereby the node 2 of the blocking of the counter goes to the initial state. Formula invented and A device for generating an identification signal of the beginning of a computer command, comprising a trigger, a counter and an encoder, the group of information inputs of the device being connected to the group of inputs of the encoder, the output of the overflow of the counter is connected to the information input of the trigger, which is due to the fact that increasing the accuracy of signal formation; three AND elements, an OR element, a delay element, a meter lockout node containing the first and second triggers, an AND element and a delay element, the access inputs, the direct access enable and the initial installation of the device are introduced into the device - Vym and second inputs of the element AND for the blocking of the counter and the input of the zero setting of the first trigger of the node of the blocking of the counter; the input of the device data highway is connected to the input of the zero setting of the second trigger and through the delay element - with the clock input of the second trigger of the lock block of the counter, the output of the AND blocking node of the counter is connected to the single input of the first trigger of the lock block of the counter, the output of the first trigger of the lock / f node of the counter is connected to the information input of the second trigger of the blocking node counter, information input of the first trigger of the lock / counter node is connected to the zero potential bus, inverse output of the second trigger of the lock block of the counter Compiled by; Sigalov Editor U. Sereda Tehred M. Khodanych Proofreader A. Obruchar Order 5567/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod,. Ul. Project, 4 connected to the clock input of the first trigger of the counter lockout node and to the first inputs of the first, second and third elements I, the initial setup input of the device is connected to the zero input of the counter, the input of the device memory access sign is connected to the clock input of the device trigger, the interrupt sign input of the device is connected with a single input of the device trigger, with the first input of the OR element and with a clock input of the encoder, the output group of which is connected to the group of information inputs of the counter, the input of the information sign device is connected to the second input of the third element AND and through the delay element to the second input of the second element AND whose output is connected to the clock input of the counter, the inverse output of the device trigger is connected to the second inputs of the OR element and the first AND element whose output is the output of the feature the beginning of the device command, the outputs of the element OR and the third element AND are connected respectively to the third input of the second element AND and the counting input of the counter. FIG. 2