SU1714575A1 - Process equipment programmable controller - Google Patents

Abstract

The invention relates to software control systems and can be used in automated systems for controlling process equipment. The purpose of the invention is to increase the speed and expansion of the field of application of the COP. A device for software control of process equipment includes a microprocessor 1, a clock generator 2, a system controller 3, buffer amplifiers 4, an address decoder 5, a program memory 6 unit, a data memory unit 7. tire driver 8 operative, .LZ.2

Description

memory, decoder 9 input-output devices, bus driver 10 input-output, six elements OR 11-16, two elements AND 17 and 18, three triggers, bus driver 22, register 23, comparison circuit 2k, priority encoder 25J multiplexer 26, element 27 delays The goal is achieved by implementing a logical interrupt mode. New in the system are the three elements OR 1A-16 two triggers 20 and 21, priority encoder 25, multiplexer 26, delay element 27. 2 tabl., K Il.

The invention relates to software control devices and can be used in automated systems for controlling technological equipment, for example, in computer numerical control systems of production complexes, robots, manipulators, etc.

A software control device is known comprising sensors, a pulse generator, triggers,

decoders, unit and tens counters, program block block, element; AND, OR, NOT. Its disadvantage is low productivity. The closest to the offer is a device for programmed control of technological processes consisting of a microprocessor, a clock generator; a system controller, a memory address decoder, a RAM, a fixed memory; bus driver memory of I / O address decoder, bus driver I / O, Tijiex bus driver for trigger, register, comparison circuit, four AND schemes, three OR schemes.

The disadvantage of it is low speed and narrow scope. This is due to the following circumstances.

The technical means of the prototype provide multi-alternative branching according to the value of the logical conditions coming from the sensors, at strictly defined moments of time, when the corresponding subprogram is connected to the main program. In this case, the fact of a change in the logical conditions, i.e. if they have not changed, then the multi-alternative branching will be idle - a control signal will be generated the same as in the previous 8e. If the logical conditions have changed, and the time of their survey

has not yet come, this leads to a decrease in the reaction time, which lowers the speed with multi-alternative branching with respect to the rate of change of logical conditions; I cannot use a known device in real-time tasks that require maximum response, for example, in emergency situations of process equipment, from which not one sensor signals, but several (and in some cases accounting and process history are necessary).

All this reduces the speed of the known device and reduces its area of application.

The purpose of the invention is to increase speed and expand the scope.

The invention consists in increasing the speed and expanding the field of application of a device for software control of technological equipment by introducing a logical interruption-interruption discipline with the formation of automatic mappings that are higher in priority than ordinary interrupts; in the program record in the register of the initial state of the inputs of logical conditions; in the software resolution of the logical interrupt by outputting the logical unit to the first trigger; in the formation of normal interrupts as well as interruptions when the state of the inputs of logical conditions that are higher in priority than ordinary interrupts changes; in the offset of the addresses of the fixed memory for addressing the logic interrupt response programs, which for the microprocessor is located at the same addresses as the addresses of the subroutines (vectors) of the normal interrupts; in software generation of automaton mappings for processing changes in the state of the inputs of logic conditions (realization of a sequential or combinational automaton) with the issuance of control actions on information outputs; in a programmatic removal of the offset of the addresses of the permanent memory after the microprocessor reads a return command from the logical interrupt to the main program, as well as writing a new state of the logical conditions to the register.  Introducing the second trigger and the corresponding connections allows you to shift the address space of the program constant memory block, switch the multiplexer on the interrupt acknowledge signal if the values of the logical conditions have changed, and also record the changed value of the logical conditions in the implementation of the new discipline - logical interrupt - with the formation of auto-, Matn1x mappings.  The introduction of the third trigger and the corresponding links allows it to form an interrupt request both with a regular interrupt and with a logical interrupt — with the formation of automaton mappings.  The introduction of the priority encoder and its corresponding connections allows the generation of a request code that is higher in priority, and a request presence signal at ordinary interrupts, lower priority logic interrupts with the formation of automaton mappings.  The introduction of the multiplexer and the corresponding links allows the formation of an interrupt vector, both for ordinary interrupts and for logical interruptions with the formation of automaton mappings.  Introducing the delay element and its associated links allows the second trigger to be zeroed after the microprocessor reads the return command from the logical interrupt to eliminate the offset of the block of permanent program memory by the second trigger.  The introduction of the fourth OR element and the corresponding connections allows zeroing the second trigger at the initial reset and, at the end of the logical interrupt, at the signal of the delay element.  The introduction of the fifth OR element and the corresponding links allows l to set a third trigger for generating an interrupt request both for a normal interrupt and a logical interrupt.  The introduction of the sixth OR element and the corresponding links allows the third trigger to be zeroed after the microprocessor enters the interrupt-handling cycle.  When using the present invention, a positive effect can be obtained, which is to increase the speed and expand the scope of application.  FIG. 1 is a functional block diagram of the system for software control; in fig. 2 - a fragment of the timing diagram of the reaction of the system to the usual interruption; in fig. H is the same, the reaction to logical interruption with the formation of automaton mappings; in fig.  - a graph of a sequential automaton from an example of a specific system implementation.  The device for software control of the process equipment contains a microprocessor 1 containing outputs 1. 1 addresses, a group of I / O 1. 2 data outputs 1. 3 control recording and receiving data, clock inputs of the first I.  and second one. 5 phases, reset inputs 1. 6, readiness 1. 7, synchronization output 1.8, input 1. 9 interrupt request, exit 1. 10 enable interrupt clock generator 2 containing inputs 2. 1 and 2. 2 connections of the quartz resonator, input 2. 3 synchronization, clock outputs of the first 2. 4 and second 2. 5 phases, output 2. 6 reset, exit 2. 7 readiness, exit 2. 8 synchronization, system controller 3 containing the first group of information inputs and outputs, the second group of information outputs and inputs 3. 1, which is a device data bus, memory control outputs 32, memory writing, input control input, output output, interrupt acknowledgment, device control bus, buffer amplifiers A, coaxial outputs. 1, the device address bus, the decoder 5, the memory address containing output 5. 1 connection of program block 6 of program memory, block 7 of data RAM, bus driver 8 of RAM, decoder 9 of I / O devices containing a group of outputs 9 and I / O device connections, outputs 9-2 and 93 bus shapers 10 I / O devices, six elements OR 11-16 two elements AND 17 and 18; three triggers, bus driver 22, register 23, comparison circuit and priority encoder 25, having information outputs 25-1 and output 25. 2 controls, multiplexer 26, delay element 27, reset input 28, ready input 29, capture input 30, and output 319 information inputs 32, information outputs 33, inputs 3 logic conditions, interrupt request inputs 35.  The third and fourth inputs of the clock generator 2 are the reset inputs of the 28 l ready device 29, respectively.  The first 2D and second 2, the clock outputs of the clock generator 2 are connected to the first 1.  and the second 1.5 clock inputs of microprocessor 1, respectively.  The third 2.6 and fourth 2.7 outputs of the clock gene, rator 2 are connected to the reset inputs 1 6 6 and readiness 1. 7 microprocessor 1, respectively.  Fifth exit 2. 8 clock generator 2 is connected to the synchronization input of the system controller 3.  Address Outputs 1. 1 microprocessor 1 is connected to the inputs of the buffer amplifiers k.  The group of input-output data 1c2 and outputs 1. The 3 control recording and receiving data of the microprocessor 1 is connected to the first group of information input-output and the recording control input and receiving data of the system controller 3, respectively.  The microprocess trap 1 input is the system capture input 30.  The microprocess wait output; pa 1 is the system idle output 31.  The output of the data reception control of the microprocessor 1 is connected to: the control of the inputs of the block 6 of the program memory, the bus driver 8 of the RAM, and the first input of the first element I 17.   The combined inverse outputs of the resolution of the buffer amplifiers k are connected to a negative power supply bus whose outputs are the bus Al address of the device.  The second group of information inputs / outputs of the system controller 3 is bus 3. 1 device data.  The read control outputs of the memory, write to memory, input, output, confirmation of the interrupt of the system controller 3 are bus 3. 2 device controls.  The group of information inputs of the decoder 5 memory addresses, the outputs of the decoder 9 input-output devices, the address inputs of the block 7 RAM data block. 6 program memory is connected to the bus. 1 device address.  The enable input of the address decoder 5 is connected to the output of the first element OR 11, the first and second inputs of which are connected to the outputs of the memory read and write control outputs of bus 3. 2 controls laziness respectively.  First exit 5. 1 of the address decoder 5 is connected to the first resolution input of block 6 of the program permanent memory.  -Second exit 5. 2 address decoder 5 is connected to the enable input of the bus driver 8 of the RAM and to the enable input of the RAM block 7.  The information inputs of the data RAM block 7 are connected to the second group of information inputs of the bus driver 8 RAM.  The information outputs of the data RAM block 7 are connected to the third group of information inputs / outputs of the bus driver For RAM.  I The enable input of the I / O decoder 9 is connected to the input control outputs from the input and output devices to the output devices of the system controller 3 via the OR 12 element, respectively.  Exit group 9. 1 of the I / O device decoder 9 is connected respectively to the enable input group of the bus driver 10 I / O devices, the enable input of which is connected to the input control output from the input device of the system controller 3.  The inputs of the bus driver 10 I / O devices are the information inputs 32 of the system, and the outputs the information outputs 33 of the device.  The output of the first element And 17 is connected to the enable input of the bus driver 22.  The reset inputs of register 23 and the first trigger 19 are connected to output 2. 6 reset the clock generator 2.  The outputs of register 23 are connected to the first group of yodes of the comparison circuit 2, the output of which is connected to the first input of the second element I 18, the second input of which is connected to the output of the first trigger 19, the information input of which is connected to the bus 3. 2 system data.  The synchronization input of register 23 is connected to the output of the third element OR 13, the first input of which is connected to the third output 9. 3 of the decoder 9 of the input / output device, and the second input is connected to the output of the second trigger 20 connected to the address input of the multiplexer 2b, the upper address input of the program memory 6, and the additional information input of the address decoder 5.  Third exit 5. 3 decoder 5 address is connected to the input of the element 27 of the delay, the output of which is connected to the first input of the fourth element OR I.  The second inverse input of the fourth element OR 1 k is connected to the output of the first trigger 19. The third input of the fourth element OR I is connected to the reset input of the first trigger 19-The output of the fourth element OR 1 is connected to the reset input of the second trigger 20, whose information input is connected to the output of the 2k comparison circuit, and the synchronization output of which is connected to the interrupt confirmation output of the system controller 3 synchronization of the first trigger 19 is connected to the second output 9. 2 decoder 9 I / O devices The information inputs of the register 23, the second group of inputs of the 2k circuit as compared to the second group of inputs of the multiplex 26 are the inputs 3 of the logical system conditions.  The second input of the first element And 17 is connected to the output of confirmation of the interruption of the system controller 3.  The third input of the second element And 18 is connected to the output 1. 8 synchronization of the microprocessor 1, and its fourth input is connected to the output 1. 10 microprocessor interrupt enable 1.  ; The output of the second terminal And 18 is connected to the first input of the fifth element OR 15, the second input of which is connected to the output 25. 2 control priority encoder 25.  The inputs of the priority encoder 25 are the inputs 35 of system interrupt requests.  Information outputs 25. 1 of the priority encoder 25 is connected to the first group of inputs of multiplexer 26, the outputs of which are connected to the first group of information inputs of the bus driver 22, to the second group of information inputs of which are connected the outputs of the driver unit Vector transition commands performed by connecting the corresponding bit driver to the limiting resistor to positive pole of the power source.   The output of the fifth element OR 15 is connected to the data input of the third three | - Gera 21, the reset input of which is connected to the output of the sixth element OR 1b.  The first inverted input of the sixth element Or 1b is connected to output 1. 10 enable interrupt microprocessor 1, and its second input is connected to output 2. 6 reset the clock generator 2.  The output of the third trigger 21 is connected to the output 1. 9 microprocessor interrupt request 1.  The synchronization input of the third trigger 21 is connected to the clock output 2. 4 first phase clock generator 2.  The microprocessor 1 is designed to run the program, t. It is a sequence of commands used to implement a control algorithm and to control a system with bus organization.  The microprocessor senses external clock signals and external 30-33 control signals and generates address signals (1. 1) data (1. 2) as well as control signals (b3).  The microprocessor 1 can be implemented, for example, on a standard integrated circuit KR580IK89A.  The clock generator 2 is designed to form two high-voltage (12V) non-overlapping clock pulses (2. 4,, 5), the formation of control signaling reset (2. 6) and readiness (2. 7) about external signals of the system (2. 8, “9) and to form a system throw (2. 8) according to the sync pulse (2. 9), which is accessible from microprocessor 1, and can be implemented, for example, on a standard integrated circuit KR580GF24, (legs 13,12 and 6 are not connected).  The system controller 3 is designed to increase the load capacity of the bus 3. 1 of data and the organization of bi-directional MBHHBIXS transmission for fixing the control word of microprocessor 1, coming over the data bus at the moment of the system strobe arrival (2. 8) from the clock generator 2, and forming in accordance with the control word and data recording and receiving signals (1. 3) microprocessor 1 bus 3. 2 device controls for each machine cycle.  The 11th control of the device includes control signals for reading the memory, writing to the memory, inputting to the input device, outputting from the system, confirming the interrupt, System Controller 3 can be played, for example, on a standard CRF80BK28, Buffer amplifiers and bus drivers B and 10 are intended to increase the load capacity of the data bus of the system data and to organize bi-directional data transmission over bus 3. 1 data (second group of outputs-inputs of the system controller) to memory blocks or from memory blocks, to external devices or from external devices, depending on control signals E1 and E2; In the absence of control signals, the outputs of bus drivers are in high impedance condition ,.  disconnected from the data bus.  The bus formers can be implemented on standard integrated circuits 589 ltb. The bus driver 8 of the data storage unit is designed to increase the load capacity of the bus data 3. 1, d, under the outputs of the unit 7, operating system: bus to the bus 3. 1 data in read mode, for connecting the data inputs of the RAM block 7 to the data bus 3 "in record mode.   Bus bar drivers 10 for input and output are designed to increase the load capacity of the GTP bus data and to connect to the bus Z. The delivered data inputs 32 in the input mode from input devices, for connecting bus 3. 1 data to information outputs 33 in output mode to output devices.  Buffer amplifiers k are designed to increase the load capacity of the bus A. 1 addresses of the system, as well as to translate their outputs into a high-impedance state when activating the discharge. Confirmation of the capture of the outputs 1. 3 microprocessor controls 1. i The address decoder 5 is designed to decrypt the address set by the bus. 1 address of the system, if the output of the element OR 11 is activated.  To connect the block of program constant memory, the output 5-0 of the decoder 5 is excited; to connect the block 7 of the RAM and the bus driver 8 of the RAM - output 5. 2  In addition, the address decoder 5 takes into account the information at the output of the trigger 20 and decrypts the return command addresses from the logic interrupt processing programs.  At the same time, output 5 is excited. 3  In the normal operation mode, the address bus decryption is performed taking into account the zero state of the output of the trigger 20.  Address decoder can be implemented, for example, on standard integrated circuits 155IDZ.  The decoder 9 I / O devices designed to decrypt information on the bus j. l system addresses if the output of the OR 12 element is activated to connect the I / O bus driver 10 and initialize the system to a logic interrupt.  To connect the I / O bus drivers 10, one corresponding bit of the output group 9 is activated. 1 external device connection.  To gate a trigger 19 that has a specific address when outputting to that address (input to this address is not used), output 9 is activated. 2  For gating trigger 23 through the element OR 13, output 9 is excited in the same way. 3  The decoder 9 input-output-j-water devices can be implemented, for example, on standard integrated microcircuits-f max 155 Idz.  The first element, OR 11, is intended to form the E1 enabling signal of the decoder 5 of the memory address, according to the bus 3. 2 controls one of the read / write memory control signals.  The second element OR 12 is intended to form a permitting signal for the decoder 9 input-output devices with bus 3 present. 2 control none of the input control signals from an input or output device to an output device.  The third element OR 13 is designed to control the synchronization input of the register 23 as output 9. 3 of the decoder 9, and the output of the second trigger 20 for writing to the register 23 or the initial state of the logical conditions of the inputs 3, or for writing the modified and already processed value of the logical conditions of the inputs Z.  The fourth element OR k is intended to control the zeroing input of the second flip-flop 20 either at initial reset from output 2 to 6 of generator 2, or by the signal from the output of delays 27 at the end of the logical interrupt - after reading the return command by microprocessor 1, or if there is no permission for logical interrupt (the first trigger 19 is reset). The fifth element OR 15 is designed to control the data input of the third trigger 21 for generating an interrupt request or a signal from output 25. 2 priority encoder 25 (normal interrupt) or a signal from the second element (logical interrupt).  The sixth element OR 1b is designed to control the reset input of the third trigger 21, either at initial reset, with a signal (2.6) of the clock generator 2, or if the output T o 10 is zeroed and the microprocessor interrupt is enabled 1 o When the output of the OR 16 is activated, trigger 21 is reset regardless of information on its data output and synchronization. The first element And 17 is designed to control the enable input of the tires of the hojo driver 22 to connect its outputs to the bus 3. 1 data.  In the event that on the tire 3. 2 control there is a control signal for confirming an interrupt, and at the outputs 1. 3 microprocessor controls 1 data receive signal, i.  when the microprocessor reads the interrupt vector from the data bus.  The second element AND 18 is designed to control the fifth element OR 15 when generating a request for a logical interrupt if the output of the comparison circuit 2C is activated (logical conditions have changed), interruptions are enabled (output 1 is activated. 10 microprocessor 1), a clock pulse arrived from output 1 - 8 of microprocessor 1 and the first trigger 19 was set.  The first trigger 19 is intended for the d / 1 control of the second element AND 18 and the fourth element OR N in order to resolve the logical interruption discipline.  If these are forbidden, then AND 18 is blocked, and three | - ger 20 through OR OR I is held in the zero state. The first trigger 19 is set to the zero state by initial reset on its asynchronous zero input, set and zeroed by the bus. data on the leading edge of the signal at the output of the decoder 9 The first trigger 19 can be implemented, for example, on a standard integrated circuit 155TM2. The second trigger 20 is designed to control the high-order address of the block 6 of the fixed memory npoi- frame, input m address multiplexer 2b and the third elementom OR 13 when implementing second logical interrupt trigger 20 is set on the rising edge of the control signal is an interrupt acknowledge bus control SO2 if activated output circuit 2k comparison.  This is necessary to ensure the priority of changes in the logical conditions of inputs 3 with respect to requests for inputs 35 Thus, even if the interrupt request (1. 9) triggered by a request received earlier on inputs 35, but the logical conditions have already changed, or the queries were received simultaneously, the second trigger 20 is established when the interrupt acknowledgment is generated, it switches the multiplexer 20 off, providing a constant address offset of 6, m. her.  will provide the implementation of the ogic interrupt.  If interrupts are disabled by software, trigger 20 will never be set, as there will be no interrupt acknowledge signal synchronizing it.

The second trigger 20 is zeroed through the OR element 1k, either the initial slam, catfish, or at the end of the logical interrupt, or is kept in the zero state by the output of the first trigger 19.

The second trigger 20 may be implemented, for example, on a standard integrated chip 155TI2.

The third trigger 21 is designed to form an interrupt request to the corresponding input 1.9 of the microprocessor 1 when its data is excited by the output of the fifth element OR 16 by the sync pulse at input 1.} Microprocessor i "The trigger 21 is zeroed by the OR 16 element or is kept in zero state when interrupt is disabled. When this prohibition is cleared (if the output is reset to OR 16), if the next requests are received (the output of the element OR 15 is activated), the third trigger 21 is set to the state of logical unit by the output 2 sync pulse, and generates the next interrupt request

The third trigger 21 can be implemented, for example, on standard integrated circuits 155TM2.

The bus driver 22 is intended to output to the bus 31 the data of the interrupt vector command code, having at the output of the multiplexer 26, when activating its enable input with the bold element I G /.

the driver of the vector-transition command is realized by connecting the bits of the inputs 7,6,0,1,2 of the bus driver 22 to the positive pole of the power source through the limiting resistor, as indicated in FIG. 22 can be implemented, for example, on standard integrated circuits 585 AP16. Register 23 is intended for recording and storing the code of logical inputs 3 or of the source code or the code processed in the last logical interrupt. The information from inputs 3 is entered into register 23 by the falling edge of the signal at the output of the element OR 13. Register 23 is zeroed by the initial gate - output 2.6 of generator 2. Register 23 outputs the stored code permanently to the 2k comparison circuit.

Register 23 can be implemented, for example, on standard integrated circuits 155IR13.

Comparison circuit 24 is designed to compare the current code of logical conditions at input 3 with the source code, or with the last processed code stored in register 23. During non-comparison, its output is activated to control the element 18 and the trigger 20.

Scheme 2 comparison can be implemented, for example, on standard integrated circuits 533SP1.

The priority encoder 25 is designed to encrypt with the priority of ordinary requests for stay on inputs 35. and generates on device outputs 25.1 the device number code, the highest priority of all devices that put logical units on inputs 35. 25.2 Priority Encoder 25o Priority Encoder 25 can be implemented, for example, on standard integrated circuits 155IV1.

The multiplexer 26 is designed to connect to the bus driver 22 either the device code (senior in priority) from the outputs 25-.1 of the priority encoder 25 (normal interrupt) or the actual logical conditions from inputs 3 (logical interrupt). The address input is controlled by trigger output 20. If it is set to zero, information from the outputs 25.1 of the priority encoder 25 is transmitted to the output of the multiplexer, if it is set, from inputs 3.

The multiplexer 26 can be implemented, for example, on standard integrated circuits 155KP1.

The delay element 27 is designed to delay the signal generated at the output of the memory address decoder 5 in order to zero the trigger 20 after the microprocessor 1 reliably reads the return address to the main program from the logical interrupt, since this command is written in block 6 of the persistent memory These programs are at the address with the unit in the higher order activated by the output of the second trigger 20, and the main program is located at the addresses with a zero in this senior rank. When microprocessor 1 reads the return command (the output 5.3 of the decoder 5 is excited at its address), starts the operation to retrieve the return address from the stack (internal operations without accessing the memory), then the pulse at the output of the delay element 27 through the element OR OR reset the trigger 20. The delay element 27 can be implemented, for example, on an even number of series-connected inverters. The reset input 28 is for receiving an initial system reset signal. The readiness input 29 is intended for receiving an external signal ready from (for example, from slow storage media when loading the memory unit 7). Capturing input 30 is for receiving a capture signal, for example, from external high-speed storage media for initiating direct memory access. Waiting output 31 is for issuing a wait signal if, at readiness input 29, a logical zero. Information inputs 32 are intended to receive information Signals of equipment status, prograzimyaemyh software without interrupts. Information outputs 33 are designed to issue control signals to the executive bodies, including signals, (generated in a normal and logical interrupt. In a normal interrupt, some of these outputs are turned on by the flags of the devices that caused the interruption after their service. Inputs 3 logical conditions are intended to receive logical conditions, the state of discrete sensors of technological equipment, the changes of which are processed using logical interruptions about the formation of automaton mappings from these The information on the inputs 3 does not change faster than the logical interrupt execution time, taking into account the waiting for the end of the normal interruption, if it has already begun. The interrupt request inputs 35 are designed to receive interrupt request signals (flags of the display, keyboard, operator panel and other The device exposes at the corresponding bit of the inputs 35 a logical unit with a trigger belonging to the technical means of this device, which is zeroed at the end of the service program of the device. The software control device operates as follows Normal interrupt. In this mode, the device software permits interrupts. In this case, at the output of the microprocessor interrupt enable 1.10, a logical unit is set (Figs. 1 and 2). When at least one unit appears at inputs 35, a logical one is set at output 25o2 of the priority encoder, which, via OR 15, sets trigger 21 via synchronous input 2.4, the output of which supplies input 1 to interrupt request 1 of microprocessor 1 unit Microprocessor 1 in the last clock of the last cycle of the current command, detecting an interrupt request, sets its internal interrupt trigger, and resets the interrupt enable trigger and goes into the interrupt processing cycle. In connection with this, the output 1,10 sets a logical zero, which is inverse the input of the element OR 16 resets and blocks the trigger 21, prohibiting the installation of the sync input 2 "4, the code of the device, which formed the request, installed on the output 25.1 of the priority encoder 25- After the microprocessor 1 goes into cycle interrupt processing cycle in a first status word is output to the system controller 3 and is driven by an interrupt acknowledgment signal (INTA in Figure 1 and 2) controlling tire 3.2. Then, the reception control signal (DBIN in FIGS. 1 and 2) of the control bus 3 "2 is energized and the output of the AND element 17 is activated. The enable input of the bus driver 22. From the outputs 25-1 through the ultiplexer 26 and the bus driver 22 to the data bus 3.1 is output one of the interrupt vector (RST in FIG. 2) using the driver of the crossover command. Next, the microprocessor organizes a write to the stack of return addresses (command counter contents: IC in FIG. 0) to the point of the interrupted program and proceeds to program execution at the address corresponding to the entered interrupt vector (RST) code and removes the confirmation signal. The interrupt processing program may include writing to the stack followed by extracting information from all registers, processing information from the device that caused it, necessarily resetting the interrupt request trigger of this device (from the outputs 33, this trigger refers to external equipment and is not indicated in Fig. 1) . Therefore, the logical unit is removed from the inputs 35 ", outputs 25.2, with the priority encoder 25. 3 the software sets the internal trigger for interrupting the microprocessor 1 output. Therefore, logical output is set at output 1.10, and the command to return to the interrupted program is executed. If the other device installs a logical unit at the inputs 35, then the interrupt process will be repeated in the same way, only in accordance with the new code at the outputs of 25.1 priority encoder the device that caused the interrupt will be served. If several devices simultaneously require servicing, then the output of the 25.1 priority encoder will set the code of the device with the highest priority (senior unit). At the end of the maintenance program of this device, interruptions will be serviced sequentially from lower priority devices. Thus, the processing of a normal interrupt caused by flags of external devices requiring servicing in the proposed device is similar to the well-known discipline of interruptions in software control systems. Interruption with the formation of automaton mappings (logical interrupt). If simultaneously with the receipt of requests for inputs 35 (before output 1.10 goes to the logical. Zero state, or in the absence of those, the information on the inputs 3 of the logical conditions changes, then the output of the comparison circuit 2 will set the logical 20 unit according to the sync pulse 1.8 of the microprocessor 1 Since the trigger 19 is preset (during initialization) and interrupts are enabled, the output of the AND 18 element is activated by the pulse at the output 1.8 of the microprocessor 1, which sets the trigger 21 via the output pulse 2, the synchro Output pulse 1.8 overlaps output 2.4.) If trigger 21 is set — a signal from output 25.2 of priority encoder 25 arrived a bit earlier, but output 1.10 of microprocessor 1 did not reset, then state of trigger 21, which has already generated a request for a normal interrupt from inputs 35, does not change, but a logical interrupt will be serviced. If a request is received from inputs 35, output 1.10 is cleared and an interrupt acknowledge signal has already been generated, then the logical interrupt will be served after a normal interrupt. The option shows the simultaneous excitation of the element 18 and the output 25.2 of the priority encoder 25. Similarly, the trigger 21 forms an interrupt request to the input 1.9 of the microprocessor 1, then the resolution is removed from the output 1.10, the trigger 21 is zeroed through the element 16 and is held at logical zero until the appearance of a logical unit at the input 1.10. Next, microprocessor 1 goes into the interrupt processing cycle, forms a control signal for confirming an interrupt on control bus So2 (iNTA in FIG. 3), according to which, as at the output of comparison circuit 2k one, sets trigger 20. Trigger 20 switches multiplexer 26 and activates high the bit address of the inputs of the block 6 of the permanent memory, which is not connected to the address bus, i.e. the offset of the address space of the block 6. Through the OR 13 element, the register 23 records the new values of the inputs 3 logical conditions and the output of the comparison circuit 2k is zeroed after the trigger 20 is reset. The latter is held in the zero state through the OR element 14 by its inverse input, if trigger 19 is reset - i.e. logical interrupt is prohibited. Therefore, the modified information from the inputs 34 through multiplexer 26, bus driver 22, the resolution input of which is activated by the output element: a H17, as described, goes to the data bus 3.1, and the microprocessor 1 perceives it as an interrupt vector, but in reality it has a different meaning: not the device code, which is higher in priority, but the state of logical conditions 36 - that is, the actual state of the sensors of the process equipment. The information (changed, the next state) from the sensors needs to be processed, i.e. create an automaton mapping - in accordance with a certain system of Boolean functions or a truth table that describe the law of formation of control actions on the executive bodies of the process equipment. Microprocessor 1, as before, writes the contents of the command counter to the stack, addresses it according to the interrupt vector (RST in FIG. , 3), which is the code of logical conditions, the first memory cell of the interrupt processing program and executes it, which forms control actions in accordance with given by a system of boolean functions or a truth table. At the end of this program, a control action is output to the output 33 of executing an interrupt enable command (this sets an output of 1-10) and returning to the main program. At the addresses of the return commands (RET4 in FIG. 3), the output 5.3 of the decoder 5 is energized in the main program of interrupt handling programs. Therefore, through delay element 27, the OR I element zeroes the trigger 20. The delay element 27 ensures a delay for reliable reading of the command the return to the address that takes into account the excited output of trigger 20. The latter is reset and the multiplexer 26 is switched. Microprocessor 1 executes an interrupted program. If during the execution of the interrupt handling program from inputs 3, requests for inputs 35 are received, this is not forced to re-install trigger 21, since reset by the excited asynchronous reset input of output 1.10 through the OR element 16 These requests will be served after the processing of the signal from the inputs 3 7522 I after the transition to the main programj. The rate of change of signals at inputs 3 is such that microprocessor 1 has time to process their change. They change no faster than processing their next change and interruption from inputs 35, if it has already begun, i.e. After setting output 1.10 to a logical unit, trigger 21 can again be set according to output 2 clock and a simple or logical interrupt processing starts again. Thus, a new introduced logical interruption discipline with the formation of automaton mappings allows us to accelerate the processing of changing logical conditions in accordance with a given system of Boolean functions or a truth table in comparison with the known invention, in which logical processing (branching by the value of logical conditions) is carried out only at a given point in the program. In the proposed system, a change in the value of logical conditions immediately causes an interruption, the priority of which is higher than the priorities of other devices (operator console, etc.) and the formation of a controlling effect on the executive bodies. At the same time, microprocessor 1 forms transitions to the same addresses as the usual interrupt, and the address space of the unit 5 is shifted to form automata mappings according to its high bit by the output of multiplexer 2.6. If the initial position of the inputs 3 is different from zero, then the microprocessor 1 excites the output 9.3 of the decoder 9 (for example, an output command at the address assigned to the register 23) and OR through the element 13 from the inputs 3 to the register 23 records the initial state of the sensors. Then, the output 9.2 of the decoder 9 is also excited and a trigger is written to the trigger 19 at the bit of the data bus 3.1, thereby allowing a new discipline of the optical interrupt — forming automatic mappings. If it is necessary to prohibit discipline, a logic zero is triggered anaogically in trigger 19, then the controller reacts only to normal interrupts — at inputs 35–2317. The output of element I 18 is activated according to the sync pulse of output 1.8 of microprocessor 1, i.e. - excited output 1.9 which occurs in the last clock of the last cycle of the current command three (a clock pulse is generated in the first clock). The trigger 21 is set on the leading edge of the sync pulse at output 2. of the clock 2 if its zero input is not activated (in this case it is held at zero). The sync pulse output 1.8, activating the output of the element 19 overlaps the clock pulse 2, |.

Table 1 5 An example of a specific implementation of the proposed system based on a microprocessor 580. Let it be necessary to form control actions ZjZ depending on the state of two discrete sensors a, b in accordance with the graph presented in Fig. In the numerator numerals the denominator is its code. -i, The algorithm for issuing control actions can be represented by a transition table (Table 1).

1,000

2,001

100

Thats

010

oo

3 010

“2

Q on

(6

5 too

ten

011. 01

45

eight

9

6,101

23

22

g (

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; 110

26

47

UzUU; | ;;

ZjZ; Here, UzU (t) is the current code (t + 1) of the vertex), the subsequent code of the vertex of the graph (Fig.). In the initial position, the register 23 (FIG. 1) is zeroed at the reset input. If the initial state of the sensors ab are different from zero, then this source code in register 23 would be recorded when the programmed excitation of output 9-3 of the decoder 9 (initialization) through the element OR 13. At the same time, the corresponding code is output 00 (cell O table.1). Table 1 is built to prevent the simultaneous change of the state of two sensors at once. Table 1 is in the permanent memory of system block 6 at addresses that have the highest unit (A1 block 6 in Fig. 1), I Then, when the system responded To change the status of sensors ab 00-01, control will be transferred by the command: RST 11001111 (the third digit of the djdgd code, the RST 11 111 commands are connected to the minus power meter bus (and the remaining bits 7.6.2, 1.0 - to plus bus) - at the inputs of 3 eight memory locations with addresses (in octal code), oiooiOg- 010173 This unit means excitation of input A1 of block 6 by trigger output 20. In response to requests for inputs 35, this bit will be 0. The following eight cells contain commands: BOOL 1: PUSH PSW; preservation of the MVI C state, 01Hj assignment U code CALL CALL UPR; call the subroutine of the ZgZ, (UPR) FOP PSW; return the RET status word; return to the interrupted program; The control action program UPR is the following command sequence: UPR: PUSH H; save H, L PUSH B; save B, C LDA RAM; reading from cell PA code UzU2U1 (s) ORA С,; concatenation to obtain address () MVI H, 57; assignment to the register H code 57 1 5 MOV L, C; transfer L - “- C, in H, L - the address of cell 1 of table 1 MOV A, M; send to battery (t + D / XZ Z, located at H, L MOV B, A; temporarily store (t + 1) // Z2 Z, in B MOV A, B; send to A ANI MASK 1 ; highlight. OUT PORT 1; output Z2Z to port 1 MOV A, B send, (t + 1) // ANIMASK2, A, highlight UzUHUI +) STA PAM, write the new state to the PAM cell; restore B, C; restore H, L enable interrupt return (to the POP PSW command) o Thus, the UPR subroutine performs automatic mapping in accordance with Table 1. Before addressing it, the code of sensors ab (logical conditions of input 3) is recorded in register C (microprocessor 1), this code is contacted with the code stored in the RAM cell (state (table), at this address UzUV "() ab is extracted (t + 1), (concatenation of the numerator and denominator of the fraction (t + 1), -, I, tAOL.1). Some of this information — the output is highlighted by the mask MASK 1, containing units in bits and zeros in the remaining bits, and output to port 1 (outputs 33). The other part, (t4-l) - the next state of the graph vertex - is highlighted by the mask MASK 2, with the sticking unit in bits (t + 1) and zeros in the remaining bits is written to the RAM cell, i.e., a transition to the second vertex of the graph (phYgoA) is made. Oo o "will progress through the raff to vertices 3 and 4. In this case, the RST commands will be generated, the cells with the sequences being addressed; A command similar to BOOL 1, only the assignment to the register C is performed in accordance with the state ab. 1.10 ... When going from state three to state four, a control action 01 is generated. The resetting of the flip-flop 20 that shifts the permanent memory of block 6 occurs at the addresses of the RET commands (marked with an asterisk -tr in the BOOL 1 subroutine} caused by the commands RST 317, RST 327, RST 337. This triggers the output 5.3 of the decoder 5 and the trigger 20 is zeroed through the delay element 27, when these RET commands have already been executed and returned to the main program, interrupted by an interrupt. that the RST command forces the microprocessor 1 generate the same addresses of interrupt vectors both on inputs 3 and on inputs 35 and the separation of these vectors occurs by an excited output of the trigger 20 shifting the addresses of the permanent memory of block 6 (input A1 of block 6 in FIG. 1) with removing the offset will occur after executing the RET command — returning to the main program — th network., after its reliable reading into microprocessor 1 from block 6 with offset and further microprocessor reading of commands will be performed with the offset removed. In order to implement a sequential automaton (FIG.) In a known invention, the same UPR program is necessary. It is also possible to implement combinational logic in a simpler way than the described sequence.

Inputs 3 of the controller are connected to the photo-electric sensors abc

In comparison with the known one, the 5-shaft-code vector has a high speed. It is necessary to generate a positional code. For simplicity, it is considered that the XjXjX code is simply output to some output port for further processing. Then after zeroing in register 23 - zero code. When the code abc 001 arrives, an interrupt is generated by the command RST 317. The memory cell of block 6 is addressed with the address containing the leftmost unit, as described above: 01001 Оg. In eight cells 01 OOlOg-OIOOU, the following commands are written: GRAY 1: PUSH PSW saving the status word, MUI A, 001; assigning the value X, X2X 001 OUT PORT 2 to the battery; pin return PSW POP PSW; enable interrupt, return To register 23 through the element OR 13, a new value of the input signal is written after zeroing the trigger 20 "After issuing the x-jXj x 111 code on the abc 100 signal when the abc 000 signal is received, an RST 307 command is generated and the code, 000, It is assumed that an external start, not indicated in FIG. 1, initiates the initial start-up, the start of the microprocessor from some non-zero 291 (multi-alternative) reaction to a change in logical conditions, since such a change immediately leads to the interruption and formation of output signals. there is no such effect in the known reaction, and a change in the logical conditions is checked by software, which can, among other things, lead to the loss of information in some signal processing tasks in real time. The invention The device for software control of technological equipment, containing a clock generator, the reset and readiness inputs of which are respectively the reset and readiness inputs of the device, the clock synchronization input of the clock generator is connected to the microprocessor clock output, the clock inputs of which are reset clock outputs, reset and readiness outputs of a clock generator, the synchronization output of which is connected to the system synchronization input controller, the first group of information input-output of which is connected, respectively, to the group of input-output data of the microprocessor, the recording control output of which is connected to the recording control input of the system controller, the output control output of the microprocessor data is connected to the corresponding control inputs of the system controller, a constant block the memory of the programs, the bus driver of the RAM and to the first input of the first element I, the outputs of the microprocessor address through buffer allocators on Connected to the corresponding address inputs of the address decoder, program permanent storage unit, data operative memory unit and device input and output decoder, the address of the address decoder is connected to the output of the first OR element, the first and second inputs of which are connected respectively to the memory read control outputs and write to the memory of the system controller, the first output of the address decoder is connected to the resolution input of the program permanent memory unit, the second output of the address decoder under 5 is connected to the resolution input bus RAM driver and to the enable input of the data RAM block whose recording input is connected to the write control output to the memory of the system controller, the second group of information inputs-outputs of which are connected respectively to the information outputs of the program memory block, the group of information inputs and outputs of the bus driver of the RAM and the group of information inputs and outputs of the bus driver of the input-output devices, the information inputs of the opera block data memory is connected, respectively, to the second group of information inputs / outputs of the bus driver RAM, and information outputs of the RAM block are connected, respectively, to the third group of information inputs / outputs of the bus driver RAM, the enable input of the decoder input devices the output is connected to the output of the second OR element, the first and second inputs of which are connected to the control outputs of the input from input devices and output to the output device of the system the controller, respectively, the output group of the I / O device decoder is connected, respectively, to the enable input group of the bus driver of the I / O devices, the input enable input of which is connected to the input control output of the input devices of the system controller, the input driver bus inputs of the I / O devices are informational the device inputs, and its outputs - information device outputs, the output of the first element I is connected to the enable input of the bus driver, the reset inputs are registered tra and trigger are connected to the reset output of the clock generator, the register outputs are connected to the first group of information inputs of the equalization circuit, the output of which is connected to the first input of the second element I, the second input of which is connected to the trigger's output, the information input is cheaply connected to the corresponding bit of the second group of information the inputs / outputs of the system controller, the third OR element, is designed so that, in order to increase speed and expand the field of application, three elec- cient OR, two trigger priority encoder, a multiplexer, and a delay element, with the register clock input connected to the output of the third element. OR, the first input of which is connected to the second output of the I / O device decoder, and the second input - to the jBTOporo trigger output, to the address input of the multiplexer, the higher address input of the program memory block and the additional information input of the memory decoder, the third output of the decoder the address is connected to the input of the delay element, the output of which is connected to the first V input of the fourth OR element, the second inverse input of the fourth OR element is connected to the output of the first trigger, the third input of the fourth IL element And connected to the reset input of the second trigger, the input of the fourth element OR is connected to the reset input of the second trigger, the information input of which is connected to the output of the comparison circuit, and the synchronization input of which is connected to the interrupt confirmation output of the system controller, the synchronization input of the first trigger is connected to the third input the I / O device decoder, the information inputs of the register are connected, respectively, to the second group of information inputs of the comparison circuit and to the second group of multiplexer inputs are logic inputs

conditions of the device, the second input of the first element AND is connected to the confirmation output of the system controller interrupt, the third input of the second element AND is connected to the microprocessor synchronization output, and the fourth input of the second And element is connected to the microprocessor interrupt enable output, the output of the second And element is connected to the first, input n of the OR element, the second input of which is connected to the control output of the priority encoder, the inputs of the priority encoder are the inputs of the device interrupt requests, information The primary outputs of the priority encoder are connected to the first group of multiplexer inputs, the outputs of which are connected to the first group of information inputs of the bus driver, the second group of information inputs of which are connected to the outputs of the vector-transition command generator, the output of the fifth element OR is connected to the data input of the third trigger, the reset input of which connected to the output of the sixth element OR, the first, inverse input of the sewn element OR connected to the output of the microprocessor interrupt enablement, the second input of the sixth The first OR element is connected to the clock oscillator reset output, the third trigger output is connected to the microprocessor interrupt request input, and the third trigger synchronization input is connected to the corresponding clock generator clock output.

Interrupt it; TZ TZ 7J

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Claims (4)

Claim A device for software control of technological equipment, containing a clock generator, the reset and ready inputs of which are respectively the reset and ready inputs of the device, the clock synchronization input is connected to the microprocessor synchronization output, the clock inputs, the reset and ready inputs of which are connected to the corresponding clock outputs, reset outputs and the availability of the clock generator, the synchronization output of which is connected to the synchronization input of the system controller, first I am the 30th group of information inputs / outputs of which is connected, respectively, to the group of microprocessor data inputs and outputs, the recording control output of which is connected to the recording control input of the system controller, the microprocessor data reception control output is connected to the corresponding control inputs of the system controller, program read-only memory block, bus memory shaper and to the first input of the first element AND, the microprocessor address outputs through buffer amplifiers are connected to the corresponding m to the address inputs of the address decoder, read-only memory block, data RAM block and input / output device decoder, the address decoder enable input is connected to the output of the first OR element, the first and second inputs of which are connected respectively to the outputs for controlling the reading of memory and writing to the memory of the system controller, the first output of the address decoder is connected to the enable input of the read-only memory block, the second output of the address decoder is connected to the enable input of the bus driver of the available memory and to the enable input of the data RAM block, the recording input of which is connected to the write control output to the system controller memory, the second group of information inputs and outputs of which is connected respectively to the information outputs of the program read-only memory, the first group of information inputs and outputs of the bus driver RAM and to the group of information inputs and outputs of the bus driver of input-output devices, the information inputs of the RAM block are connected with accordingly, to the second group of information inputs / outputs of the bus RAM driver, and the information outputs of the RAM block are connected, respectively, to the third group of information inputs and outputs of the bus RAM driver, the enable input of the decoder of the input-output devices is connected to the output of the second OR element , the first and second inputs of which are connected to the outputs of the input control from input devices and output to the output device of the system controller, respectively, the group you The input of the input-output device decoder is connected, respectively, to the group of resolution inputs of the bus driver of the input-output devices, the input of the input of which is connected to the input control input from the input devices of the system controller, the inputs of the bus driver of the input-output devices are information inputs of the device, and its outputs - information outputs of the device, the output of the first element AND is connected to the enable input of the bus driver, the inputs of the reset register and trigger are connected to the reset output a clock generator, the outputs of the register are connected to the first group of information inputs of the comparison circuit, the output of which is connected to the first input of the second element AND, the second input of which is connected to the output of the trigger, the information input of which is connected to the corresponding category of the second group of information inputs and outputs of the system controller, the third element OR, O t l and s ^ ¹ 171 575 sistent in that, in order to improve performance and extend the scope of a device further administered three OR gates, two trigger Prior a tethered encoder, multiplexer and delay element, the register synchronization input being connected to the output of the third OR element, the first input of which is connected to the second output of the decoder of the input-output devices, and the second input is connected to the output of the second trigger, to the address input of the multiplexer, the oldest address input of the block a constant '15 program memory and an additional information input of the memory decoder, the third output of the address decoder is connected to the input of the delay element, the output of which is connected to the first input of the fourth element LEE, a second inverted input of the fourth OR gate is connected to the output of the first flip-flop ^ third fourth input of the OR element is connected to the reset input of the second trigge- ²⁵ pa, the fourth element is connected to the output of OR reset input of the second flip-flop having an information input coupled to an output of the comparison circuit, and the synchronization input of which 30 is connected to the output of the interrupt confirmation of the system controller, the synchronization input of the first trigger is connected to the third input of the decoder of the input-output devices, information 35 register inputs are connected, respectively, to the second group of information inputs of the comparison circuit and to the second group of inputs of the multiplexer and are inputs of the other logical conditions of the device, the second input of the first element And is connected to the confirmation output of the interrupt of the system controller, the third input of the second element And is connected to the synchronization output of the microprocessor, and the fourth input of the second AND element is connected to the output of the microprocessor interrupt enable, the output of the second AND element is connected to the first, input of the fifth OR element, the second input of which It is connected to the control output of the priority encoder, the inputs of the priority encoder are the requests for interrupting the device, the information outputs of the priority encoder are connected to the first group of inputs of the multiplexer, the outputs of which are connected to the first group of information inputs of the bus driver, the outputs of the command generator are connected to the second group of information inputs vector transition, the output of the fifth element OR is connected to the data input of the third trigger, the reset input of which is connected to the output of the sixth OR element, the first, inverse input of the sixth OR element is connected to the output of the microprocessor interrupt enable, the second input of the sixth OR is connected to the reset output of the clock generator, the output of the third trigger is connected to the input of the microprocessor interrupt request, the synchronization input of the third trigger is connected to the corresponding clock clock output " Interrupt 2.5 ^; '' 4.1 3.1 1.8 w 110 - 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