RU1815643C - Device for debugging programs for microcomputer - Google Patents

Abstract

The invention relates to computer technology and can be used to debug hardware and programs in real time. In order to increase productivity when debugging programs and expanding functionality, to a device containing an address setting block, an input data block and debugging modes, an address decoder, a break address block, a comparison circuit, the first and second AND elements, the OR element, ready, blocking triggers memory, interrupt request, reset, capture request, microprocessor, output data block and debug modes, bus data driver, bus address driver, multiplexer, debug RAM, three AND elements, direct memory access request trigger, register-latch of high address byte, four groups of three-stable keys, direct memory access controller, serial channel transceiver with corresponding set of communications. 5 ill. (L C

Description

The invention relates to computer technology and can be used for debugging equipment and programs in real time. And it can be widely used for debugging and operation of microprocessor systems and devices (both single-processor / multiprocessor).

The aim of the invention is to increase productivity when debugging programs and expand functionality due to the possibility of debugging eight- and sixteen bit microprocessors.

In FIG. 1 and 2 are a functional diagram of a program debugging device; Fig. 3 is a timing chart in

loading mode of information into the debugged device on the control microcomputer; Fig. 4 is a timing chart for reading a memory of a debugged device and its transmission to a control microcomputer; 5 is a timing diagram of a ROM programming.

The device (FIGS. 1, 2) contains ROM 1, address setting unit 2, stop address and debugging mode unit 3, input data and debugging mode unit 4, microprocessor 5. first and second elements AND 6. 7, comparison circuit 8, bus data shapers 9 and 10, address multiplexer 11, third and fourth address elements AND 12, 13, OR element 14. debugging memory unit 15, direct access request trigger 16.

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read-only trigger 17 of the direct memory access controller, standby trigger 18, lock memory trigger 19, reset trigger 20, interrupt request trigger 21, capture request trigger 22, the first group of 23 three-stable keys, latch register 24 high address bytes, the controller 25 direct memory access (DMA), fifth element 26, second group of three stable keys, block 28 of output data and debug modes, transceivers 29 of the IRPS serial channel, third and fourth groups 30, 31 of three stable keys, address decoder 32. The following signals are shown on bus SHU1: 33 — read signal, 34 — ROM select signal 1, 35 — memory signal of the output input device, 36 — block select signal 2.37 — write signal, 38 — block select signal 3, 3, 39 - block selection signal 4.40 - signal clock frequency of the controller, serial interface, 41 - interrupt request for direct memory access, 42 - clock frequency, 43 - reset, 44 - interrupt end request in direct access mode memory, 45 - interrupt request for transmission to the debug microcomputer, 46 - interrupt request for receiving inform from the debugging microcomputer, 47 — interrupt request for the programming mode of the EEPROM. 1, 48 — select signal of the controller 25 of the DAC, 49 — select signal of the controller 29 IRPS, 50 — select signal of the block 28, 51 set the trigger signal 16 of the direct access request, 52 — signal for setting the ready-for-ready trigger; 53 — signal for setting the ready-for-trigger 18. In addition to the internal bus ШУ1, the debugging device has an internal data bus ШД1 54 and an address bus ША1 55, as well as external buses for the address ША2, 56, data ЩД2 57, and control ШУ2 for connections to debugged microprocessor oystvu. On SHU2 the following signals are shown: signal Read memory 58, signal Sign of input / output commands 59, signal Interrupt confirmation 60, clock signal Start of cycle 61, signal Clock frequency 62, signal Ready 62, signal Memory lock 64, signal Reset 65, signal Memory record 66, interrupt request signal 67; Signal Capture Request 68, Signal Capture Confirmation 69.

The following signals are shown on the internal bus of the device: Setting the cyclic mode 70, Setting the stop mode at the specified address 71, Setting the interrupt request 72, Setting

reset 73, Set memory lock 74, Load RAM 75, Set direct access to memory 76, Program EPROM 77, Require capture 78.3 record

EEPROM 79, Prohibition of Extradition 80.

The communication device with the control microcomputer is implemented in the rank of interface IRPS 81.

ROM 1 and microprocessor 5 are designed to process the information stream.

containing address control commands and

data and coming from the manager

a microcomputer in accordance with a predetermined bench press set by the operator on the terminal keyboard. As a microprocessor element can be used element 1821 BM 85. The transceiver 29 serial

The Q channel is intended for communication of a debugging device with a control microcomputer and can be implemented on the basis of 580 V 51. The microcomputer decoder can be implemented on the basis of 580 V 51. The decoder 32 is designed to select programmatically controlled elements of the device.

Block 2 with a built-in timer and RAM is designed to read the address of the debugged device and fix the passage

0 of the program being debugged through the specified address with the formation of a control stop signal at this address in the search-wait mode. Block 3 is designed to specify the address of comparison and formation

5 two control signals stop by input / output commands, stop by interrupt. Block 4 with built-in timers and RAM is designed to read the data of the debugged device, generate service control signals and the clock frequency of block 29. Block 28 with a built-in timer and RAM is used to output information to SD2, generate control signals and interrupt request

5 when operating in operation in an EPROM programming mode. As blocks 2, 3, 4, 28 we use LSI 1821 R.U55. The keys 30. 31 with the third state are intended for pairing the block 25 with ШУ1 and ША1. Key 27 s

™ the third state provides the connection of block 28 to SD2. Element And 25 translates the text. Frequency 42 to the counting input of the ROM programming timer, which is part of block 28. Elements And 6.7 of the comparison circuit 8, element OR 14, ready trigger 18 is used to generate a ready signal 63 and depending on the selected debug mode. Tire formers 9, 10 for purpose5

started to interface SD1 and ША1 with RAM 15. Multiplexer 11 controls the connection of RAM 15 to either ША1, ШД1. SHU1, or SHA2.SCHD2.DU2.

The DAC controller 25 is designed to organize the exchange of information between the host microcomputer and the device being debugged. As a block 25, an LSI DAC 580 BT 57 is used. The And 13 element controls the availability trigger 1.7 of the DAP controller 25. Register 24 latches the high byte of the address generated by the controller 25 and provides it to ША2. The direct access request trigger 16 starts the controller 25 in the direct access memory exchange modes. The key 23 with the third state sets on LS2 the low byte of the address. Triggers 19, 20, 21, 22 are designed to generate control signals reset, memory lock, interrupt request, debug micro-computer request. As triggers, D triggers can be used.

The device in the process of debugging programs provides the following modes of operation:

debugging 8-bit microprocessor devices; .

debugging 16-bit microprocessor devices;

information exchange between the control microcomputer and the debugged device in the RAP mode;

work with debugging RAM;

programming ROM microprocessor devices;

resetting debugged microcomputers and their launch;

step-by-step program execution;

program stop at a given address and number of cycles;

interrupt stopping occurring in a debugged microprocessor device;

stopping by the ENTER or EXIT commands;

blocking the memory of the debugged microprocessor device;

interruption of the debugged microprocessor device specified through the debugging device.

The operating modes are set by the program debug microcomputer via blocks 4 and 28. The operation of the device begins with its initial installation by means of the RESET signal 65 of bus ШУ2 supplied from the debug microcomputer.

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0

The stage of selecting and assigning devices is carried out by a user who determines on which of the p system ranks the IRPS will be implemented

the interface of the control microcomputer with the debugging device (Fig. 1). The step of loading debugged programs into the memory of microprocessor devices is carried out by means of a control program

debug microcomputer. In this case, the debugging device according to the IRPS rank by the transceiver 29 of the serial channel receives a control command, the format of which determines the operating mode, as well as the starting and ending address of the loaded memory zone of the debugged device. When the output buffer is full, the transceiver 29 generates an RX RDY ready signal, which is an interrupt request signal 46 of the microprocessor 5. The microprocessor 5 switches to the request processing subroutine 46, reads the input register of the transceiver 5 and, in accordance with the control command information, performs setting program-controlled blocks 4, 28 and controller 25 of the RAP. At the same time. the processor 5 sets the signal to a single state setting direct access to the memory 76, thereby unlocking the RAP trigger 16. Upon completion of the process of setting up the debugging device for boot mode, data are transmitted via the IRPS channel, which must be loaded into the RAM of the device being debugged. When the data byte is received by the transceiver 29, an interrupt request 46 is generated, the microprocessor 5 switches to the information processing subroutine, reads the contents of the transceiver 29 into the accumulator, and sends the data byte to port A of block 28, where it latches. Then, by the command OUTPUT of the microprocessor 5, a control signal 51 is set to set the PDP trigger 16, which, by its output, transfers the direct access request input of the PDP controller 25 to the active state. In response to a direct request

0 access DRQ controller 25 DAP generates a HOLD signal request-capture, which is supplied to the D-input 22 and is clocked at a frequency of 62. The trigger 22 switches to another stable state and generates a signal on the SHU 2

° capture request 68. The microprocessor of the debugged device goes into the third. state and responds with a capture confirmation signal 69, received at the corresponding input of the DAC controller 25 and

turning the keys 30 and 31 into the third state, through which the write signals 37, read 33 and the low byte of address 55 from the microprocessor 5 pass when the controller is configured for the required operating mode. At the same time, the capture confirmation signal 69 opens the key 27, and the output data written to the port A of block 28 is sent to ЩД2, and the DAC controller 25 generates a signal of the address AS gate along the leading edge of which the address high byte and address resolution AEN are written, which register 24 and element 23 are opened. Thus, the address of the loadable RAM will be set on STA 2. In addition, the trigger 16 overturns by the leading edge of the address AS gate and the active level of the access request signal DRQ is removed from the corresponding input of the controller 25. Then, in accordance with the operating algorithm, the controller 25 generates a signal Write memory 66 to the control panel 2 at the set addresses and data on LUA2 and ST2. Thus, a single data cycle occurs in the RAM of the device being debugged. The controller 25 waits for the next byte of data to arrive on the IRPS channel 81, when the interrupt request 46 is again generated and the microprocessor 5 cocks the trigger 16. Using the trigger 16 allows synchronizing the relatively slow time by the IRPS exchange and the high-speed RAP mode. The exchange rate of the control microcomputer and the device being debugged 1 will be determined by the parameters of the IRPS channel 81. The timing diagram of the operation in the mode of recording information in the memory of the device being debugged is shown in FIG.

Information from the memory of the device being debugged to the host microcomputer is transmitted under the control program. At the same time, the debugging device via the IRPS channel by the transceiver 29 receives a control command, the format of which determines the operating mode, as well as the starting and ending memory addresses of the device being debugged.

Upon receipt of the control command by the transceiver 29, an interrupt request 46 is generated. The microprocessor 5 switches to the interrupt request processing routine 46, reads the input register of the transceiver 29, and, in accordance with the contents of the control command, sets the 4.28 blocks and the DAC controller 25 to the memory reading mode. moreover

port A of block 4 is configured for gated read mode when the input information is latched in the input buffer along the leading edge of the read signal

memory 58. In addition, the microprocessor 5 sets to a single state the direct access setting signal in the memory 76 and the prohibition signal 80, which is in the capture state ША2, ШД2. and ШУ2 blocks the transfer of the contents of block 28 through the key 27. Then, on the OUTPUT command, the microprocessor 5 sets the transceiver 29 to the transmission mode, and a transmit ready signal T X RDY is generated, which is an interrupt request 45. When it appears, a transition to the corresponding subprogram occurs in which, on the OUTPUT command, a control signal 51 for setting the trigger 16 of the RAP request is generated. The trigger 16, by its output, puts the DRQ input of the direct access request of the DAC controller 25 into active state. Then the controller 25 DPD forms

The HOLD REQUEST signal HOLD, which is supplied to the D input of the capture trigger 22 and is clocked at a frequency of 62. The trigger 22 switches to another stable state and informs the capture request signal 68 on the control unit 2.

The microprocessor 5 of the device being debugged goes into the third state and responds with a capture confirmation signal 69, which is sent to the DAC controller 25 and switches the keys 30 to the third state

31. through which control signals 37.33 and the low byte of address 55 from the microprocessor are received when the controller 25 of the DAC is configured for this operating mode. In accordance with the functioning algorithm, the DAC controller 25 generates an AS gate address signal, on the leading edge of which the high byte of the address and AEN address resolution, which opens register 24 and element 23, are written in block 4.

Thus, the address of the RAM being read will be set on SHA2. Then, the controller 25 sets the read signal of the memory 58 to the control unit 2 and, with its trailing edge, the data from the SD2 is latched into block 4. Block 4 sets

interrupt request 41, by which the microprocessor reads the corresponding port, executing the ENTER command, and by the command EXIT, the data byte is written to the transceiver 29 and received from it

signal readiness for transmission T X RDY, which is an interrupt request 45, by which the next read cycle of the memory of the device being debugged begins. End of exchange characterized by circulation

to the last memory address of the device being debugged, it is accompanied by the formation of the corresponding TC signal, which is supplied to one of the interrupt request inputs 44. Therefore, by request44, microprocessor 5 exits the exchange program via the direct access channel. The timing diagram of the operation in the mode of reading information from the memory of the debugged device is presented in Fig. 4.

The next step after downloading the program run is carried out either in continuous mode or in steps. The user from the keyboard of the video terminal dials the appropriate debugging directive, which is represented by a specific control command transmitted to the debugging device via the IRPS channel 81 and processed by microprocessor 5. The required mode of operation is determined by the state of port C of block 4, the information is recorded to it by signal 37. In this case, the internal control signal 74, which is received at the D-input of the trigger 19 of the memory lock and signal 73, is received at the D-input of the trigger 20 reset provide signals blocking memory 64 and reset 65 log level. O, In the case of continuous operation in port C of block 4 are set to log. О signals 70, 71 and two bits of port C of block 3, received by the I6 and I7 elements, as a result of which a log is sent from the output of the OR 14 element to the D-input of the ready trigger. About and a single signal SHU2 -63 readiness is formed.

When working in the mode of execution of the debugged program, the signal 70 is set to a single state, which, through the OR element 14, enters the D-input of the trigger 18. A signal 61 is received at the C-input - the beginning of the cycle. As a result, a ready signal 63 is generated. After which the device being debugged enters the standby state, the current data and address values will be located on SD2 and ША2. The microprocessor 5, on the ENTER command, reads the address block 2 and ports A and B of the data block 4, and then transmits their contents through the transceiver 29 to the control microcomputer. Running the program being debugged per step is carried out by setting the ready trigger 18 to a single state by supplying a control signal 53 to the P input.

The operation of the device in the run mode of work programs with a stop sign is determined by setting to

Native state of signals 71 - setting the stop mode to address, setting the stop mode by interrupt (received from port 6 of block 2 to element 6), setting the stop mode by the ENTER and OUTPUT commands (received from port C of block 2 to element 7 )

When debugging work programs with a stop by the ENTER and OUTPUT commands, the bit of port C of block 2 is sent to the single state, which is received at the first input of the And 7. element. At the second input of the And 7 element, the signal SHU2 59 receives, a sign of the I / O commands. Item output

«At | h connected to one of the four inputs of the element OR 14, the output of which will be set to the level of the log. 1 if there are INPUT and OUTPUT commands in the debugged program. In this case, a log is sent to the D-input of the ready trigger 18. Г and upon the arrival of the control signal ШУ2 61 the beginning of the command to the С-input of the trigger 18, a signal of readiness 63 with a log level will be generated. A. The device being debugged enters a standby state. On ША2 the address of the input / output device will be set, on ШД2 data read or written to the external device, in

depending on how the INPUT or OUTPUT command is executed.

Then, the microprocessor 5, on the ENTER command, reads ШД2 and ША2, respectively, through blocks 2, 4 and, through the transceiver 29, transfers them to the control microcomputer. The start of the program after stopping is carried out by reinstalling the ready trigger 18 by the control signal 53. When debugging work programs in the stop-by-break mode, the bit of the port C of the register is input to the first state of the element And 6. The second input of this element receives a signal SHU2 60 confirmation

interruptions. The output of the AND 6 element is connected to one of the four inputs of the OR element 14, at the output of which the log level will be set. 1 if there is confirmation in the debugged program

interruptions. In this case, a log is sent to the D-input of the ready trigger 18. 1st and upon the arrival of the control signal ШУ2 61 the beginning of the command to the C-input of the trigger, a signal 63 will be generated ready with a level of log. A. The device being debugged enters a standby state. On ША2 there will be an address of return to the debugged program upon completion of interrupt processing, on ШД2 - the command code

RESTART defining an interrupt vector. Reading tires ШД2 and ША2 is performed in the same way as in the INPUT and OUTPUT cycle.

When debugging work programs in the stop mode at the address, the microprocessor device enters the standby state when the program being debugged passes through the specified stop address the required number of cycles. For this purpose, the microprocessor 5 receives information containing the type of debug mode via the IRPS channel 81 in this case, stop at address, stop address and number of cycles). Then, by the ENTER command, a stop address is written to block 3, and its built-in timer is set to the required number of cycles for passing the given address. The mode is started by setting the control signal 71 to a single state, setting the stop mode to the given address of block 4. In this case, a comparison circuit 8 is opened, which compares the stop address recorded in block 3 with the current value ША2. If the addresses match, circuit 8 generates an equal signal. The output of element 8 is connected to the counting input of the subtraction of the timer of block 2, when the timer value becomes zero, i.e. the program will go through a predetermined number of cycles, a transfer signal is generated, which is fed to one of the inputs of the OR element 14, and the output of the OR element 14 is connected to the D-input of the ready trigger 18. Thus, the logical unit at the D-input of the trigger 18 provided that the timer of block 2 is zero. The ready trigger 18 will generate a ready signal 63 along the leading edge of the signal 61 of the beginning of the command going to the C input. The processor of the debugged device will go into a standby state. On SHA2 there will be a stop address, on SHA2 the data corresponding to this address. Microcomputer bus readings are performed in the same way as in previous shutdown modes.

In addition to signal conditioning, the device can also generate a reset signal 65, which is received by the debugged microcomputer. To do this, trigger 20. The control signal 73 is received at the D-input, which is set to the logical unit state through the corresponding bit of port M of block 4. The clock frequency 62 is received at the C-input of trigger 20. The reset is removed by applying it to the D-input trigger 20 of the zero signal 73 on the leading edge of the clock frequency 62.

The use of a trigger in a reset formation circuit is necessary so that the asynchronous signal generated in port C of block 4 is transferred to the time diagram of the operation of the smoothed microcomputer. For the same purpose of synchronizing control signals 72, 76, 74, an interrupt request trigger 21, a capture request trigger 22, and a memory lock trigger 19 are used.

In addition to the above, the program debugging device provides a mode of operation with debugging RAM 15, the necessity of which is due to the following reasons.

Debugging software for microprocessor devices involves running programs in real time and adjusting them based on the results of memory commands. Since debugged devices have ROMs in their composition, it is natural to debug programs in the ROM address area is not possible. To ensure operation in the required address zone, the device has debugging RAM, into which the working program is loaded from the control microcomputer via the IRPS channel 81, and then this RAM 15 is switched to the address, data and control buses of the microprocessor device and a memory blocking signal 64 is supplied. which disables the ROM, the place of which is occupied by the debugging RAM 15. When operating in the boot mode of the debugging RAM 15, the microprocessor 5 receives the control command containing the type of operation mode and decodes it via the IRPS channel 81. Then, in accordance with the specified mode, the command sets the control signal 78 to the capture demand by entering the corresponding bit of the port C of block 28 in a single state. The signal 78, which is received at the S input of the capture request trigger 22, sets the signal 68 to - capture request, as a result of which the microprocessor of the device being debugged enters the capture state and disconnects from ША2 and ШД2, which are connected to the corresponding inputs of the debugging RAM 15. The next ENTER command is set to single state control signal loading RAM 75 which opens conditioners data bus 9 and the address 10, when connected in this way RAM 15 to the internal data buses and SHD1

SHA1 addresses. By the same signal 75, the multiplexer 11 connects to the RAM 15 the senior addresses SHA1 and the write signal 37. Thus, the RAM 15 is connected to the internal buses SHD1, SHA1 and SHU1. Then, through the IRPS channel 81, the transceiver 29 receives an array of data that must be loaded into RAM 15. The microprocessor 5, upon interruption request 46, receives the incoming information and forms a write cycle to RAM 15. In order to prevent access to the RAM blocks at this time , 2, 3, 4, 28 the address fields and RAM 15 must be spaced apart. Upon completion of the exchange, the signal loading RAM 75 is again set to a logical zero state, bus drivers 9, 10 go into the third state and, as a result, ША1 and ШД1 are disconnected from RAM 15, and m ltipleksor 11 is switched on and SHA2 SHU2. Thus, the debugging RAM will be connected to the microprocessor device. In order for the user to work in this mode, it is necessary to set a single signal 74 memory lock and zero signal capture request 78 by the OUTPUT command with access to port C of block 28. In this case, the ROM of the microprocessor device is blocked and the microprocessor of the debugged device exits the capture, and instead of ROM, RAM 15 is connected.

The next step, after loading the work programs into the memory of the device being debugged, running them and adjusting them, consists in programming the ROM with ultraviolet erasure. In this case, the debugging device according to the IRPS rank by the transceiver 29 of the serial channel receives a control command, the format of which determines the operating mode, as well as the start and end address of the programmable ROM and generates an interrupt request 46, which arrives at the corresponding input of microprocessor 5. Microprocessor 5 goes to the processing routine interrupts and, in accordance with the control command code, configures the 4.328 program blocks and the RAP controller 25. Then, the built-in timer of block 28 is tuned to a time delay of 50 ms, which must be maintained in order to comply with the programming timing of the UV-erased ROM.

After transmitting the control command and setting the device to the programming mode via the IRPS,

sending an array of data from the control microcomputer to the RAM of blocks 4, 28. Then the microprocessor, having loaded the last byte of information into the memory, by the OUTPUT command latches the first byte into the port A of block 28 and sets the control signal to logic zero 76 setting direct access to the memory, thereby blocking the C input of the trigger 16 of the RAP request.

The next OUTPUT command generates a control signal 51, which is input to the S-input of flip-flop 16, which puts the direct-access request input DRQ of controller 26 into an active state. In response to the receipt of the direct access request, the controller 25 generates a HOLD capture request signal, which is supplied to the D-input of the trigger 22 and clocked at a frequency of 62. The trigger 22 generates a single capture request signal 68 to the controller. The microprocessor of the device being debugged is disconnected from ШД2, ДА2, ШУ2 and responds with a signal confirming capture 69, arriving at the corresponding

the input of the DAC controller 25 and transferring to the third state the elements 30.31 through which the write signals 37, read 33 and the low byte of address 55 from microprocessor 5 pass when the controller is set to

required operating mode.

At the same time, the capture confirmation signal 69 opens the element 27 and the data byte recorded in the port A of block 28 is sent to SD2, and the DAP controller generates the AS address strobe signals, on the leading edge of which the address high byte and the address resolution signal AEN are recorded, which register 24 and elements 23 are opened. Thus, the address of the programmable ROM will be set on SHA2.

Then, in accordance with the functioning algorithm, the controller with the exposed addresses and data on ША2 and ШД2

generates a signal 66, recording memory on the control 2. The leading edge of the strobe of the address AS through the element And 13 with a single signal 77, programming the EPROM is fed to the C-input of the trigger 17 of the controller’s readiness

25, the DAC, the latter, in turn, puts the controller 25 into the standby state by the output of the zero level, as a result of which the address and programming data are stored on ША2, ШД2, and the memory record is on signal ШУ2. At the same time, the output signal of the trigger 17 opens the I26 element and the clock frequency 37 is supplied to the counting input of the timer unit 28, configured for 50 ms. To comply

the programming time chart of the BIS EPROM with UV erasure, the microprocessor after at least 4 microseconds after issuing the control signal 51 by the OUTPUT command by setting a specific bit of port C of register 28, a signal 79 is written to the EPROM.

After the 50 ms required for

When programming the EPROM, the register timer generates a single pulse 47, which arrives at one of the interrupt request inputs of the microprocessor 5. The latter goes to the interrupt processing routine, removes the control signal 79, and the signal 52 sets the trigger ready. C. TIP through the triggers 16 17 brings the controller out of the wait cycle with the completion of the acquisition of buses ША2 and ШД2. The programming of the next memory cell is carried out according to the same algorithm with writing the next byte of information to port A of block 28. The timing diagram of this debug mode is shown in Fig. 5.

Operation with eight-bit or sixteen-bit microprocessor devices is determined by the user before starting debugging. In this case, the software-accessible ports of blocks 2, 3, 4, 28 are configured. For debugging eight-bit processors, ports A, B of blocks 2,3, ports A of blocks 4.28 are used. For debugging sixteen-bit processors, all ports in accordance with FIG. 1.

As a debug microcomputer, domestic microcomputer ISKRA 1030, S-1840, EC-1810 and others can be used together with service peripheral equipment. The standard software for these microcomputers for working with the proposed devices has been expanded with an additional command line interpreter and software monitor.

The command line interpreter analyzes console input (from the keyboard of the video terminal) and, depending on the entered information, transfers control to the bootloader of the operating system or boot of the software monitor.

When switching to the debugging mode of software, a program monitor is used, which allows working both with the program in debugged microcomputers and in the debugging microcomputer itself.

The procedures for executing the program monitor directives through the IRPS channel are sent to the debugging device, where they are analyzed and processed, providing input of information to the air-blast device, working with memory and input-output registers, and controlling the execution of programs of debugged microcomputers.

The program monitor allows the user to work on the following directives: filling the memory area with a constant, comparing two memory arrays, moving the memory array, calculating the checksum of the memory area, replacing the contents of the memory, outputting to the display device the contents of the memory area, starting and stopping the microprocessor at a given address, tracing the program, editing general purpose registers, reading memory with the OUTPUT of its contents in the control microcomputer, writing to the memory of the device being debugged CTBA information from the control microcomputer, the microcomputer being debugged installation rooms.

The proposed device, together with a debug microcomputer, allows for a full cycle of software development: compiling, correcting programs, debugging them on microcomputers and micro-processor devices. In addition to the above device. It has software and hardware flexibility. Thus, by inputting several devices, microprocessor systems are multi-program debugged, which increases the productivity of the program debugging process.

Given these capabilities, the proposed device allows for a complete software development process, as well as monitoring and diagnostics of microprocessor devices.

Claims (1)

Formula invented and A device for debugging microcomputer programs, comprising an address setting unit, an input data block and debug modes, an address decoder, a stop address and debug mode blocks, an output data block and debug modes, a comparison circuit, first and second AND elements, an OR element, ready triggers, memory lock, interrupt request, reset, and capture request, with the first address input of the address setting unit connected to the first low byte of the address bus of the debugged microcomputer, the second address input of the address setting unit connected to the second byte of the address line of the debugged microcomputer, the third address input of the address block of the microcomputer, the fourth address input of the block of the address set and the first address inputs of the input data block and debug modes, the stop address block and debug modes, the decoder the addresses and the block of output data and debug modes are connected to the internal address bus of the control microcomputer, the fifth and sixth inputs of the address set block, the second and third inputs of the block of input data and modes debugs are inputs of the device for connecting to the write and read outputs of the control bus of the host microcomputer, the second inputs of the stop address block and the block of output data and debug modes are inputs of the device for connecting to the write output of the control bus of the host microcomputer, the first the fourth outputs of the address decoder are connected respectively to the seventh input of the sample of the address setting block, the third input of the sample of the stop address block and debug modes, the third sample input of the block of output data and debug modes, the fourth input of the block of input data and debugging modes, the eighth input-output of the block of setting the address, the fifth input-output of the block of input data and debugging modes, the fourth inputs of the block of stop address and debugging modes, as well as the block of output data and debugging modes - the outputs of the device for connecting the control microcomputer to the data bus, the first, second and third outputs of the stop address block and debug modes form the stop address output for the Stop mode at the address that is connected to the first input of the comparison circuit, w The other input of the comparison circuit is the input of the device and is connected to the address bus of the debugged microcomputer, the output of the comparison circuit is connected to the input of the timer of the address setting unit operating in the subtracting mode, the output of which is connected to the first input of the OR element, the sixth input of the block of input data and debug modes is is the input of the least significant data byte of the corresponding bus of the debugged device, the seventh input of the block of input data and debug modes is the input of the highest byte of the data of the same name bus of the debugged microcomputer, the fourth , the output of the stop address block and debug modes sets the debug mode to Stop by interrupt and is connected to the first input the first element I. The fifth output of the stop address block and debug modes sets the debug mode Stop by input and output commands and is connected to the first input 5 of the second element And, the first output of the input data block and debug modes determines the step-by-step debug mode and is connected to the second input OR, the second output of the input data block and debug modes sets the Stop mode to the address and is connected to the third enable input of the comparison circuit, the third output of the input data block and debug modes sets the control signal Interrupt request and connected to the information input of the interrupt request trigger, the fourth output of the block of the input data block and debug modes sets the control signal P Reset and is connected to the information input of the reset trigger, the fifth output of the block of input data and debug modes sets the control signal of the Memory lock and is connected to the information 5 by the input of the memory lock trigger, the outputs of the memory lock trigger, interrupt request, reset and capture request are the outputs of the device for connecting to the inputs Q of the same name signals of the control bus of the debugged microcomputer, the synchronization inputs of the memory lock triggers, interrupt request, reset and capture request are connected to the input of the device connected to the clock output of the control bus of the debugged microcomputer, the second input of the first element And is the input of the device for connecting to the output of the confirmation of the interruption of the control bus of the debugged microcomputer, the output of the first element And is connected to the third input of the OR element, the second input of the second element And is the input of the device wa for connection to the output command feature 5 of the input / output of the control bus of the debugged microcomputer, the output of the second AND element is connected to the fourth input of the OR element, the output of the OR element is connected to the information input of the availability trigger. the clock input of the ready trigger is the input of the device for connecting to the signal output The start of the control bus cycle of the debugged microcomputer, the output of the ready trigger is the output 5 devices for connecting to the signal input Readiness of the control bus for the debugged microcomputer, the ninth input of the address block, the fifth input of the block of the stop address and debug modes, the eighth input of the block of input data and debug modes, and the fifth input of the block of output data and debug modes is connected to the input of the device for connecting to the output of the control signal The memory of the input / output device of the control microcomputer, characterized in that, in order to increase productivity when debugging programs and expand functionality due to the possibility debugging of eight- and sixteen-bit processors, a bus data driver, a bus address driver, an address multiplexer, a debug memory unit, a third AND element, a request trigger are introduced into the device direct access, the fourth element of And, the readiness trigger of the direct memory access controller, register-latch of the high byte of the address, the first-fourth of the group of three-stable keys, the direct memory access controller, the fifth element of And, the first inputs of the bus driver data and register-latch of the high byte of the address, as well as the first input-output of the direct memory access controller are connected by the input-output of the device for connecting to the internal data bus of the control microcomputer, the output of the timer of the block of output data and modes of debugging is the output of the device for connecting to the input of the first interrupt request of the internal control bus of the control microcomputer, the first inputs of the bus address generator, address multiplexer and the fourth group of three-stable keys are connected to the address bus of the control microcomputer, the first input of the third group of three-stable keys and the second input of the address the multiplexer connected to the input of the device for connecting to the recording output of the control bus of the control microcomputer, the second input of the third group of three-stable keys in is the input of the device for connecting to the read output of the control bus of the control microcomputer, the clock input of the controller of direct memory access and the first input of the fifth AND element are connected to the input of the device for connecting to the output of the same frequency of the control bus of the control microcomputer, p the fifth to eighth outputs of the address decoder are respectively connected to the sampling inputs of the direct access controller, to the first installation inputs of the direct memory access request trigger and the readiness trigger of the direct memory access controller, with the second installation input of the direct memory access request trigger and the installation input of the ready trigger, the first output of the block of the output data block and debug modes. defining RAM loading mode, connected to the second inputs of the bus data shapers, addresses and to the third input of the address multiplexer, the second output block of output data and debug modes, which determines the direct memory access setting mode, is connected to the first input of the third AND element, the third output of the block of output data and debug modes, 0 of the Programming EPROM mode is connected to the first input of the fourth AND element, the fourth output of the block of output data and debug modes is connected to the installation input of the capture request trigger, the fifth fifth output of the block of output bottom and debug modes is the output of the device for connecting the external bus to the ROM input of the ROM debug microcomputer control, sixth output of the prohibition of issuing 0 block of output data and debug modes is connected to the first input of the second group of three-stable keys, the output of the bus address former, the first and second outputs of the address multiplexer, the first 5, the input of the debugging memory block is connected to the external address bus of the debugged microcomputer, the output of the bus data former is connected to the second input of the debugging memory block and the external data bus 0 debugged microcomputer, the fourth input of the address multiplexer is connected to the sixth output of the input data block and debug modes and connected to the input of the device for connecting to the output of the external control bus of the debugged microcomputer 5, the fifth input of the address multiplexer is connected to the external address bus of the cast microcomputer, the third and the fourth outputs of the address multiplexer are connected to the third and fourth inputs of the debugging memory block, the output of the address strobe of the direct memory access controller is connected to the second input of the reg latch latches the high byte of the address and second 5 inputs of the third and fourth element AND, the output address resolution of the direct memory access controller is connected to the first input of the first group of three-stable keys and the third input of the register-latch 0 high byte, the output request for capturing the direct memory access controller is connected to the information input of the trigger for the capture request, the input for confirming the capture of the direct access controller for memory 5, the second inputs of the second and fourth groups of three-stable keys, the third input of the third group of three-stable keys are connected with the input of the device for connecting to the output of the confirmation of the capture of the external control bus of the debugged microcomputer, the input of the direct access controller of the memory of the recording memory is connected to the first output of the third group re-stable keys and the input of the device for connecting the external control bus of the debugged microcomputer to the same name, the input of the direct memory access controller is connected to the second output of the third group of three-stable keys and the input of the device for connecting the external control bus of the debugable microcomputer to the same name, the output of the readiness trigger the direct memory access controller is connected to the readiness input of the direct memory access controller and the second input of the fifth AND element, the output of which is connected to about the counting input of the timer block of the output data and debug modes, the seventh and eighth outputs of the block of output data and debug modes form the output of a sixteen-bit information word that is connected to the third input of the second group of three-stable keys, the fourth and fifth inputs of the second group of three-stable keys are inputs devices for connecting to the outputs of memory lock and confirming the interruption of the external control bus of the debugged microcomputer, the output of the second group of three-stable keys is the output of the device -OPERATION input for connection to the external data bus microcomputer debugged. the output of the third AND element is connected to the clock input of the direct memory access request trigger, the output of the fourth element And is connected to the clock input of the readiness trigger of the direct memory access controller, the outputs of the first group of three-stable keys and the latch register of the high address byte are the outputs devices for connecting to the external bus inputs the addresses of the debugged microcomputer, the output of the fourth group of three-stable keys is connected to the address input of the direct memory access controller and the second by the input of the first group of three-stable keys, the output of the direct access request trigger is connected to the input request of the direct memory access controller, the output of the end of which is the output of the device for connecting to the input of the second interrupt request the internal control bus of the control microcomputer, the seventh output of the input block data and debug modes is the output of the device for connecting to the input of the third interrupt request the internal control bus of the control microcomputer, the eighth output and the ninth input of the input data block and debugging modes, the ninth and tenth outputs of the address decoder are connected to the outputs of the device for connection to the internal control bus of the control microcomputer. Figure 1 w: T & SStiSSS ™ 1 - / --- Reading the first faufrtef FIG. 4 Reading Second Byte 5 3 g SI